ENGR00244769-2 [NOR FLASH]-Improve WEIM NOR speed

Increase the NOR flash read speed.
Added weimnor driver to use cached (and page mode) reads.

Signed-off-by: Oliver Brown <oliver.brown@freescale.com>

diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig
index fc897eddcfa3b5b942836ce14f26c859a50f6c4d..3b2d31e4c4d2ae047ca7b826b864d1e5809d4767 100644 (file)
--- a/arch/arm/configs/imx6_defconfig
+++ b/arch/arm/configs/imx6_defconfig
@@ -301,6 +301,7 @@ CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
 # CONFIG_ARCH_MX503 is not set
 # CONFIG_ARCH_MX51 is not set
 CONFIG_ARCH_MX6=y
+# CONFIG_MACH_IMX_BLUETOOTH_RFKILL is not set
 CONFIG_ARCH_MX6Q=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_SOC_IMX6Q=y
@@ -752,8 +753,8 @@ CONFIG_MTD_CFI_UTIL=y
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_IMX6X_WEIMNOR=y
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -1099,6 +1100,7 @@ CONFIG_TOUCHSCREEN_MAX11801=y
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_NOVATEK is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2005 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
@@ -1957,6 +1959,7 @@ CONFIG_USB_OTG=y
 #
 # CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
+# CONFIG_FSL_USB_TEST_MODE is not set
 CONFIG_USB_EHCI_ARC=y
 CONFIG_USB_EHCI_ARC_OTG=y
 # CONFIG_USB_EHCI_ARC_HSIC is not set

diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index 4222730bbaba51682a550c0532f520f9d616eed4..f028fa82830407c7404af357450f72956d97cec0 100644 (file)
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -438,6 +438,7 @@ static struct spi_board_info m25p32_spi0_board_info[] __initdata = {
                .platform_data  = &m25p32_spi_flash_data,
        },
 };
+
 static void spi_device_init(void)
 {
        spi_register_board_info(m25p32_spi0_board_info,
@@ -478,8 +479,8 @@ static struct physmap_flash_data nor_flash_data = {
        .nr_parts       = ARRAY_SIZE(mxc_nor_partitions),
 };
 
-static struct platform_device physmap_flash_device = {
-       .name   = "physmap-flash",
+static struct platform_device imx6x_weimnor_device = {
+       .name   = "imx6x-weimnor",
        .id     = 0,
        .dev    = {
                .platform_data = &nor_flash_data,
@@ -493,15 +494,45 @@ static void mx6q_setup_weimcs(void)
        unsigned int reg;
        void __iomem *nor_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);
        void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);
+       struct clk *clk;
+       u32 rate;
 
-       /*CCM_BASE_ADDR + CLKCTL_CCGR6*/
+       /* CLKCTL_CCGR6: Set emi_slow_clock to be on in all modes */
        reg = readl(ccm_reg + 0x80);
        reg |= 0x00000C00;
        writel(reg, ccm_reg + 0x80);
 
-       __raw_writel(0x00620081, nor_reg);
-       __raw_writel(0x1C022000, nor_reg + 0x00000008);
+       /* Timing settings below based upon datasheet for M29W256GL7AN6E
+          These setting assume that the EIM_SLOW_CLOCK is set to 132 MHz */
+       clk = clk_get(NULL, "emi_slow_clk");
+       if (IS_ERR(clk))
+               printk(KERN_ERR "emi_slow_clk not found\n");
+
+       rate = clk_get_rate(clk);
+       if (rate != 132000000)
+               printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"
+                      " WEIM NOR timing may be incorrect!\n");
+
+       /* EIM_CS0GCR1: 16-bit port on DATA[31:16],  Burst Length 8 words,
+          Chip select enable is set */
+       __raw_writel(0x00020181, nor_reg);
+
+       /* EIM_CS0GCR2: Address hold time is set to cycle after ADV negation */
+       __raw_writel(0x00000001, nor_reg + 0x00000004);
+
+       /* EIM_CS0RCR1: RWSC = 9 EIM Clocks, ADV Negation = 2 EIM Clocks,
+          OE Assertion = 2 EIM Clocks */
+       __raw_writel(0x0a022000, nor_reg + 0x00000008);
+
+       /* EIM_CS0RCR2: APR = Page read enabled, PAT = 4 EIM Clocks */
+       __raw_writel(0x0000c000, nor_reg + 0x0000000c);
+
+       /* EIM_CS0WCR1: WWSC = 8 EIM Clocks, WADVN = 1,  WBEA = 1, WBEN = 1,
+          WEA = 1, WEN = 1  */
        __raw_writel(0x0804a240, nor_reg + 0x00000010);
+
+       /* EIM_WCR: WDOG_EN = 1, INTPOL = 1  */
+       __raw_writel(0x00000120, nor_reg + 0x00000090);
 }
 
 static int max7310_1_setup(struct i2c_client *client,
@@ -1581,12 +1612,12 @@ static void __init mx6_board_init(void)
        }
        /* SPI */
        imx6q_add_ecspi(0, &mx6q_sabreauto_spi_data);
-               if (spinor_en)
-                       spi_device_init();
-               else if (weimnor_en) {
-                       mx6q_setup_weimcs();
-                       platform_device_register(&physmap_flash_device);
-               }
+       if (spinor_en)
+               spi_device_init();
+       else if (weimnor_en) {
+               mx6q_setup_weimcs();
+               platform_device_register(&imx6x_weimnor_device);
+       }
        imx6q_add_mxc_hdmi(&hdmi_data);
 
        imx6q_add_anatop_thermal_imx(1, &mx6q_sabreauto_anatop_thermal_data);