MLK-9772-2 ARM: dts: imx6qdl-sabresd: add camera ov564x support

Add ov5640 support

Signed-off-by: Robby Cai <r63905@freescale.com>

diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index d133c0906dc65f9452b16ffd31d3dc6f75902924..5d9b38060067e7c08f2c8ec0e3319cfd4b5d7e65 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -214,6 +214,22 @@
                status = "okay";
        };
 
+       v4l2_cap_0 {
+               compatible = "fsl,imx6q-v4l2-capture";
+               ipu_id = <0>;
+               csi_id = <0>;
+               mclk_source = <0>;
+               status = "okay";
+       };
+
+       v4l2_cap_1 {
+               compatible = "fsl,imx6q-v4l2-capture";
+               ipu_id = <0>;
+               csi_id = <1>;
+               mclk_source = <0>;
+               status = "okay";
+       };
+
        v4l2_out {
                compatible = "fsl,mxc_v4l2_output";
                status = "okay";
@@ -301,6 +317,24 @@
                interrupts = <18 8>;
                interrupt-route = <1>;
        };
+
+       ov564x: ov564x@3c {
+               compatible = "ovti,ov564x";
+               reg = <0x3c>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ipu1_2>;
+               clocks = <&clks IMX6QDL_CLK_CKO>;
+               clock-names = "csi_mclk";
+               DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+               AVDD-supply = <&vgen3_reg>;  /* 2.8v, on rev C board is VGEN3,
+                                               on rev B board is VGEN5 */
+               DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+               pwn-gpios = <&gpio1 16 1>;   /* active low: SD1_DAT0 */
+               rst-gpios = <&gpio1 17 0>;   /* active high: SD1_DAT1 */
+               csi_id = <0>;
+               mclk = <24000000>;
+               mclk_source = <0>;
+       };
 };
 
 &i2c2 {
@@ -609,6 +643,23 @@
                        >;
                };
 
+               pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
+                       fsl,pins = <
+                               MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
+                               MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
+                               MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
+                               MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
+                               MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
+                               MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
+                               MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
+                               MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
+                               MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+                               MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
+                               MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
+                               MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
+                       >;
+               };
+
                pinctrl_pwm1: pwm1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1