ARM: dts: apq8064: Add ADM configuration node

Add Application Data Mover (DMA) device node.
Connect GSBI6 UARTDM RX and TX channels to it.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 90552dc217f4d3fb864f011307b5e69ebae7e29f..4b90df1390b9a78c068bfaae9fac820fca724652 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -264,6 +264,10 @@
                        };
                };
 
+               adm: dma@18320000 {
+                       status = "okay";
+               };
+
                sata_phy0: phy@1b400000 {
                        status = "okay";
                };

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 60b9b9aa0dafeeb187dbc931716f009486f9ab21..d2768d0ee890737b42b2f073067374f3ea85d55a 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -971,6 +971,7 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
+                       syscon-tcsr = <&tcsr>;
 
                        gsbi6_serial: serial@16540000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
@@ -979,6 +980,13 @@
                                interrupts = <0 156 0x0>;
                                clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
                                clock-names = "core", "iface";
+
+                               qcom,rx-crci = <11>;
+                               qcom,tx-crci = <6>;
+
+                               dmas = <&adm 6>, <&adm 7>;
+                               dma-names = "rx", "tx";
+
                                status = "disabled";
                        };
                };
@@ -1380,6 +1388,26 @@
                        };
                };
 
+               adm: dma@18320000 {
+                       compatible = "qcom,adm";
+                       reg = <0x18320000 0xE0000>;
+                       interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
+                       #dma-cells = <1>;
+
+                       clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+                       clock-names = "core", "iface";
+
+                       resets = <&gcc ADM0_RESET>,
+                                <&gcc ADM0_PBUS_RESET>,
+                                <&gcc ADM0_C0_RESET>,
+                                <&gcc ADM0_C1_RESET>,
+                                <&gcc ADM0_C2_RESET>;
+                       reset-names = "clk", "pbus", "c0", "c1", "c2";
+                       qcom,ee = <1>;
+
+                       status = "disabled";
+               };
+
                tcsr: syscon@1a400000 {
                        compatible = "qcom,tcsr-apq8064", "syscon";
                        reg = <0x1a400000 0x100>;