]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
drm/radeon: adjust default dispclk on DCE6 (v2)
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 18 Jun 2014 15:46:35 +0000 (11:46 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 1 Jul 2014 15:16:08 +0000 (11:16 -0400)
Set the default to 600Mhz if it's not set in the bios,
and bump the default to 600Mhz if it's lower than that.

This fixes display issues with certain 4k DP monitors when
using 5.4 Ghz DP clocks.

v2: fix typo.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_atombios.c

index 30844814c25a3c931a286b6823b54c88a0bbf348..173f378428a96d477eddf937e7bdd3d46fd222a6 100644 (file)
@@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                        rdev->clock.default_dispclk =
                                le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
                        if (rdev->clock.default_dispclk == 0) {
-                               if (ASIC_IS_DCE5(rdev))
+                               if (ASIC_IS_DCE6(rdev))
+                                       rdev->clock.default_dispclk = 60000; /* 600 Mhz */
+                               else if (ASIC_IS_DCE5(rdev))
                                        rdev->clock.default_dispclk = 54000; /* 540 Mhz */
                                else
                                        rdev->clock.default_dispclk = 60000; /* 600 Mhz */
                        }
+                       /* set a reasonable default for DP */
+                       if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
+                               DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
+                                        rdev->clock.default_dispclk / 100);
+                               rdev->clock.default_dispclk = 60000;
+                       }
                        rdev->clock.dp_extclk =
                                le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
                        rdev->clock.current_dispclk = rdev->clock.default_dispclk;