ENGR00324668 mmc: core: add delay for SD3.0 UHS mode switch

We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
 mmcblk0: unable to read partition table

The root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.

So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.

Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit ef3bce5feb2ed36c9f4483287454d35ae330dbe3)
(cherry picked from commit c0cbde8a248036fae1768f232385290c23eddbd7)
(cherry picked from commit 138bab9f78ea2285b6e7c7cd6c8cd956def44003)

diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 692fdb177294c242f3df6c9e1313df0584f100b3..569972f45c0d0c734764a65ca52e905525d8a670 100644 (file)
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -522,6 +522,13 @@ static int sd_set_bus_speed_mode(struct mmc_card *card, u8 *status)
        else {
                mmc_set_timing(card->host, timing);
                mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr);
+
+               /*
+                * FIXME: Sandisk SD3.0 cards DDR50 mode requires such
+                * delay to get stable, without this delay we may encounter
+                * CRC errors after switch to DDR50 mode
+                */
+               mmc_delay(100);
        }
 
        return 0;