]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
powerpc/mpc83xx: Fix usb mux setup for mpc834x
authorPeter Korsgaard <jacmet@sunsite.dk>
Tue, 9 Jun 2009 11:43:32 +0000 (13:43 +0200)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 16 Jun 2009 02:45:31 +0000 (21:45 -0500)
usb0 and usb1 mux settings in the sicrl register were swapped (twice!)
in mpc834x_usb_cfg(), leading to various strange issues with fsl-ehci
and full speed devices.

The USB port config on mpc834x is done using 2 muxes: Port 0 is always
used for MPH port 0, and port 1 can either be used for MPH port 1 or DR
(unless DR uses UTMI phy or OTG, then it uses both ports) - See 8349 RM
figure 1-4..

mpc8349_usb_cfg() had this inverted for the DR, and it also had the bit
positions of the usb0 / usb1 mux settings swapped. It would basically
work if you specified port1 instead of port0 for the MPH controller (and
happened to use ULPI phys), which is what all the 834x dts have done,
even though that configuration is physically invalid.

Instead fix mpc8349_usb_cfg() and adjust the dts files to match reality.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/asp834x-redboot.dts
arch/powerpc/boot/dts/mpc8349emitx.dts
arch/powerpc/boot/dts/mpc834x_mds.dts
arch/powerpc/boot/dts/sbc8349.dts
arch/powerpc/platforms/83xx/mpc83xx.h
arch/powerpc/platforms/83xx/usb.c

index 7da84fd7be93faf176058dd51e6f022f1dca5bf8..261d10c4534bae5bbeae07414056a8987be1bce4 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
index e3eeaeda91876e037561277baef3d22170dc6f93..feeeb7f9d6091031825dfc2f477ebe785b9d1f26 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
 
                usb@23000 {
index a2553a6f90096bdc179c09b4877b8544df47bcdd..230febb9b72f81a01ed6bfe9b55f7b88dae25ba2 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
index 5fb6f6684b0eda8b724c2b4c2f741f3ba59b020c..2d9fa68f641cec3c551b54a8059ebdac428094df 100644 (file)
                        interrupt-parent = <&ipic>;
                        interrupts = <39 0x8>;
                        phy_type = "ulpi";
-                       port1;
+                       port0;
                };
                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                usb@23000 {
index 83cfe51526ec26a5219ccb458dc0e56c1e996538..d1dc5b0b4fbfac991beb22578cb99cb559ae3238 100644 (file)
@@ -22,8 +22,8 @@
 /* system i/o configuration register low */
 #define MPC83XX_SICRL_OFFS         0x114
 #define MPC834X_SICRL_USB_MASK     0x60000000
-#define MPC834X_SICRL_USB0         0x40000000
-#define MPC834X_SICRL_USB1         0x20000000
+#define MPC834X_SICRL_USB0         0x20000000
+#define MPC834X_SICRL_USB1         0x40000000
 #define MPC831X_SICRL_USB_MASK     0x00000c00
 #define MPC831X_SICRL_USB_ULPI     0x00000800
 #define MPC8315_SICRL_USB_MASK     0x000000fc
index 11e1fac17c7ffff030aeba316051c062bafd0da4..3ba4bb7d41bb0d8f3905d5f9123d992b47872371 100644 (file)
@@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void)
                sccr |= MPC83XX_SCCR_USB_DRCM_11;  /* 1:3 */
 
                prop = of_get_property(np, "phy_type", NULL);
+               port1_is_dr = 1;
                if (prop && (!strcmp(prop, "utmi") ||
                                        !strcmp(prop, "utmi_wide"))) {
                        sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
                        sicrh |= MPC834X_SICRH_USB_UTMI;
-                       port1_is_dr = 1;
+                       port0_is_dr = 1;
                } else if (prop && !strcmp(prop, "serial")) {
                        dr_mode = of_get_property(np, "dr_mode", NULL);
                        if (dr_mode && !strcmp(dr_mode, "otg")) {
                                sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
-                               port1_is_dr = 1;
+                               port0_is_dr = 1;
                        } else {
-                               sicrl |= MPC834X_SICRL_USB0;
+                               sicrl |= MPC834X_SICRL_USB1;
                        }
                } else if (prop && !strcmp(prop, "ulpi")) {
-                       sicrl |= MPC834X_SICRL_USB0;
+                       sicrl |= MPC834X_SICRL_USB1;
                } else {
                        printk(KERN_WARNING "834x USB PHY type not supported\n");
                }
-               port0_is_dr = 1;
                of_node_put(np);
        }
        np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");