drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 7e1206d1df6ac0e6164fa96ad2c332ded6bfdce3..aa04632523fa8e4457d0674804d8eef98e6faf10 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -34,7 +34,7 @@
 
 u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
-        u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0));
+        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
        tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
        tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -45,32 +45,32 @@ u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
                                        uint32_t idx)
 {
-       return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx);
+       return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
 }
 
 void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
                                         uint32_t idx, uint32_t val)
 {
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val);
+       WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
 }
 
 void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
        if (enable)
-               WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN),
+               WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
                        BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
        else
-               WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0);
+               WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
 }
 
 void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
 {
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+       WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
 u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
 {
-       return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_CONFIG_MEMSIZE));
+       return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
 }
 
 static const u32 nbio_sdma_doorbell_range_reg[] =
@@ -96,21 +96,13 @@ void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
 void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
                                        bool enable)
 {
-       u32 tmp;
-
-       tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0,  mmRCC_DOORBELL_APER_EN));
-       if (enable)
-               tmp = REG_SET_FIELD(tmp,  RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
-       else
-               tmp = REG_SET_FIELD(tmp,  RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
-
-       WREG32(SOC15_REG_OFFSET(NBIO, 0,  mmRCC_DOORBELL_APER_EN), tmp);
+       WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 }
 
 void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
                                bool use_doorbell, int doorbell_index)
 {
-       u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE));
+       u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 
        if (use_doorbell) {
                ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
@@ -118,15 +110,15 @@ void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
        } else
                ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range);
+       WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 }
 
 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
 {
        uint32_t data;
 
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
-       data = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA));
+       WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
+       data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
 
        return data;
 }
@@ -134,8 +126,8 @@ static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_
 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
                                       uint32_t data)
 {
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA), data);
+       WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
+       WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
 }
 
 void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
@@ -182,15 +174,15 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
        u32 interrupt_cntl;
 
        /* setup interrupt control */
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8);
-       interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL));
+       WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
+       interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
        /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
         * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
         */
        interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
        /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
        interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
-       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl);
+       WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 }
 
 struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;