drm/i915: Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on...

commit 8faf3b317471179c02db339aa80955a2e88c036d upstream.

Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e7e521ac4dab76a293b00923e8d657b6e72ad2b..d02016dc77dc219b79221d89845d902d759d1d34 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1473,6 +1473,10 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
        int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
        u32 temp;
        int tries = 5, j, n;
+       u32 pipe_bpc;
+
+       temp = I915_READ(pipeconf_reg);
+       pipe_bpc = temp & PIPE_BPC_MASK;
 
        /* XXX: When our outputs are all unaware of DPMS modes other than off
         * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1504,6 +1508,12 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                        /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
                        temp = I915_READ(fdi_rx_reg);
+                       /*
+                        * make the BPC in FDI Rx be consistent with that in
+                        * pipeconf reg.
+                        */
+                       temp &= ~(0x7 << 16);
+                       temp |= (pipe_bpc << 11);
                        I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
                                        FDI_SEL_PCDCLK |
                                        FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
@@ -1644,6 +1654,12 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                        /* enable PCH transcoder */
                        temp = I915_READ(transconf_reg);
+                       /*
+                        * make the BPC in transcoder be consistent with
+                        * that in pipeconf reg.
+                        */
+                       temp &= ~PIPE_BPC_MASK;
+                       temp |= pipe_bpc;
                        I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
                        I915_READ(transconf_reg);
 
@@ -1722,6 +1738,9 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                I915_READ(fdi_tx_reg);
 
                temp = I915_READ(fdi_rx_reg);
+               /* BPC in FDI rx is consistent with that in pipeconf */
+               temp &= ~(0x07 << 16);
+               temp |= (pipe_bpc << 11);
                I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
                I915_READ(fdi_rx_reg);
 
@@ -1765,7 +1784,12 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                                }
                        }
                }
-
+               temp = I915_READ(transconf_reg);
+               /* BPC in transcoder is consistent with that in pipeconf */
+               temp &= ~PIPE_BPC_MASK;
+               temp |= pipe_bpc;
+               I915_WRITE(transconf_reg, temp);
+               I915_READ(transconf_reg);
                udelay(100);
 
                /* disable PCH DPLL */