]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: dts: orion5x: Configure WNR854T ethernet PHY LEDs
authorJamie Lentin <jm@lentin.co.uk>
Sat, 6 Aug 2016 10:10:13 +0000 (11:10 +0100)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Wed, 14 Sep 2016 15:00:26 +0000 (17:00 +0200)
The default PHY configuration disables most of the LEDs. The following
configures the ethernet activity LEDs as Netgear intended.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm/boot/dts/orion5x-netgear-wnr854t.dts

index 86a3cb1610ee3ac7df2cd1ce8f3055dab40ee839..9f6ae4e1de06be9fa8d7bca20d82bba0db3850a1 100644 (file)
                        port@0 {
                                reg = <0>;
                                label = "lan3";
+                               phy-handle = <&lan3phy>;
                        };
 
                        port@1 {
                                reg = <1>;
                                label = "lan4";
+                               phy-handle = <&lan4phy>;
                        };
 
                        port@2 {
                                reg = <2>;
                                label = "wan";
+                               phy-handle = <&wanphy>;
                        };
 
                        port@3 {
                                reg = <3>;
                                label = "cpu";
+                               ethernet = <&ethport>;
                        };
 
                        port@5 {
                                reg = <5>;
                                label = "lan1";
+                               phy-handle = <&lan1phy>;
                        };
 
                        port@7 {
                                reg = <7>;
                                label = "lan2";
+                               phy-handle = <&lan2phy>;
+                       };
+               };
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       lan3phy: ethernet-phy@0 {
+                               /* Marvell 88E1121R (port 1) */
+                               compatible = "ethernet-phy-id0141.0cb0",
+                                            "ethernet-phy-ieee802.3-c22";
+                               reg = <0>;
+                               marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+                       };
+
+                       lan4phy: ethernet-phy@1 {
+                               /* Marvell 88E1121R (port 2) */
+                               compatible = "ethernet-phy-id0141.0cb0",
+                                            "ethernet-phy-ieee802.3-c22";
+                               reg = <1>;
+                               marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+                       };
+
+                       wanphy: ethernet-phy@2 {
+                               /* Marvell 88E1121R (port 1) */
+                               compatible = "ethernet-phy-id0141.0cb0",
+                                            "ethernet-phy-ieee802.3-c22";
+                               reg = <2>;
+                               marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+                       };
+
+                       lan1phy: ethernet-phy@5 {
+                               /* Marvell 88E1112 */
+                               compatible = "ethernet-phy-id0141.0cb0",
+                                            "ethernet-phy-ieee802.3-c22";
+                               reg = <5>;
+                               marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+                       };
+
+                       lan2phy: ethernet-phy@7 {
+                               /* Marvell 88E1112 */
+                               compatible = "ethernet-phy-id0141.0cb0",
+                                            "ethernet-phy-ieee802.3-c22";
+                               reg = <7>;
+                               marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
                        };
                };
        };