drm/i915/gen9+: Program watermarks as a separate step during evasion, v3.

The watermark updates for SKL style watermarks are no longer done
in the plane callbacks, but are now called in a separate watermark
update function that's called during the same vblank evasion,
before the plane updates.

This also gets rid of the global skl_results, which was required for
keeping track of the current atomic commit.

Changes since v1:
- Move line unwrap to correct patch. (Lyude)
- Make sure we don't regress ILK watermarks. (Matt)
- Rephrase commit message. (Matt)
Changes since v2:
- Fix disable watermark check to use the correct way to determine single
  step watermark support.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lyude <cpaul@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478609742-13603-3-git-send-email-maarten.lankhorst@linux.intel.com
[mlankhorst: Small whitespace fix in skl_initial_wm]

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 194f0fda3a9f34588c040ebd3684a9e3d87b0358..12f004e5d71fb8d8b83bbf8704d925cd00e8ea66 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2047,13 +2047,6 @@ struct drm_i915_private {
                 */
                uint16_t skl_latency[8];
 
-               /*
-                * The skl_wm_values structure is a bit too big for stack
-                * allocation, so we keep the staging struct where we store
-                * intermediate results here instead.
-                */
-               struct skl_wm_values skl_results;
-
                /* current hardware state */
                union {
                        struct ilk_wm_values hw;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 218d1f461d9b69a30aa9e2d4867e16886b8de6e5..a5f75e19af80eed41e438046f54e45c5db2b7f74 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3391,9 +3391,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_framebuffer *fb = plane_state->base.fb;
-       const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
-       const struct skl_plane_wm *p_wm =
-               &crtc_state->wm.skl.optimal.planes[0];
        int pipe = intel_crtc->pipe;
        u32 plane_ctl;
        unsigned int rotation = plane_state->base.rotation;
@@ -3429,9 +3426,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
        intel_crtc->adjusted_x = src_x;
        intel_crtc->adjusted_y = src_y;
 
-       if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
-               skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
-
        I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
        I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
        I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
@@ -3464,18 +3458,8 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
-       const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
        int pipe = intel_crtc->pipe;
 
-       /*
-        * We only populate skl_results on watermark updates, and if the
-        * plane's visiblity isn't actually changing neither is its watermarks.
-        */
-       if (!crtc->primary->state->visible)
-               skl_write_plane_wm(intel_crtc, p_wm,
-                                  &dev_priv->wm.skl_results.ddb, 0);
-
        I915_WRITE(PLANE_CTL(pipe, 0), 0);
        I915_WRITE(PLANE_SURF(pipe, 0), 0);
        POSTING_READ(PLANE_SURF(pipe, 0));
@@ -10865,16 +10849,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
-       const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
-       const struct skl_plane_wm *p_wm =
-               &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
        int pipe = intel_crtc->pipe;
        uint32_t cntl = 0;
 
-       if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
-               skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
-
        if (plane_state && plane_state->base.visible) {
                cntl = MCURSOR_GAMMA_ENABLE;
                switch (plane_state->base.crtc_w) {
@@ -14425,8 +14402,17 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
                        intel_check_cpu_fifo_underruns(dev_priv);
                        intel_check_pch_fifo_underruns(dev_priv);
 
-                       if (!crtc->state->active)
-                               intel_update_watermarks(intel_crtc);
+                       if (!crtc->state->active) {
+                               /*
+                                * Make sure we don't call initial_watermarks
+                                * for ILK-style watermark updates.
+                                */
+                               if (dev_priv->display.atomic_update_watermarks)
+                                       dev_priv->display.initial_watermarks(intel_state,
+                                                                            to_intel_crtc_state(crtc->state));
+                               else
+                                       intel_update_watermarks(intel_crtc);
+                       }
                }
        }
 
@@ -14622,7 +14608,6 @@ static int intel_atomic_commit(struct drm_device *dev,
 
        drm_atomic_helper_swap_state(state, true);
        dev_priv->wm.distrust_bios_wm = false;
-       dev_priv->wm.skl_results = intel_state->wm_results;
        intel_shared_dpll_commit(state);
        intel_atomic_track_fbs(state);
 
@@ -14946,7 +14931,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
        intel_pipe_update_start(intel_crtc);
 
        if (modeset)
-               return;
+               goto out;
 
        if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
                intel_color_set_csc(crtc->state);
@@ -14958,6 +14943,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
        else if (INTEL_GEN(dev_priv) >= 9)
                skl_detach_scalers(intel_crtc);
 
+out:
        if (dev_priv->display.atomic_update_watermarks)
                dev_priv->display.atomic_update_watermarks(old_intel_state,
                                                           intel_cstate);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 75252ecaa61334f7ef2104b92152512a37487b8b..3b2c567b8103b852d1f03f3f4fd8d90451100902 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1744,13 +1744,6 @@ bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
                               enum pipe pipe);
 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
                                 struct intel_crtc *intel_crtc);
-void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-                        const struct skl_plane_wm *wm,
-                        const struct skl_ddb_allocation *ddb);
-void skl_write_plane_wm(struct intel_crtc *intel_crtc,
-                       const struct skl_plane_wm *wm,
-                       const struct skl_ddb_allocation *ddb,
-                       int plane);
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a5812eec8edd2ce2df6c0598b78b244028c76e2..5d53a0892187ded7fd23673387c5e2515a53c722 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4202,19 +4202,29 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
        struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
+       const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
        enum pipe pipe = crtc->pipe;
+       int plane;
+
+       if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
+               return;
 
        I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
+
+       for_each_universal_plane(dev_priv, pipe, plane)
+               skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
+
+       skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
 }
 
-static void skl_update_wm(struct intel_crtc *intel_crtc)
+static void skl_initial_wm(struct intel_atomic_state *state,
+                          struct intel_crtc_state *cstate)
 {
+       struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
        struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
-       struct skl_wm_values *results = &dev_priv->wm.skl_results;
+       struct skl_wm_values *results = &state->wm_results;
        struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
-       struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
-       struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
        enum pipe pipe = intel_crtc->pipe;
 
        if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -4222,22 +4232,8 @@ static void skl_update_wm(struct intel_crtc *intel_crtc)
 
        mutex_lock(&dev_priv->wm.wm_mutex);
 
-       /*
-        * If this pipe isn't active already, we're going to be enabling it
-        * very soon. Since it's safe to update a pipe's ddb allocation while
-        * the pipe's shut off, just do so here. Already active pipes will have
-        * their watermarks updated once we update their planes.
-        */
-       if (intel_crtc->base.state->active_changed) {
-               int plane;
-
-               for_each_universal_plane(dev_priv, pipe, plane)
-                       skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
-                                          &results->ddb, plane);
-
-               skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
-                                   &results->ddb);
-       }
+       if (cstate->base.active_changed)
+               skl_atomic_update_crtc_wm(state, cstate);
 
        skl_copy_wm_for_pipe(hw_vals, results, pipe);
 
@@ -7706,7 +7702,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
        /* For FIFO watermark updates */
        if (INTEL_GEN(dev_priv) >= 9) {
                skl_setup_wm_latency(dev_priv);
-               dev_priv->display.update_wm = skl_update_wm;
+               dev_priv->display.initial_watermarks = skl_initial_wm;
                dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
                dev_priv->display.compute_global_watermarks = skl_compute_wm;
        } else if (HAS_PCH_SPLIT(dev_priv)) {

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7b761826a7389968dea5d26008b7434579286452..3ba7d59df00d96b3f65fed44541c106f3707efa3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -203,13 +203,8 @@ skl_update_plane(struct drm_plane *drm_plane,
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_plane *intel_plane = to_intel_plane(drm_plane);
        struct drm_framebuffer *fb = plane_state->base.fb;
-       const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
-       struct drm_crtc *crtc = crtc_state->base.crtc;
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        const int pipe = intel_plane->pipe;
        const int plane = intel_plane->plane + 1;
-       const struct skl_plane_wm *p_wm =
-               &crtc_state->wm.skl.optimal.planes[plane];
        u32 plane_ctl;
        const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
        u32 surf_addr = plane_state->main.offset;
@@ -233,9 +228,6 @@ skl_update_plane(struct drm_plane *drm_plane,
 
        plane_ctl |= skl_plane_ctl_rotation(rotation);
 
-       if (wm->dirty_pipes & drm_crtc_mask(crtc))
-               skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane);
-
        if (key->flags) {
                I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
                I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
@@ -291,19 +283,9 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
        struct drm_device *dev = dplane->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_plane *intel_plane = to_intel_plane(dplane);
-       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
        const int pipe = intel_plane->pipe;
        const int plane = intel_plane->plane + 1;
 
-       /*
-        * We only populate skl_results on watermark updates, and if the
-        * plane's visiblity isn't actually changing neither is its watermarks.
-        */
-       if (!dplane->state->visible)
-               skl_write_plane_wm(to_intel_crtc(crtc),
-                                  &cstate->wm.skl.optimal.planes[plane],
-                                  &dev_priv->wm.skl_results.ddb, plane);
-
        I915_WRITE(PLANE_CTL(pipe, plane), 0);
 
        I915_WRITE(PLANE_SURF(pipe, plane), 0);