Dong Aisheng [Fri, 14 Nov 2014 02:27:06 +0000 (10:27 +0800)]
MLK-9834 mmc: sdhci-esdhc-imx: fix SD3.0 failed to resume if M/F is enabled
Due to the power lost in suspend if Mega/Fast is enabled which is a new
feature introduced, the static settings like tuning control in probe()
function of controller will be lost which results in the later resume
failed on tuning routine for SD3.0 cards(SDR50/SDR104).
This patch moves the tunning setting from probe() function into
register setting path before the tuning is executed.
Then the tuning setting becomes dynamically and re-set again after
resume for a SD3.0 card when doing tuning.
Dong Aisheng [Wed, 6 Aug 2014 05:04:09 +0000 (13:04 +0800)]
ENGR00324668 mmc: core: add delay for SD3.0 UHS mode switch
We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition table
The root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.
So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.
Dong Aisheng [Mon, 17 Nov 2014 08:51:10 +0000 (16:51 +0800)]
MLK-9428 dts: imx6sx: optimize can pad settings
Detailed reproduce steps:
1. boot-up to Linux command prompt.
2. send data from CAN device using "candump" command.
3. capture the TXD waveform during transmission.
4. severe overshoot/undershoot is observed (+4.4V ~ -1.2V).
HW team found that the pad setting of the CAN signal pins is not optimized.
In existing BSP, SPEED/DSE/SRE = 10/110/1 is used. They propose change it
to SPEED/DSE/SRE = 00/100/0.
Dong Aisheng [Tue, 18 Nov 2014 08:03:55 +0000 (16:03 +0800)]
MLK-9501 dts: imx6sx-sdb: optimize usdhc3 pad settings
Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card running
at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write using
FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.
HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD signal pins are
not optimized. In existing BSP, when running at SD3.0/DDR50/1.8V, SPEED/DSE/SRE
= 01/011/1 is used. They propose change it to -
SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.
SDHC high speed cards also had such issue(refer to MLK-9500).
We only changed the default state (<50Mhz) pad setting, for ultra high speed
state like 100Mhz and 200Mhz, it does not have such issue since they already
set to the maximum Drive Strength value.
Dong Aisheng [Tue, 18 Nov 2014 08:32:03 +0000 (16:32 +0800)]
MLK-9871 dts: imx6sx: remove canfd related stuff
The CANFD IP will be removed in final production, so remove
the CANFD related stuff in dts tree to avoid confusion.
The patch only removed user level in dts part, the exists related
clocks and pads in source code are still there which seems not matter.
Dong Aisheng [Tue, 9 Dec 2014 08:43:37 +0000 (16:43 +0800)]
MLK-9975-2 imx6sx-ard: fix CAN unwork if power up the borad on first time
The CAN transceiver on MX6SX Sabreauto board seems in sleep mode
by default after power up the board. User has to press the wakeup
key on ARD baseboard before using the transceiver, or it may not
work properly when power up the board at the first time(warm reset
does not have such issue).
This patch wakeup the transceiver firstly if needed during intialization
by control the wakeup pin, then user do not have to press wakeup key
button to enable the transceiver.
BTW, stby gpio is also updated which is wrong before.
ENGR00333130-2 dts: imx6sx: add legacy imx6sx sdb revA support
The CAN transceiver is changed on RevB board and the default imx6sx-sdb.dts
is for support new RevB board.
This patch adds the dts for legacy RevA board support, especially for CAN
device.
This is for people who still wants to use RevA board with this code base.
The host->vmmc will be in disabled state if there's no card detected.
In that case arbitrarily disabling the host->vmmc in sdhci_remove_host()
may cause the following warning due to unblanced use count of regulator.
root@imx6qdlsolo:~# modprobe -r sdhci-esdhc-imx
mmc3: card e624 removed
------------[ cut here ]------------
WARNING: at drivers/regulator/core.c:1727 _regulator_disable+0xe4/0x14c()
unbalanced disables for VCC_SD3
Modules linked in: sdhci_esdhc_imx(-) sdhci_pltfm
CPU: 0 PID: 884 Comm: modprobe Not tainted 3.10.53-02577-gd22d937 #715
[<80013b00>] (unwind_backtrace+0x0/0xf4) from [<80011524>] (show_stack+0x10/0x14)
[<80011524>] (show_stack+0x10/0x14) from [<8002c290>] (warn_slowpath_common+0x54/0x6c)
[<8002c290>] (warn_slowpath_common+0x54/0x6c) from [<8002c2d8>] (warn_slowpath_fmt+0x30/0x40)
[<8002c2d8>] (warn_slowpath_fmt+0x30/0x40) from [<802cc054>] (_regulator_disable+0xe4/0x14c)
[<802cc054>] (_regulator_disable+0xe4/0x14c) from [<802cc0ec>] (regulator_disable+0x30/0x64)
[<802cc0ec>] (regulator_disable+0x30/0x64) from [<80468dfc>] (sdhci_remove_host+0x78/0x160)
[<80468dfc>] (sdhci_remove_host+0x78/0x160) from [<7f005934>] (sdhci_esdhc_imx_remove+0x30/0x58 [sdhci_esdhc_imx])
[<7f005934>] (sdhci_esdhc_imx_remove+0x30/0x58 [sdhci_esdhc_imx]) from [<80313038>] (platform_drv_remove+0x18/0x1c)
[<80313038>] (platform_drv_remove+0x18/0x1c) from [<803119d8>] (__device_release_driver+0x70/0xcc)
[<803119d8>] (__device_release_driver+0x70/0xcc) from [<803120cc>] (driver_detach+0xac/0xb0)
[<803120cc>] (driver_detach+0xac/0xb0) from [<803116c4>] (bus_remove_driver+0x7c/0xd0)
[<803116c4>] (bus_remove_driver+0x7c/0xd0) from [<8006fc80>] (SyS_delete_module+0x124/0x210)
[<8006fc80>] (SyS_delete_module+0x124/0x210) from [<8000e080>] (ret_fast_syscall+0x0/0x30)
---[ end trace 7bd0fb3a78254b54 ]---
root@imx6qdlsolo:~# EXT3-fs (mmcblk3p2): I/O error while writing superblock
Only disable regulators if they're on when remove host controller.
Fugang Duan [Mon, 19 Jan 2015 09:16:35 +0000 (17:16 +0800)]
MLK-10116 tty: serial: imx: fix flush buffer issue when module clock is at 4Mhz
In general, uart module clock require it is great than 80Mhz to match 5Mbps
baud rate. When test below 14Mhz module clock, software reset cause state
machines off normal. And for i.MX6SL evk board low power test, it set uart
module clock to 4Mhz, which cause console port print out messy code.
The patch just is workaround to fix console issue.
Sandor Yu [Mon, 19 Jan 2015 06:36:59 +0000 (14:36 +0800)]
MLK-10115: ov5640:define function ov5640_turn_on_AE_AG() with static
ov5640 driver will failed to build with build-in:
drivers/media/platform/mxc/subdev/built-in.o: In function
`ov5640_turn_on_AE_AG':
ov5640.c:(.text+0x3890): multiple definition of `ov5640_turn_on_AE_AG'
drivers/media/platform/mxc/capture/built-in.o:v4l2-int-device.c:(.text+0x783c):
first defined here
make[3]: *** [drivers/media/platform/built-in.o] Error 1
make[2]: *** [drivers/media/platform] Error 2
make[1]: *** [drivers/media] Error 2
make: *** [drivers] Error 2
make: *** Waiting for unfinished jobs....
It is caused by function of ov5640_turn_on_AE_AG define as global function,
change it to static function to resolv the issue.
Richard Zhu [Thu, 25 Dec 2014 06:36:44 +0000 (14:36 +0800)]
MLK-10058-4 pci: imx6: refine imx6sx pcie pm
- Regarding to the pcie design on imx6sx, some gpc
operations are mandatory pre-required when pcie phy
is powered on/off.
In order to DO NOT touch gpc module in pcie driver,
register one pcie phy regulator into gpc, encapsulate
the pcie phy power on/off pre gpc related operations into
regulator's notify and contained in gpc driver
- in order to save power consumption, disable pcie clks and phy
regulator if the pcie link is down.
- remove the PRST set/unset in suspend/resume, because that
usb hub would be reset, and the name of the dev node of the
thumb disk inserted in the port of the pcie2usb device,
would be changed randomly after suspend resume on imx6sx.
- add the extremely power save mode
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Richard Zhu [Thu, 25 Dec 2014 06:30:38 +0000 (14:30 +0800)]
MLK-10058-3 arm: gpc: add pcie phy power gpc operations
For PCIe module on i.mx6sx, some GPC operations would
be mandatory required when PCIe PHY is powered on/off.
So we need update gpc driver for the new requirements.
We implement it by regulator notify framwork in gpc driver.
NOTE:
make sure gpc driver is ready before PCIe driver is probed.
Otherwise, cause system hang during PCIe driver probe,
because the notify NOT installed ready and the gpc will
NOT power on PCIe.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Some gpc operations are mandatory required when
iMX6SX PCIe PHY is powered on/off.
use the notify framwork to encapsulate the
pre-operations in gpc driver
- add two pre-xxx macros into consumer.h
- kick off the pre-xxx events in enable/disalbe call back.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Xiubo Li [Fri, 29 Aug 2014 07:12:12 +0000 (15:12 +0800)]
ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.
The 'big-endian-data' property is originally used to indicate whether the
LSB firstly or MSB firstly will be transmitted to the CODEC or received
from the CODEC, and there has nothing relation to the memory data.
Generally, if the audio data in big endian format, which will be using the
bytes reversion, Here this can only be used to bits reversion.
So using the 'lsb-first' instead of 'big-endian-data' can make the code
to be readable easier and more easy to understand what this property is
used to do.
This property used for configuring whether the LSB or the MSB is transmitted
first for the fifo data.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit eadb0019d206591e34e864b62059b292e157d8fc)
Xiubo Li [Mon, 25 Aug 2014 03:31:02 +0000 (11:31 +0800)]
ASoC: fsl-sai: Convert to use regmap framework's endianness method.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 014fd22ef9c6a7e9536b7e16635714a1a34810a8)
Peter Chen [Tue, 30 Sep 2014 01:10:59 +0000 (09:10 +0800)]
MLK-10107-3 ARM: imx_v7_defconfig: enable more USB functions
USB Ethernet function at host mode
USB Media function(webcam) at host mode
USB Audio function at host mode
USB Serial function at host mode
USB EHSET driver at host mode (for OTG & EH Certification test)
Several USB Gadget functions:
- Configfs
- NCM
- Zero (used for test)
- Gadgetfs
- Serial
Above functions are built as module.
Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Peter Chen <peter.chen@freescale.com>
For chipidea, its resume sequence is not-EHCI compatible, see
below description for FPR at portsc. So in order to send SoF in
time for remote wakeup sequence(within 3ms), the RUN/STOP bit must
be set before the resume signal is ended, but the usb resume
code may run after resume signal is ended, so we had to set it
at suspend path.
Force Port Resume - RW. Default = 0b.
1= Resume detected/driven on port.
0=No resume (K-state) detected/driven on port.
Host mode:
Software sets this bit to one to drive resume signaling. The Controller sets this bit to '1' if
a J-to-K transition is detected while the port is in the Suspend state. When this bit
transitions to a '1' because a J-to-K transition is detected, the Port Change Detect bit in
the USBSTS register is also set to '1'. This bit will automatically change to '0' after the
resume sequence is complete. This behavior is different from EHCI where the controller
driver is required to set this bit to a '0' after the resume duration is timed in the driver.
Note that when the controller owns the port, the resume sequence follows the defined
sequence documented in the USB Specification Revision 2.0. The resume signaling
(Full-speed 'K') is driven on the port as long as this bit remains a '1'. This bit will remain
a '1' until the port has switched to idle. Writing a '0' has no affect because the port
controller will time the resume operation, clear the bit and the port control state switches
to HS or FS idle.
This field is '0' if Port Power(PP) is '0' in host mode.
This bit is not-EHCI compatible.
Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Thu, 12 Dec 2013 06:33:02 +0000 (14:33 +0800)]
ENGR00291876 usb: phy-mxs: add delay before set phyctrl.clkgate
There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phypwd, otherwise, the wakeup
signal may can't wake up controller.
Peter Chen [Thu, 21 Nov 2013 08:45:18 +0000 (16:45 +0800)]
ENGR00288578-8 usb: phy-mxs: do not set PWD.RXPWD1PT1 for low speed connection
At very rare cases, the SoF will not send out after resume with
low speed connection. The workaround is do not power down
PWD.RXPWD1PT1 bit during the suspend.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
For non-otg mode, we keep the usage of disconnect line between phy analog
and digital unchanging; for otg mode, at peripheral role, we keep the usage
unchanging too, at host role, the digital part needs to know dp/dm change
to respond device's data pulse when it is at low power mode.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
Bai Ping [Tue, 13 Jan 2015 14:19:53 +0000 (22:19 +0800)]
MLK-10089 arm: imx: Add 198MHz OPP for i.MX6SX
Update the i.MX6SX operating points to comply with the latest
datasheet. Latest i.MX6SX datasheet of Rev.F, 1/2015 adds the
198MHz setpoint. For the RevB board, the VDD_ARM and ADD_SOC
are connected together, so the voltage for 198MHz needs to be
set to 1.175V. for the general setting, add a 25mV margin to
cover the board IR drop.
this patch is copy from commit: 17dae6e92 on branch imx_3.10.y
as too many conflicts to resolve.
Bai Ping [Wed, 14 Jan 2015 14:46:10 +0000 (22:46 +0800)]
MLK-10091 arm: imx: check pll1 enable when changing arm_podf
According to the hardware design, when changing the arm_podf divider,
make sure the pll1 has clk output. If the pll1 output is disabled before
changing the arm_podf, enbale and bypass the pll1 to make sure the
arm_podf can be successfully changed.
Li Jun [Thu, 15 Jan 2015 13:00:34 +0000 (21:00 +0800)]
MLK-10102-8 usb: chipidea: support role change after power lost
This patch is to complete support usb resume from power lost in non-otg
fsm mode:
- Re-init usb phy.
- Support role changes during system sleep with power lost.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
Li Jun [Fri, 16 Jan 2015 05:11:57 +0000 (13:11 +0800)]
MLK-10102-7 usb: chipidea: otg: fix deadlock of usb host removal after system resume
This is to fix possible deadlock of usb host with mass storage removal after
system resume, by waiting host finish device disconnection and then stop host
This is a patch merge for ideas from below 2 patches:
ENGR00308442-2 usb: chipidea: otg: wait devices disconnected before stop host.
ENGR00310498 usb: chipidea: otg: fix otg role switch from host to device failure
How to reproduce:
Failure case 1:
- Enable console wakeup:
echo enabled > /sys/class/tty/ttymxc0/power/wakeup
- Connect a udisk with ID cable to OTG port.
- Suspend the system:
ehco mem > /sys/power/state
- Remove ID cable together with udisk.
- Wakeup the system by console.
- OTG port cannot switch to device role.
Failure case 2:
- Connect a udisk with ID cable to OTG port.
- Enable usb wakeup by ./low_power_usb.sh
- Suspend the system:
ehco mem > /sys/power/state
- Remove ID cable together with udisk.
- System wakeup but OTG port cannot switch to device role.
Root cause:
In this case, ID change interrupt generates before port change interrupt,
so with irq disabled, ci_handle_id_switch() will find there is usb device
still connected and wait it to disconnect by sleep, but disconnect will not
happen since usb irq still disabled so port change irq has no chance to be
handled.
How this patch is fixing this issue:
This patch waits host finish handle usb device disconnection before stop host,
and enables irq before sleep and disables irq after, thus port change
rq can be handled and usb device disconnection can timely happen, then
ci_handle_id_switch() can stop host and switch to device role correctly.
Li Jun [Thu, 15 Jan 2015 12:10:36 +0000 (20:10 +0800)]
MLK-10102-4 usb: chipidea: host: support resume usb from power lost
This patch implements the suspend and resume routine for save and restore
registers of ehci, this is to support host resume from a system sleep with
power lost.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
Li Jun [Thu, 15 Jan 2015 12:17:07 +0000 (20:17 +0800)]
MLK-10102-2 usb: chipidea: add suspend and resume routine for role driver
We may need to do extra things for system suspend/resume per different
roles(e.g. power lost during system sleep), so define system suspend/resume
handler for roles.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Thu, 15 Jan 2015 11:13:13 +0000 (19:13 +0800)]
MLK-10102-1 usb: chipidea: imx: usb resume from power lost during system sleep
i.MX6SX mega off can shutdown domain power supply if none of peripheral
in this domain is registered as wakeup source, this patch adds usb controller
imx specific re-init after resume from such power lost during system sleep.
Anson Huang [Fri, 16 Jan 2015 10:47:42 +0000 (18:47 +0800)]
MLK-10103-2 cpufreq: imx6: increase SOC/PU voltage for vpu 352M
When VPU is running at 352MHz, SOC/PU voltage need to be
at 1.25V for 396/792MHz setpoint, as 396M setpoint is
removed, so only increase 792M setpoint's voltage.
Anson Huang [Fri, 16 Jan 2015 10:42:08 +0000 (18:42 +0800)]
MLK-10103-1 ARM: imx: add VPU 352M for i.mx6q
When VPU freq is set to 352MHz, it needs to source clk
from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change
freq to 352M, cpufreq's 396M setpoint will be removed.
Busfreq will be disabled as it needs PLL2_PFD2 to be
as 396MHz to achieve low power audio freq setpoint.
To enable VPU 352MHz feature, select it in menuconfig,
it is disabled by default.
Fugang Duan [Fri, 16 Jan 2015 05:18:00 +0000 (13:18 +0800)]
ENGR00320136 net: fec: fix rcv is not last issue when do suspend/resume test
When do suspend/resume stress test, some log shows "rcv is not +last".
The issue is that enet suspend will disable phy clock, phy link down,
after resume back, enet MAC redo initial and ready to tx/rx packet,
but phy still is not ready which is doing auto-negotiation. When phy
link is not up, don't schdule napi soft irq.
Steve Cornelius [Tue, 6 Jan 2015 23:20:15 +0000 (16:20 -0700)]
MLK-9769-26 caam: fix RNG buffer cache alignment
The hwrng output buffers (2) are cast inside of a a struct (caam_rng_ctx)
allocated in one DMA-tagged region. While the kernel's heap allocator
should place the overall struct on a cacheline aligned boundary, the 2
buffers contained within may not necessarily align. Consenquently, the ends
of unaligned buffers may not fully flush, and if so, stale data will be left
behind, resulting in small repeating patterns.
This fix aligns the buffers inside the struct.
Note that not all of the data inside caam_rng_ctx necessarily needs to be
DMA-tagged, only the buffers themselves require this. However, a fix would
incur the expense of error-handling bloat in the case of allocation failure.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Victoria Milhoan [Wed, 14 Jan 2015 18:43:12 +0000 (11:43 -0700)]
MLK-9769-23 Replace SECVIO of_irq_to_resource() with irq_of_parse_and_map()
Replace of_irq_to_resource() in the SECVIO module with the simpler
equivalent irq_of_parse_and_map(). Also, add error checking to
to the SECVIO and Job Ring modules. Based on upstream commit f7578496a671a96e501f16a5104893275e32c33a.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
Victoria Milhoan [Thu, 18 Dec 2014 21:06:50 +0000 (14:06 -0700)]
MLK-10036 Freescale CAAM: Add support for DSM with Mega/Fast mix on
This patch allows CAAM to be enabled as a wakeup source for the
Mega/Fast mix domain. If CAAM is enabled as a wakeup source, it
will continue to be powered on across Deep Sleep Mode (DSM). This
allows CAAM to be functional after the system resumes from DSM.
MLK-9971 Add XCBC-AES support for CAAM in i.MX6 family
Add XCBC-AES support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
Jason Liu [Tue, 6 Jan 2015 03:23:59 +0000 (11:23 +0800)]
Need gate the QSPI2 and GPMI_IO clock during clock init
QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Peter Chen [Mon, 23 Sep 2013 03:20:08 +0000 (11:20 +0800)]
ENGR00320792-3 usb: gadget: mark init as late_initcall
Since we introduce -EPROBE_DEFER for udc driver, it will be
probed at late_initcall if it is defered. When the gadget
is built in, it will return "couldn't find an available UDC"
at such case. That's the problem we met at below link:
We have no driver's probe at gadget driver, so we can't return
-EPROBE_DEFER. And it is also not suitable to defer udc_bind_to_driver
if the udc is not found temporarily, since it is hard to decide the
return value for usb_gadget_probe_driver.
Due to above reasons, mark gadget's init as late_initcall may be a
moderate solution.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Fri, 9 Jan 2015 07:35:07 +0000 (15:35 +0800)]
MLK-10085-5 usb: chipidea: Add usb charger detect notify
- Change .notify's return value from void to int, update msm notify_event
return value accordingly.
- Add CI_HDRC_CONTROLLER_VBUS_EVENT and
CI_HDRC_CONTROLLER_CHARGER_POST_EVENT to finish the USB charger
detection flow.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <jun.li@freescale.com>
It is used to indicate whether we use SoC's usb charger
detection or not. Besides, we add anatop phandle since
we need to use anatop register to do most of charger detect operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Fri, 9 Jan 2015 03:39:33 +0000 (11:39 +0800)]
MLK-10085-1 power: imx6: add imx6 USB charger detection
Add imx6 USB charger detection, the vbus supplier will create and
remove struct usb_charger, and notify vbus connect and disconnect
event. The detail USB charger detection flow is at: "i.MX6 RM,
Chapter Universal Serial Bus 2.0 Integrated PHY (USB-PHY),
Charger detection, Charger detection software flow".
Since imx6 only has charger detection function, and no charging
current function is existed. It the user wants the detection abilities
from SoC, it can use this detection method
(add imx6-usb-charger-detection at dts). If the charger IC
already has USB charger detection function, and the user wants
to use the detection method from charger IC, please do not add
imx6-usb-charger-detection property at dts.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Allen Xu [Thu, 15 Jan 2015 02:18:29 +0000 (10:18 +0800)]
MLK-10028 QSPI dynamically alloc memory for AHB read
QSPI may failed to alloc enough memory (256MB) for AHB read in
previous implementation, especially in 3G/1G memory layout kernel.
Dynamically alloc memory to avoid such issue.
This implementation generally alloc 4MB memory for AHB read, it should
be enough for common scenarios, and the side effect (0.6% performance
drop) is minor.
Previous implementation
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out 33554432 bytes (34 MB) copied, 2.16006 s, 15.5 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out 33554432 bytes (34 MB) copied, 1.43149 s, 23.4 MB/s
After applied the patch
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out 33554432 bytes (34 MB) copied, 2.1743 s, 15.4 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out 33554432 bytes (34 MB) copied, 1.43158 s, 23.4 MB/s
NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.
To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.
No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.
Allen Xu [Thu, 4 Dec 2014 13:51:48 +0000 (21:51 +0800)]
MLK-9957 mtd: NAND: fix the kernel panic issue for NAND suspend/resume
The branch determined by GPMI_IS_MX6SX() should not include
acquire_dma_channels() function which causes unbalanced dma
request/release on other platform.
Removed GPMI_IS_MX6SX() to make code simple although it is not necessary
to restore GPMI/BCH registers for i.MX6Q/DL
Ye.Li [Mon, 1 Dec 2014 09:28:47 +0000 (17:28 +0800)]
MLK-9920 mtd: qspi: Add ddrsmp parameter to device tree
Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for i.MX6SX Sabreauto/Sabresd board.
Allen Xu [Fri, 14 Nov 2014 16:36:07 +0000 (00:36 +0800)]
MLK-9851 mtd: Change the mtd device driver build order for mfgtool
i.MX6SX Sabreauto board enabled both NAND and QSPI1 drivrers, and by default,
NAND driver built first in kernel compiling, and it would be load first when
Kernel brought up.
Since we could not guarantee all boards mounted NAND chips, we wish the Kernel
could load QSPI driver first, when system mapped QSPI and NAND, the mtd device
index won't change dynamically, otherwise, the mfgtool may write images to the
inappropriate storage devices.
The code change moved the SPI driver at the prior position of NAND driver in
Makefile to solve this issue.
Allen Xu [Thu, 25 Sep 2014 10:39:09 +0000 (05:39 -0500)]
ENGR00311101 QSPI: i.MX6SX: fixed the random QSPI access failed issue
We found there is a low probability(5%) QSPI access timeout issue,
usually it happened on kernel boot stage, the first time kernel tried to
access QSPI chip. The READ_ID command was sent but not executed,
consequently the probe function failed.
Finally we located the issue by these steps.
1. Since the issue happened randomly and usually it cost half day to
reproduce, we add more debug code in driver, to create a timeout file if
the issue occurred.
2. Prepared an autorun script to keep rebooting the system and check if
the timeout file existed, if the file existed, stop reboot.
3. The system will stop rebooting when timeout error occurred, set the
CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
is no clock output, while clock output can be measured when QSPI driver
successfully probed.
4. Check the code and found QSPI clock rate was changed while not
disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
clock glitch may occurred and propagated into downstream clock dividers
Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
need to change the approach of seting clock rate. In current
implementation, there are several places in which the clock was touched.
1. probe function. prepare and enable clock before setting the QSPI
register, disable and unprepare the clock before exit.
2. nor_setup & nor_setup_last, since we change clock rate in these two
functions.
3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
QSPI access request.
4. resume function. Clock was required to restroe the setting after
resume, disable the clock before exit.
Sandor Yu [Wed, 14 Jan 2015 07:41:43 +0000 (15:41 +0800)]
MLK-10092-2 dts: Rename compatible string from ov564x to ov5640
There are two version ov5640 driver,
one is written with v4l2 int-device architecture,
and the other is written with v4l2 subdev architecture.
Rename subdev ov5640 compatible string from ov5640x
to ov5640 to distinguish with ov5640 int-device driver.
so ov564x is used for int-device architecture and
ov5640 is used for subdev architecture.
Sandor Yu [Wed, 14 Jan 2015 07:34:22 +0000 (15:34 +0800)]
MLK-10092-1 ov5640: Rename compatible string from ov564x to ov5640
There are two version ov5640 driver,
one is written with v4l2 int-device architecture,
and the other is written with v4l2 subdev architecture.
Rename subdev ov5640 compatible string from ov5640x to ov5640
to distinguish with ov5640 int-device driver.
so ov564x is used for int-device architecture and
ov5640 is used for subdev architecture.
Liu Ying [Tue, 13 Jan 2015 02:19:10 +0000 (10:19 +0800)]
MLK-10084 media: mxc vout: Correct black color filling for interleaved formats
In non-linear_bypass_pp and non-tiled_bypass_pp modes, the triple fbdev frame
buffer would be rendered with video frames in turn. We need to fill all the
three frame buffers with black color before streaming on instead of filling only
one of them.
Fugang Duan [Wed, 14 Jan 2015 08:18:58 +0000 (16:18 +0800)]
MLK-10098 ARM: imx: fix 1588 clock init
The enet clock define is changed as there has no "enet_ref" clock name.
If the tx_clk is sourced from SOC anatop PLL, user define the clock id
in devicetree. So we only to judge the ptp clock valid and then set the
related GPR bit.
According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig:
"In some older versions of glibc [<=2.8] SWP is used during futex trylock()
operations with the assumption that the code will not be preempted. This
invalid assumption may be more likely to fail with SWP emulation enabled,
leading to deadlock of the user application."
The audio codec toolchain version is gcc-4.1.1-glibc-2.4, we need turn off
the CONFIG_SWP_EMULATE in the imx_v7_defconfig.
projects / karo-tx-linux.git / log