Peter Chen [Fri, 17 Feb 2012 07:22:07 +0000 (15:22 +0800)]
ENGR00174734-2 usb: fix bugs that dp and dm are floating at device mode
At i.mx6x, the data line (dp and dm) are floating at device mode,
that is to say data line will be any values (0-3.6v).
So if the usb wakeup is enabled, there will be a wakeup interrupt
that causes usb to active mode.
In order to fix this problem well, we need to do below things:
- Need to discharge both dp and dm
- It needs to discharge data line when we switch to device mode and
usb cable is disconnected from the host, but not to disable discharge
after line state is SE0, the reason is that if we do not pulldown
the data line, the line state will be floating again, and possible cause
the wakeup interrupt.
- It needs to disable discharge data line when the usb cable connects at
device mode and usb device is connected at host mode, otherwise it will
affect signal quality.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Sandor Yu [Tue, 21 Feb 2012 09:26:28 +0000 (17:26 +0800)]
ENGR00174911 MX6x Setting HDMI default mode according bootload cmdline
Origin HDMI default video mode is setting to VGA.
But the HDMI will change to the vide mode setting in bootloader
command line when the first time HDMI cable plugin.
It will cause GUI sometime can't not get correct FB video mode
when system bootup without HDMI cable plugout.
Ryan QIAN [Wed, 22 Feb 2012 01:32:51 +0000 (09:32 +0800)]
ENGR00175080 [MX6] MMC: kernel failed to init eMMC card, after boot from eMMC
issue:
if uboot is loaded from eMMC, the eMMC memory will be configured to DDR mode.
on kernel startup, it will initialize the card at SDR mode, while the register
of USDHC is still configured to DDR enable mode. Therefore, the initialization
of eMMC memory will fail.
fix:
- clear MIX_CTRL on sdhc platform init code.
- clear vselect bit of VENDOR_SPEC on sdhc platform init code.
Adrian Alonso [Fri, 17 Feb 2012 00:42:33 +0000 (18:42 -0600)]
ENGR00171079-8 imx6q sabreauto cs42888 audio support
* Add imx6q sabreauto cs42888 audio support
* Set clock parent relations
anaclk_2 -> pll4_audio_clk -> esai_root_clk
* Match corresponding sysclk frequency to keep lrclk_ratio
relation on imx-cs4288 esai configuration
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* Add mx6q anaclk_1/2 clock input source clock support
* anaclk can be bypassed to pll4_audio.
* _clk_audio_video_set_parent allows to bypass anaclk input
clock source, for sabreauto platform anaclk_2 is the clock
source for cs42888 and this clock needs to be bypassed to
esai to supply the same master clk signal.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 17 Feb 2012 00:32:27 +0000 (18:32 -0600)]
ENGR00171079-6 imx-cs42888 sabreauto esai config
* imx-cs42888 config esai for sabreauto support
* Select lrclk_ratio according to mclk_freq
* Set clkdiv relations
* Add safer codec reset, request and free gpio
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 17 Feb 2012 21:09:31 +0000 (15:09 -0600)]
ENGR00171079-5 imx6q-sabreauto set supportted sample rates
* cs42888 set imx6q-sabreauto supportted play/record sample rates
master clk signal is a fixed source clock @24576000Mhz, thus
limit the play/record sample rates lrclk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* Get audio codec platform data and overwrite supportted
sample rates if defined in machine board file.
* Remove machine soc specific sample rate settings.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 17 Feb 2012 18:14:28 +0000 (12:14 -0600)]
ENGR00171079-3 fsl_devices add generic audio codec platform data
* Add generic audio codec platform_data to be able to
pass specific settings to audio codecs found in Freescale
target boards.
* cs42888 get this platform data to override specific settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 17 Feb 2012 00:18:25 +0000 (18:18 -0600)]
ENGR00171079-1 mx6q-ard: esai remove record early param
* Remove record early param, pad GPIO9 shared with
ESAI_FSR and WDOG1 doesn't conflict as WDOG1
connection is open, NANDF_CS3 is shared with ESAI_TX1
and connection is also open with nand socket, no other
pad conflicts.
* Add esai interrupt gpio pin.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
GPU clock on i.mx6dl:
gpu2d_core_clk source from gpu3d_shader_clk,
gpu3d_axi_clk source from mmdc0 directly, 400Mhz by default,
gpu2d_axi_clk source from mmdc0 directly, 400Mhz by default,
AXI_CLK on i.mx6dl:
set axi_clk parent to pll3_pfd_540M and divid by 2, which will
get 270Mhz by default,
VPU clock on i.mx6dl:
VPU will parent from axi_clk, then by default, it will be 270Mhz,
which will be suitable for VPU 1080p support.
pll3_pfd_540M on i.mx6dl will be dedicated to VPU/IPU/AXI_CLK use,
other users should not change this assignment
Sammy He [Tue, 21 Feb 2012 05:51:20 +0000 (13:51 +0800)]
ENGR00174904 VPU: change spinlock to mutex
The spinlock caused a bug warning when we enable the lock debug mechenism.
See the log:
"
BUG: sleeping function called from invalid context at mm/slub.c:847
in_atomic(): 1, irqs_disabled(): 0, pid: 6053, name: aiurdemux0:sink
INFO: lockdep is turned off.
no locks held by aiurdemux0:sink/6053.
[<80042f24>] (unwind_backtrace+0x0/0xfc) from
[<800f1dec>] (kmem_cache_alloc+0x114/0x180)
[<800f1dec>] (kmem_cache_alloc+0x114/0x180) from
[<800e425c>] (__get_vm_area_node+0x88/0x194)
[<800e425c>] (__get_vm_area_node+0x88/0x194) from
[<800e4b78>] (__vmalloc_node_range+0x68/0x1c8)
[<800e4b78>] (__vmalloc_node_range+0x68/0x1c8) from
[<800e4d18>] (__vmalloc_node+0x40/0x48)
[<800e4d18>] (__vmalloc_node+0x40/0x48) from
[<800e4f04>] (vmalloc_user+0x2c/0x74)
[<800e4f04>] (vmalloc_user+0x2c/0x74) from [<8038eb28>] (vpu_ioctl+0x204/0x8b0)
[<8038eb28>] (vpu_ioctl+0x204/0x8b0) from [<8010643c>] (do_vfs_ioctl+0x80/0x5e4)
[<8010643c>] (do_vfs_ioctl+0x80/0x5e4) from [<801069d8>] (sys_ioctl+0x38/0x60)
[<801069d8>] (sys_ioctl+0x38/0x60) from [<8003d500>] (ret_fast_syscall+0x0/0x3c)
"
Change the spinlock to mutex to fix this issue.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com>
Wu Guoxing [Tue, 21 Feb 2012 05:02:50 +0000 (13:02 +0800)]
ENGR00174899: mx6/dl:gpu2d:fix gc320 can not run at high core clock issue
gc320 on Rigel can not run at high core clock, above 200M core clock will
make system hang.
change gc320's axi outstanding limit to 16 as a ic workaround.
Alan Tull [Fri, 17 Feb 2012 21:15:35 +0000 (15:15 -0600)]
ENGR00174809 hdmi audio oops in hdmi_dma_mmap_copy
Runtime dma_area may be invalid after trigger stop command.
This will cause an oops in hdmi_dma_mmap_copy. To fix this,
disable mmap copying with trigger stop command and also check
the runtime->dma_area before doing hdmi_dma_mmap_copy.
Chen Liangjun [Fri, 17 Feb 2012 06:33:50 +0000 (14:33 +0800)]
ENGR00174747 ASRC:fix spinlock bug
When use clk_enable and clk_disable function, system may enter
sleep. so these 2 funciton can not used surrounding with spin
lock/unlock. And the clk_enable/disable function already keep
the counter of open and close and it is no need to keep the counter
in driver.
Wayne Zou [Tue, 14 Feb 2012 01:10:53 +0000 (09:10 +0800)]
ENGR00174394 MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB config.
MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB configuration.
For, LDB_SEP0 mode, the disp_id should be 0, and sec_disp_id should be
1 on MX6Q, since the LDB channel 0 should be connected to IPU DI0.
Jason Liu [Wed, 15 Feb 2012 10:34:41 +0000 (18:34 +0800)]
ENGR00174540: i.mx6: anatop_regulator: LDO voltage print not correctly
The LDO voltage constraint not printed correctly:
print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal
There due to one typo: << in the code, thus will make the LDO constraint print
not correctly, the patch will make the print correctly as the followings:
print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal
Danny Nold [Tue, 14 Feb 2012 23:15:23 +0000 (17:15 -0600)]
ENGR00174106-3 - EPDC fb: Support EPDC v2.0
- Added new register definitions for EPDCv2.0
- Added support for 64 LUTs
- Conditionalized code for EPDC versions 1.0, 2.0, and 2.1
- Support for EPDC auto-waveform selection
- Support for collision test mode
- Support for PxP bypassing
- Support for LUT cancellation
- Support for new PxP limitations
- Support for collision minimization EPDC feature
- Added workaround for collision status bug (can't clear
IRQ before reading collision status for LUTs 16-63)
Signed-off-by: Danny Nold <dannynold@freescale.com>
Fugang Duan [Tue, 14 Feb 2012 08:56:26 +0000 (16:56 +0800)]
ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk and i2c3 are mutually exclusive, because
all of them use GPIO_16, so it only for one function work
at a moment.
- Test result:
TO1.1 IEEE 1588 is convergent in Sabrelite board.
Chen Liangjun [Tue, 14 Feb 2012 03:23:30 +0000 (11:23 +0800)]
ENGR00174399 ASRC: fix mmap fail bug
If output sample rate is less than input sample rate, it is possible
that the address of output dma buffer 0 can not be divided by page size.
Thus the mmap of output dma in the user space would fail and test
would fail.
let all output dma buffers allocate dma buffer together and we can
assure that the address of output dma buffer 0 can be divided by
page size.
Liu Ying [Mon, 13 Feb 2012 09:45:17 +0000 (17:45 +0800)]
ENGR00174395 V4L2 capture: Driver improvement
1) CSI module should be disabled first for CSI_MEM channel,
otherwise, the capture channels will hang after restarting
for several times.
2) Disable CSI module correctly for overlay. Move stopping
preview channel operation out of de-select interface.
3) Check cam->overlay_on is true in close function before
stopping preview.
4) Check cam->vf_start_sdc function before calling it.
Sammy He [Tue, 14 Feb 2012 02:09:05 +0000 (10:09 +0800)]
ENGR00174323 vpu: Fix system hang issue of multi-instances processing
VPU registers have been mapped with ioremap() at probe which
L_PTE_XN is 1, and the same physical address must be mapped multiple
times with same type when doing mmap() to user space, so also need
to set it to 1. Otherwise, there may be unexpected result in video
codec.
Here, Use new defined pgprot_noncachedxn for vm_page_prot in mmap().
Tony Lin [Fri, 10 Feb 2012 09:06:21 +0000 (17:06 +0800)]
ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1
remove the workaround
For TO1.0: bit16 of GPR11 must be set to enable perfmon
For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon.
set 1/0 to enable/disable perfmon
Xinyu Chen [Fri, 10 Feb 2012 07:54:41 +0000 (15:54 +0800)]
ENGR00174127 mag3110: merge the mag3110 sensor driver
Merge mag3110 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export set delay interface to userspace and
use polling mode instead of interrupt mode.
Merge mma8451 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export enable and position interface to userspace.
Zhang Jiejing [Wed, 11 Jan 2012 06:20:15 +0000 (14:20 +0800)]
ENGR00173857 MX6Q: add 600M work point
Add a 600M work point for better suit for cpufreq driver.
For current MX6Q clock tree, the most near 600M working point
is 624M, so we use 624M as 600M working point.
We found we have 200/400/800/1G working point is not very
good for cpufreq adjustment, since we don't have a uniform
working point distribution, since the interactive governor
is using cpu usage to adjust frequency, eg, 60% CPU, going
to 600M working point, if above a threshold (%85 default)
will going to max frequency directly.
From the [sheet] , you can see in game case, it will have much
chance in 400M working point, between 400M and 800M working
point, there is a gap, so the 400M will be most used frequency.
we add 600 WP to fill this gap, and make game case have
better experience.
Richard Zhu [Wed, 8 Feb 2012 06:58:41 +0000 (14:58 +0800)]
ENGR00174033-2 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can accessed
Richard Zhu [Wed, 8 Feb 2012 06:57:56 +0000 (14:57 +0800)]
ENGR00174033-1 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed
Peter Chen [Thu, 9 Feb 2012 09:38:59 +0000 (17:38 +0800)]
ENGR00174128-1 Revert "Remove the discharge for VBUS and DP-1"
As dp/dm is floating with no usb cable and switch host mode to
device mode situation, it do needs this discharge dp patch
But, discharge vbus doesn't be needed at suspend_irq, so
keep it removing.
Nancy Chen [Thu, 9 Feb 2012 16:27:07 +0000 (10:27 -0600)]
ENGR00174094 i.MX6DL: Change CPU voltages to 1V
Change CPU voltages (0.95V and 0.85V) to 1V
CPU voltage should be above 1.0V for all CPU frequency
since L1 Cache power is connected to VDDARM internally.
Jason Liu [Thu, 9 Feb 2012 06:09:58 +0000 (14:09 +0800)]
ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need
set DDR/periph_clk parent to pll2_mfd_400M during clock init, which
will setup the clock usecount of pll2_mfd_400M correctly, otherwise,
when all the child device with clock source from pll2_mfd_400M turn
off, the pll2_mfd_400M will turns off automaticly, which will cause
system hang due to DDR clock is off when code is runing on it.
Peter Chen [Thu, 9 Feb 2012 09:07:44 +0000 (17:07 +0800)]
ENGR00174124: Revert "[USB Host]change the default wakeup value of RH"
This patch creates two bugs at current i.mx usb framework.
- The high speed device can't be recognized at the first time.
- The usb device can't be recognized after system resume with
usb vbus.
The reason why it creates bugs that it changes (auto)suspend/resume
process for usb core.
Tony LIU [Wed, 8 Feb 2012 07:33:56 +0000 (15:33 +0800)]
ENGR00174037-1 Add HSIC suspend/resume feature
MSL part
- For HSIC, not connect nor disconnect, then WKCN,
WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
avoid 24M OSCI not stable issue
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Alan Tull [Wed, 8 Feb 2012 22:40:31 +0000 (16:40 -0600)]
ENGR00172342-2 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Alan Tull [Thu, 26 Jan 2012 17:37:01 +0000 (11:37 -0600)]
ENGR00172342-1 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Wayne Zou [Thu, 2 Feb 2012 07:10:35 +0000 (15:10 +0800)]
ENGR00171353 MIPI_DSI: mipi display blank and unblank fail fixed
mipi display blank and unblank fail on HW board: MX6Q_ARM2 1G SN 0112
The host processor sends PCLK, HS and VS information to display modules
two frames before sleep-out command is sent.
Sandor Yu [Wed, 8 Feb 2012 05:45:18 +0000 (13:45 +0800)]
ENGR00173962 Added HDMI enable function
Whenever IPU clock change or gating, the HDMI PHY should reset or config again,
otherwise the HDMI PHY will not work.
It is the root cause for Ubuntu can't show GUI to HDMI device when bootup
and GPU application tutorial4_es20 no output to HDMI device.
Added enable function in mxcfb_set_par() to fix aboved two issue.
Added HDMI initialization check, only one HDMI instanse supported.
projects / karo-tx-linux.git / log