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ENGR00209846 MX6SL-Enable DVFS_CORE on all MX6 platforms
2013-05-24 Ranjani VaidyanathanENGR00209846 MX6SL-Enable DVFS_CORE on all MX6 platforms
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00209617 MX6x - Add WAIT mode workaround
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00209657 MX6SL-Initialise CPU_CLK and AHB_CLK to...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00209620 MX6-Disable PU Brown out detection in...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00181068: MX6 Source IPU_HSP and AXI clocks from...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00180882- MX6DL Add bus frequency scaling support.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00180185: MX6-Add support for low power audio playback
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00179747: MX6DL-Fix boot failure
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00179574: MX6- Add bus frequency scaling support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00179582 MX6: Bypass PLL1 during WAIT
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00178763: MX6-Fix TO1.0 boot-fail issue
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00176366: MX6-Switch ARM_CLK to PLL2_400MHz when...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00176136- MX6: Added support for 1.2GHz ARM Frequency
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00174569: MX6 - Disable WAIT mode by default
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00173586-2 [MX6] Add support to source GPT from...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00173586-1 [MX6] Add support to source GPT from...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00173585: MX6: Added WAIT mode workaround for MX6Q...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00170520: MX6-Enable WAIT mode by default.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00170212: MX6 - Implement a SW workaround for TKT065875
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00170434: MX6 - Add support to read Silicon version
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00170141: Fix debug messages generated by CPUFREQ
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00170005: Enable DVFS-CORE at boot
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00163052: CPUFREQ does not report correct frequency
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00162319: MX6 - Add support for updated VDDARM...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00162460:MX6-Revert "MX6-Disable PLL1 when CPU...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00162318: MX6: Donot power down PLL when PLL is...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00161487: Fix SD/USB/FEC performance issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00160492: MX6-Disable PLL1 when CPU clk is below...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00160296: MX6-Added secondary and dependent clocks...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00160397: Fix build break caused by DVFS-CORE driver
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00159641: MX6-Add DVFS-CORE support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00159959: MX6-Updated CPU voltages for different...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00155879: MX6: Enable ARM core to enter WAIT mode...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00156153: MX6- Fix bugs in clock code.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00155981: MX6: Fix crash caused by cpufreq during...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00155958: MX6: Fix bug in setting parent of periph_clk
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00155715: MX6: Fix warnings is clock and cpufreq...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00139280: MX6: Add CPUFREQ support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00154748: MX5x: Add CPUFREQ and DVFS support to...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00153913: MX6x - Fix bug in set_parent and set_rate...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00153507: Mx6q/d- Add the support to change the...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00151891: MX50-Fix bug in exit from LPAPM mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00152172: MX5x- Port bus_freq driver to 2.6.38...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00143294-3: MX50-Port DVFS-CORE and bus_freq driver...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00143294-2: MX5x-Port DVFS-CORE and bus_freq driver...
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00143294-1: Fix bug in MC13892 driver
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00142020-3: MX50: Add SPI and MC13892 support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00142020-2: MX50: Add SPI and MC13892 support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00142020-1: MX50: Add SPI and MC13892 support
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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2013-05-24 Ranjani VaidyanathanENGR00141399-1 Add MX50 support for 2.6.38
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Linux kernel for KaRo TX COM modules