Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

   1 * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
   2
   3 Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
   4 controller instances named DMAC capable of serving multiple clients. Channels
   5 can be dedicated to specific clients or shared between a large number of
   6 clients.
   7
   8 Each DMA client is connected to one dedicated port of the DMAC, identified by
   9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
  10 256 clients in total. When the number of hardware channels is lower than the
  11 number of clients to be served, channels must be shared between multiple DMA
  12 clients. The association of DMA clients to DMAC channels is fully dynamic and
  13 not described in these device tree bindings.
  14
  15 Required Properties:
  16
  17 - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
  18               Examples with soctypes are:
  19                 - "renesas,dmac-r8a7743" (RZ/G1M)
  20                 - "renesas,dmac-r8a7745" (RZ/G1E)
  21                 - "renesas,dmac-r8a7790" (R-Car H2)
  22                 - "renesas,dmac-r8a7791" (R-Car M2-W)
  23                 - "renesas,dmac-r8a7792" (R-Car V2H)
  24                 - "renesas,dmac-r8a7793" (R-Car M2-N)
  25                 - "renesas,dmac-r8a7794" (R-Car E2)
  26                 - "renesas,dmac-r8a7795" (R-Car H3)
  27                 - "renesas,dmac-r8a7796" (R-Car M3-W)
  28
  29 - reg: base address and length of the registers block for the DMAC
  30
  31 - interrupts: interrupt specifiers for the DMAC, one for each entry in
  32   interrupt-names.
  33 - interrupt-names: one entry for the error interrupt, named "error", plus one
  34   entry per channel, named "ch%u", where %u is the channel number ranging from
  35   zero to the number of channels minus one.
  36
  37 - clock-names: "fck" for the functional clock
  38 - clocks: a list of phandle + clock-specifier pairs, one for each entry
  39   in clock-names.
  40 - clock-names: must contain "fck" for the functional clock.
  41
  42 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  43   connected to the DMA client
  44 - dma-channels: number of DMA channels
  45
  46 Example: R8A7790 (R-Car H2) SYS-DMACs
  47
  48         dmac0: dma-controller@e6700000 {
  49                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  50                 reg = <0 0xe6700000 0 0x20000>;
  51                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
  52                               0 200 IRQ_TYPE_LEVEL_HIGH
  53                               0 201 IRQ_TYPE_LEVEL_HIGH
  54                               0 202 IRQ_TYPE_LEVEL_HIGH
  55                               0 203 IRQ_TYPE_LEVEL_HIGH
  56                               0 204 IRQ_TYPE_LEVEL_HIGH
  57                               0 205 IRQ_TYPE_LEVEL_HIGH
  58                               0 206 IRQ_TYPE_LEVEL_HIGH
  59                               0 207 IRQ_TYPE_LEVEL_HIGH
  60                               0 208 IRQ_TYPE_LEVEL_HIGH
  61                               0 209 IRQ_TYPE_LEVEL_HIGH
  62                               0 210 IRQ_TYPE_LEVEL_HIGH
  63                               0 211 IRQ_TYPE_LEVEL_HIGH
  64                               0 212 IRQ_TYPE_LEVEL_HIGH
  65                               0 213 IRQ_TYPE_LEVEL_HIGH
  66                               0 214 IRQ_TYPE_LEVEL_HIGH>;
  67                 interrupt-names = "error",
  68                                 "ch0", "ch1", "ch2", "ch3",
  69                                 "ch4", "ch5", "ch6", "ch7",
  70                                 "ch8", "ch9", "ch10", "ch11",
  71                                 "ch12", "ch13", "ch14";
  72                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
  73                 clock-names = "fck";
  74                 #dma-cells = <1>;
  75                 dma-channels = <15>;
  76         };
  77
  78         dmac1: dma-controller@e6720000 {
  79                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  80                 reg = <0 0xe6720000 0 0x20000>;
  81                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  82                               0 216 IRQ_TYPE_LEVEL_HIGH
  83                               0 217 IRQ_TYPE_LEVEL_HIGH
  84                               0 218 IRQ_TYPE_LEVEL_HIGH
  85                               0 219 IRQ_TYPE_LEVEL_HIGH
  86                               0 308 IRQ_TYPE_LEVEL_HIGH
  87                               0 309 IRQ_TYPE_LEVEL_HIGH
  88                               0 310 IRQ_TYPE_LEVEL_HIGH
  89                               0 311 IRQ_TYPE_LEVEL_HIGH
  90                               0 312 IRQ_TYPE_LEVEL_HIGH
  91                               0 313 IRQ_TYPE_LEVEL_HIGH
  92                               0 314 IRQ_TYPE_LEVEL_HIGH
  93                               0 315 IRQ_TYPE_LEVEL_HIGH
  94                               0 316 IRQ_TYPE_LEVEL_HIGH
  95                               0 317 IRQ_TYPE_LEVEL_HIGH
  96                               0 318 IRQ_TYPE_LEVEL_HIGH>;
  97                 interrupt-names = "error",
  98                                 "ch0", "ch1", "ch2", "ch3",
  99                                 "ch4", "ch5", "ch6", "ch7",
 100                                 "ch8", "ch9", "ch10", "ch11",
 101                                 "ch12", "ch13", "ch14";
 102                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 103                 clock-names = "fck";
 104                 #dma-cells = <1>;
 105                 dma-channels = <15>;
 106         };