1 Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
2 ------------------------------------------------------------
4 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
5 representation of DRIF interfacing with a master device is shown below.
7 +---------------------+ +---------------------+
8 | |-----SCK------->|CLK |
9 | Master |-----SS-------->|SYNC DRIFn (slave) |
10 | |-----SD0------->|D0 |
11 | |-----SD1------->|D1 |
12 +---------------------+ +---------------------+
14 As per datasheet, each DRIF channel (drifn) is made up of two internal
15 channels (drifn0 & drifn1). These two internal channels share the common
16 CLK & SYNC. Each internal channel has its own dedicated resources like
17 irq, dma channels, address space & clock. This internal split is not
18 visible to the external master device.
20 The device tree model represents each internal channel as a separate node.
21 The internal channels sharing the CLK & SYNC are tied together by their
22 phandles using a property called "renesas,bonding". For the rest of
23 the documentation, unless explicitly stated, the word channel implies an
26 When both internal channels are enabled they need to be managed together
27 as one (i.e.) they cannot operate alone as independent devices. Out of the
28 two, one of them needs to act as a primary device that accepts common
29 properties of both the internal channels. This channel is identified by a
30 property called "renesas,primary-bond".
33 - When both the internal channels that are bonded together are enabled,
34 the zeroth channel is selected as primary-bond. This channels accepts
35 properties common to all the members of the bond.
36 - When only one of the bonded channels need to be enabled, the property
37 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
38 enabled channel can act alone as any other independent device.
40 Required properties of an internal channel:
41 -------------------------------------------
42 - compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
43 "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
45 When compatible with the generic version, nodes must list the
46 SoC-specific version corresponding to the platform first
47 followed by the generic version.
49 - reg: offset and length of that channel.
50 - interrupts: associated with that channel.
51 - clocks: phandle and clock specifier of that channel.
52 - clock-names: clock input name string: "fck".
53 - dmas: phandles to the DMA channels.
54 - dma-names: names of the DMA channel: "rx".
55 - renesas,bonding: phandle to the other channel.
57 Optional properties of an internal channel:
58 -------------------------------------------
59 - power-domains: phandle to the respective power domain.
61 Required properties of an internal channel when:
62 - It is the only enabled channel of the bond (or)
63 - If it acts as primary among enabled bonds
64 --------------------------------------------------------
65 - pinctrl-0: pin control group to be used for this channel.
66 - pinctrl-names: must be "default".
67 - renesas,primary-bond: empty property indicating the channel acts as primary
68 among the bonded channels.
69 - port: child port node corresponding to the data input, in accordance with
70 the video interface bindings defined in
71 Documentation/devicetree/bindings/media/video-interfaces.txt. The port
72 node must contain at least one endpoint.
74 Optional endpoint property:
75 ---------------------------
76 - sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
77 This property maps to SYNCAC bit in the hardware manual. The
78 default is 1 (active high).
83 (1) Both internal channels enabled:
84 -----------------------------------
86 When interfacing with a third party tuner device with two data pins as shown
89 +---------------------+ +---------------------+
90 | |-----SCK------->|CLK |
91 | Master |-----SS-------->|SYNC DRIFn (slave) |
92 | |-----SD0------->|D0 |
93 | |-----SD1------->|D1 |
94 +---------------------+ +---------------------+
96 drif00: rif@e6f40000 {
97 compatible = "renesas,r8a7795-drif",
98 "renesas,rcar-gen3-drif";
99 reg = <0 0xe6f40000 0 0x64>;
100 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cpg CPG_MOD 515>;
103 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
104 dma-names = "rx", "rx";
105 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
106 renesas,bonding = <&drif01>;
107 renesas,primary-bond;
108 pinctrl-0 = <&drif0_pins>;
109 pinctrl-names = "default";
112 remote-endpoint = <&tuner_ep>;
117 drif01: rif@e6f50000 {
118 compatible = "renesas,r8a7795-drif",
119 "renesas,rcar-gen3-drif";
120 reg = <0 0xe6f50000 0 0x64>;
121 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&cpg CPG_MOD 514>;
124 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
125 dma-names = "rx", "rx";
126 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
127 renesas,bonding = <&drif00>;
131 (2) Internal channel 1 alone is enabled:
132 ----------------------------------------
134 When interfacing with a third party tuner device with one data pin as shown
137 +---------------------+ +---------------------+
138 | |-----SCK------->|CLK |
139 | Master |-----SS-------->|SYNC DRIFn (slave) |
141 | |-----SD-------->|D1 |
142 +---------------------+ +---------------------+
144 drif00: rif@e6f40000 {
145 compatible = "renesas,r8a7795-drif",
146 "renesas,rcar-gen3-drif";
147 reg = <0 0xe6f40000 0 0x64>;
148 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&cpg CPG_MOD 515>;
151 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
152 dma-names = "rx", "rx";
153 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
154 renesas,bonding = <&drif01>;
157 drif01: rif@e6f50000 {
158 compatible = "renesas,r8a7795-drif",
159 "renesas,rcar-gen3-drif";
160 reg = <0 0xe6f50000 0 0x64>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cpg CPG_MOD 514>;
164 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
165 dma-names = "rx", "rx";
166 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
167 renesas,bonding = <&drif00>;
168 pinctrl-0 = <&drif0_pins>;
169 pinctrl-names = "default";
172 remote-endpoint = <&tuner_ep>;