1 * Allwinner sun8i GMAC ethernet controller
3 This device is a platform glue layer for stmmac.
4 Please see stmmac.txt for the other unchanged properties.
7 - compatible: should be one of the following string:
8 "allwinner,sun8i-a83t-emac"
9 "allwinner,sun8i-h3-emac"
10 "allwinner,sun8i-v3s-emac"
11 "allwinner,sun50i-a64-emac"
12 - reg: address and length of the register for the device.
13 - interrupts: interrupt for the device
14 - interrupt-names: should be "macirq"
15 - clocks: A phandle to the reference clock for this device
16 - clock-names: should be "stmmaceth"
17 - resets: A phandle to the reset control for this device
18 - reset-names: should be "stmmaceth"
19 - phy-mode: See ethernet.txt
20 - phy-handle: See ethernet.txt
21 - #address-cells: shall be 1
22 - #size-cells: shall be 0
23 - syscon: A phandle to the syscon of the SoC with one of the following
25 - allwinner,sun8i-h3-system-controller
26 - allwinner,sun8i-v3s-system-controller
27 - allwinner,sun50i-a64-system-controller
28 - allwinner,sun8i-a83t-system-controller
31 - allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
32 - allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
33 Both delay properties need to be a multiple of 100. They control the delay for
36 Optional properties for the following compatibles:
37 - "allwinner,sun8i-h3-emac",
38 - "allwinner,sun8i-v3s-emac":
39 - allwinner,leds-active-low: EPHY LEDs are active low
41 Required child node of emac:
42 - mdio bus node: should be named mdio
44 Required properties of the mdio node:
45 - #address-cells: shall be 1
46 - #size-cells: shall be 0
48 The device node referenced by "phy" or "phy-handle" should be a child node
49 of the mdio node. See phy.txt for the generic PHY bindings.
51 Required properties of the phy node with the following compatibles:
52 - "allwinner,sun8i-h3-emac",
53 - "allwinner,sun8i-v3s-emac":
54 - clocks: a phandle to the reference clock for the EPHY
55 - resets: a phandle to the reset control for the EPHY
59 emac: ethernet@1c0b000 {
60 compatible = "allwinner,sun8i-h3-emac";
62 reg = <0x01c0b000 0x104>;
63 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
64 interrupt-names = "macirq";
65 resets = <&ccu RST_BUS_EMAC>;
66 reset-names = "stmmaceth";
67 clocks = <&ccu CLK_BUS_EMAC>;
68 clock-names = "stmmaceth";
72 phy-handle = <&int_mii_phy>;
74 allwinner,leds-active-low;
78 int_mii_phy: ethernet-phy@1 {
80 clocks = <&ccu CLK_BUS_EPHY>;
81 resets = <&ccu RST_BUS_EPHY>;