1 MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
3 PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
4 ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
7 - compatible: Should contain "mediatek,mt7623-pcie".
8 - device_type: Must be "pci"
9 - reg: Base addresses and lengths of the PCIe controller.
10 - #address-cells: Address representation for root ports (must be 3)
11 - #size-cells: Size representation for root ports (must be 2)
12 - #interrupt-cells: Size representation for interrupts (must be 1)
13 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
14 Please refer to the standard PCI bus binding document for a more detailed
16 - clocks: Must contain an entry for each entry in clock-names.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: Must include the following entries:
19 - free_ck :for reference clock of PCIe subsys
20 - sys_ck0 :for clock of Port0
21 - sys_ck1 :for clock of Port1
22 - sys_ck2 :for clock of Port2
23 - resets: Must contain an entry for each entry in reset-names.
24 See ../reset/reset.txt for details.
25 - reset-names: Must include the following entries:
26 - pcie-rst0 :port0 reset
27 - pcie-rst1 :port1 reset
28 - pcie-rst2 :port2 reset
29 - phys: List of PHY specifiers (used by generic PHY framework).
30 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
31 number of PHYs as specified in *phys* property.
32 - power-domains: A phandle and power domain specifier pair to the power domain
33 which is responsible for collapsing and restoring power to the peripheral.
34 - bus-range: Range of bus numbers associated with this controller.
35 - ranges: Ranges for the PCI memory and I/O regions.
37 In addition, the device tree node must have sub-nodes describing each
38 PCIe port interface, having the following mandatory properties:
41 - device_type: Must be "pci"
42 - reg: Only the first four bytes are used to refer to the correct bus number
44 - #address-cells: Must be 3
45 - #size-cells: Must be 2
46 - #interrupt-cells: Must be 1
47 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
48 Please refer to the standard PCI bus binding document for a more detailed
50 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
51 property is sufficient.
52 - num-lanes: Number of lanes to use for this port.
56 hifsys: syscon@1a000000 {
57 compatible = "mediatek,mt7623-hifsys",
58 "mediatek,mt2701-hifsys",
60 reg = <0 0x1a000000 0 0x1000>;
65 pcie: pcie-controller@1a140000 {
66 compatible = "mediatek,mt7623-pcie";
68 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
69 <0 0x1a142000 0 0x1000>, /* Port0 registers */
70 <0 0x1a143000 0 0x1000>, /* Port1 registers */
71 <0 0x1a144000 0 0x1000>; /* Port2 registers */
74 #interrupt-cells = <1>;
75 interrupt-map-mask = <0xf800 0 0 0>;
76 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
77 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
78 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
79 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
80 <&hifsys CLK_HIFSYS_PCIE0>,
81 <&hifsys CLK_HIFSYS_PCIE1>,
82 <&hifsys CLK_HIFSYS_PCIE2>;
83 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
84 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
85 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
86 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
87 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
88 phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
89 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
90 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
91 bus-range = <0x00 0xff>;
92 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
93 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
97 reg = <0x0000 0 0 0 0>;
100 #interrupt-cells = <1>;
101 interrupt-map-mask = <0 0 0 0>;
102 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
109 reg = <0x0800 0 0 0 0>;
110 #address-cells = <3>;
112 #interrupt-cells = <1>;
113 interrupt-map-mask = <0 0 0 0>;
114 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
121 reg = <0x1000 0 0 0 0>;
122 #address-cells = <3>;
124 #interrupt-cells = <1>;
125 interrupt-map-mask = <0 0 0 0>;
126 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;