arch/arm/boot/dts/armada-385.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 385 SoC.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "armada-38x.dtsi"
  16
  17 / {
  18         model = "Marvell Armada 385 family SoC";
  19         compatible = "marvell,armada385", "marvell,armada38x";
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         reg = <0>;
  28                 };
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                 };
  34         };
  35
  36         soc {
  37                 internal-regs {
  38                         pinctrl {
  39                                 compatible = "marvell,mv88f6820-pinctrl";
  40                                 reg = <0x18000 0x20>;
  41                         };
  42                 };
  43
  44                 pcie-controller {
  45                         compatible = "marvell,armada-370-pcie";
  46                         status = "disabled";
  47                         device_type = "pci";
  48
  49                         #address-cells = <3>;
  50                         #size-cells = <2>;
  51
  52                         msi-parent = <&mpic>;
  53                         bus-range = <0x00 0xff>;
  54
  55                         ranges =
  56                                <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  57                                 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  58                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  59                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
  60                                 0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
  61                                 0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
  62                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
  63                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
  64                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
  65                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
  66                                 0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
  67                                 0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
  68
  69                         /*
  70                          * This port can be either x4 or x1. When
  71                          * configured in x4 by the bootloader, then
  72                          * pcie@4,0 is not available.
  73                          */
  74                         pcie@1,0 {
  75                                 device_type = "pci";
  76                                 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  77                                 reg = <0x0800 0 0 0 0>;
  78                                 #address-cells = <3>;
  79                                 #size-cells = <2>;
  80                                 #interrupt-cells = <1>;
  81                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  82                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  83                                 interrupt-map-mask = <0 0 0 0>;
  84                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  85                                 marvell,pcie-port = <0>;
  86                                 marvell,pcie-lane = <0>;
  87                                 clocks = <&gateclk 8>;
  88                                 status = "disabled";
  89                         };
  90
  91                         /* x1 port */
  92                         pcie@2,0 {
  93                                 device_type = "pci";
  94                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  95                                 reg = <0x1000 0 0 0 0>;
  96                                 #address-cells = <3>;
  97                                 #size-cells = <2>;
  98                                 #interrupt-cells = <1>;
  99                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 100                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 101                                 interrupt-map-mask = <0 0 0 0>;
 102                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 103                                 marvell,pcie-port = <1>;
 104                                 marvell,pcie-lane = <0>;
 105                                 clocks = <&gateclk 5>;
 106                                 status = "disabled";
 107                         };
 108
 109                         /* x1 port */
 110                         pcie@3,0 {
 111                                 device_type = "pci";
 112                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 113                                 reg = <0x1000 0 0 0 0>;
 114                                 #address-cells = <3>;
 115                                 #size-cells = <2>;
 116                                 #interrupt-cells = <1>;
 117                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 118                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 119                                 interrupt-map-mask = <0 0 0 0>;
 120                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 121                                 marvell,pcie-port = <2>;
 122                                 marvell,pcie-lane = <0>;
 123                                 clocks = <&gateclk 6>;
 124                                 status = "disabled";
 125                         };
 126
 127                         /*
 128                          * x1 port only available when pcie@1,0 is
 129                          * configured as a x1 port
 130                          */
 131                         pcie@4,0 {
 132                                 device_type = "pci";
 133                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 134                                 reg = <0x1000 0 0 0 0>;
 135                                 #address-cells = <3>;
 136                                 #size-cells = <2>;
 137                                 #interrupt-cells = <1>;
 138                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 139                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 140                                 interrupt-map-mask = <0 0 0 0>;
 141                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 142                                 marvell,pcie-port = <3>;
 143                                 marvell,pcie-lane = <0>;
 144                                 clocks = <&gateclk 7>;
 145                                 status = "disabled";
 146                         };
 147                 };
 148         };
 149 };