arch/arm/boot/dts/armada-38x.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 38x family of SoCs.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This file is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This file is distributed in the hope that it will be useful,
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 #include "skeleton.dtsi"
  50 #include <dt-bindings/interrupt-controller/arm-gic.h>
  51 #include <dt-bindings/interrupt-controller/irq.h>
  52
  53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  54
  55 / {
  56         model = "Marvell Armada 38x family SoC";
  57         compatible = "marvell,armada380";
  58
  59         aliases {
  60                 gpio0 = &gpio0;
  61                 gpio1 = &gpio1;
  62                 serial0 = &uart0;
  63                 serial1 = &uart1;
  64         };
  65
  66         pmu {
  67                 compatible = "arm,cortex-a9-pmu";
  68                 interrupts-extended = <&mpic 3>;
  69         };
  70
  71         soc {
  72                 compatible = "marvell,armada380-mbus", "simple-bus";
  73                 #address-cells = <2>;
  74                 #size-cells = <1>;
  75                 controller = <&mbusc>;
  76                 interrupt-parent = <&gic>;
  77                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  78                 pcie-io-aperture  = <0xe8000000 0x100000>;
  79
  80                 bootrom {
  81                         compatible = "marvell,bootrom";
  82                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  83                 };
  84
  85                 devbus_bootcs: devbus-bootcs {
  86                         compatible = "marvell,mvebu-devbus";
  87                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  88                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         clocks = <&coreclk 0>;
  92                         status = "disabled";
  93                 };
  94
  95                 devbus_cs0: devbus-cs0 {
  96                         compatible = "marvell,mvebu-devbus";
  97                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  98                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         clocks = <&coreclk 0>;
 102                         status = "disabled";
 103                 };
 104
 105                 devbus_cs1: devbus-cs1 {
 106                         compatible = "marvell,mvebu-devbus";
 107                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
 108                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         clocks = <&coreclk 0>;
 112                         status = "disabled";
 113                 };
 114
 115                 devbus_cs2: devbus-cs2 {
 116                         compatible = "marvell,mvebu-devbus";
 117                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 118                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         clocks = <&coreclk 0>;
 122                         status = "disabled";
 123                 };
 124
 125                 devbus_cs3: devbus-cs3 {
 126                         compatible = "marvell,mvebu-devbus";
 127                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 128                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         clocks = <&coreclk 0>;
 132                         status = "disabled";
 133                 };
 134
 135                 internal-regs {
 136                         compatible = "simple-bus";
 137                         #address-cells = <1>;
 138                         #size-cells = <1>;
 139                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 140
 141                         L2: cache-controller@8000 {
 142                                 compatible = "arm,pl310-cache";
 143                                 reg = <0x8000 0x1000>;
 144                                 cache-unified;
 145                                 cache-level = <2>;
 146                                 arm,double-linefill-incr = <1>;
 147                                 arm,double-linefill-wrap = <0>;
 148                                 arm,double-linefill = <1>;
 149                                 prefetch-data = <1>;
 150                         };
 151
 152                         scu@c000 {
 153                                 compatible = "arm,cortex-a9-scu";
 154                                 reg = <0xc000 0x58>;
 155                         };
 156
 157                         timer@c600 {
 158                                 compatible = "arm,cortex-a9-twd-timer";
 159                                 reg = <0xc600 0x20>;
 160                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 161                                 clocks = <&coreclk 2>;
 162                         };
 163
 164                         gic: interrupt-controller@d000 {
 165                                 compatible = "arm,cortex-a9-gic";
 166                                 #interrupt-cells = <3>;
 167                                 #size-cells = <0>;
 168                                 interrupt-controller;
 169                                 reg = <0xd000 0x1000>,
 170                                       <0xc100 0x100>;
 171                         };
 172
 173                         i2c0: i2c@11000 {
 174                                 compatible = "marvell,mv64xxx-i2c";
 175                                 reg = <0x11000 0x20>;
 176                                 #address-cells = <1>;
 177                                 #size-cells = <0>;
 178                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 179                                 timeout-ms = <1000>;
 180                                 clocks = <&coreclk 0>;
 181                                 status = "disabled";
 182                         };
 183
 184                         i2c1: i2c@11100 {
 185                                 compatible = "marvell,mv64xxx-i2c";
 186                                 reg = <0x11100 0x20>;
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 190                                 timeout-ms = <1000>;
 191                                 clocks = <&coreclk 0>;
 192                                 status = "disabled";
 193                         };
 194
 195                         uart0: serial@12000 {
 196                                 compatible = "snps,dw-apb-uart";
 197                                 reg = <0x12000 0x100>;
 198                                 reg-shift = <2>;
 199                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 200                                 reg-io-width = <1>;
 201                                 clocks = <&coreclk 0>;
 202                                 status = "disabled";
 203                         };
 204
 205                         uart1: serial@12100 {
 206                                 compatible = "snps,dw-apb-uart";
 207                                 reg = <0x12100 0x100>;
 208                                 reg-shift = <2>;
 209                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 210                                 reg-io-width = <1>;
 211                                 clocks = <&coreclk 0>;
 212                                 status = "disabled";
 213                         };
 214
 215                         pinctrl: pinctrl@18000 {
 216                                 reg = <0x18000 0x20>;
 217
 218                                 ge0_rgmii_pins: ge-rgmii-pins-0 {
 219                                         marvell,pins = "mpp6", "mpp7", "mpp8",
 220                                                        "mpp9", "mpp10", "mpp11",
 221                                                        "mpp12", "mpp13", "mpp14",
 222                                                        "mpp15", "mpp16", "mpp17";
 223                                         marvell,function = "ge0";
 224                                 };
 225
 226                                 ge1_rgmii_pins: ge-rgmii-pins-1 {
 227                                         marvell,pins = "mpp21", "mpp27", "mpp28",
 228                                                        "mpp29", "mpp30", "mpp31",
 229                                                        "mpp32", "mpp37", "mpp38",
 230                                                        "mpp39", "mpp40", "mpp41";
 231                                         marvell,function = "ge1";
 232                                 };
 233
 234                                 i2c0_pins: i2c-pins-0 {
 235                                         marvell,pins = "mpp2", "mpp3";
 236                                         marvell,function = "i2c0";
 237                                 };
 238
 239                                 mdio_pins: mdio-pins {
 240                                         marvell,pins = "mpp4", "mpp5";
 241                                         marvell,function = "ge";
 242                                 };
 243
 244                                 ref_clk0_pins: ref-clk-pins-0 {
 245                                         marvell,pins = "mpp45";
 246                                         marvell,function = "ref";
 247                                 };
 248
 249                                 ref_clk1_pins: ref-clk-pins-1 {
 250                                         marvell,pins = "mpp46";
 251                                         marvell,function = "ref";
 252                                 };
 253
 254                                 spi0_pins: spi-pins-0 {
 255                                         marvell,pins = "mpp22", "mpp23", "mpp24",
 256                                                        "mpp25";
 257                                         marvell,function = "spi0";
 258                                 };
 259
 260                                 spi1_pins: spi-pins-1 {
 261                                         marvell,pins = "mpp56", "mpp57", "mpp58",
 262                                                        "mpp59";
 263                                         marvell,function = "spi1";
 264                                 };
 265
 266                                 nand_pins: nand-pins {
 267                                         marvell,pins = "mpp22", "mpp34", "mpp23",
 268                                                        "mpp33", "mpp38", "mpp28",
 269                                                        "mpp40", "mpp42", "mpp35",
 270                                                        "mpp36", "mpp25", "mpp30",
 271                                                        "mpp32";
 272                                         marvell,function = "dev";
 273                                 };
 274
 275                                 uart0_pins: uart-pins-0 {
 276                                         marvell,pins = "mpp0", "mpp1";
 277                                         marvell,function = "ua0";
 278                                 };
 279
 280                                 uart1_pins: uart-pins-1 {
 281                                         marvell,pins = "mpp19", "mpp20";
 282                                         marvell,function = "ua1";
 283                                 };
 284
 285                                 sdhci_pins: sdhci-pins {
 286                                         marvell,pins = "mpp48", "mpp49", "mpp50",
 287                                                        "mpp52", "mpp53", "mpp54",
 288                                                        "mpp55", "mpp57", "mpp58",
 289                                                        "mpp59";
 290                                         marvell,function = "sd0";
 291                                 };
 292
 293                                 sata0_pins: sata-pins-0 {
 294                                         marvell,pins = "mpp20";
 295                                         marvell,function = "sata0";
 296                                 };
 297
 298                                 sata1_pins: sata-pins-1 {
 299                                         marvell,pins = "mpp19";
 300                                         marvell,function = "sata1";
 301                                 };
 302
 303                                 sata2_pins: sata-pins-2 {
 304                                         marvell,pins = "mpp47";
 305                                         marvell,function = "sata2";
 306                                 };
 307
 308                                 sata3_pins: sata-pins-3 {
 309                                         marvell,pins = "mpp44";
 310                                         marvell,function = "sata3";
 311                                 };
 312                         };
 313
 314                         gpio0: gpio@18100 {
 315                                 compatible = "marvell,armada-370-gpio",
 316                                              "marvell,orion-gpio";
 317                                 reg = <0x18100 0x40>, <0x181c0 0x08>;
 318                                 reg-names = "gpio", "pwm";
 319                                 ngpios = <32>;
 320                                 gpio-controller;
 321                                 #gpio-cells = <2>;
 322                                 #pwm-cells = <2>;
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <2>;
 325                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 326                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 327                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&coreclk 0>;
 330                         };
 331
 332                         gpio1: gpio@18140 {
 333                                 compatible = "marvell,armada-370-gpio",
 334                                              "marvell,orion-gpio";
 335                                 reg = <0x18140 0x40>, <0x181c8 0x08>;
 336                                 reg-names = "gpio", "pwm";
 337                                 ngpios = <28>;
 338                                 gpio-controller;
 339                                 #gpio-cells = <2>;
 340                                 #pwm-cells = <2>;
 341                                 interrupt-controller;
 342                                 #interrupt-cells = <2>;
 343                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 345                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 346                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&coreclk 0>;
 348                         };
 349
 350                         systemc: system-controller@18200 {
 351                                 compatible = "marvell,armada-380-system-controller",
 352                                              "marvell,armada-370-xp-system-controller";
 353                                 reg = <0x18200 0x100>;
 354                         };
 355
 356                         gateclk: clock-gating-control@18220 {
 357                                 compatible = "marvell,armada-380-gating-clock";
 358                                 reg = <0x18220 0x4>;
 359                                 clocks = <&coreclk 0>;
 360                                 #clock-cells = <1>;
 361                         };
 362
 363                         coreclk: mvebu-sar@18600 {
 364                                 compatible = "marvell,armada-380-core-clock";
 365                                 reg = <0x18600 0x04>;
 366                                 #clock-cells = <1>;
 367                         };
 368
 369                         mbusc: mbus-controller@20000 {
 370                                 compatible = "marvell,mbus-controller";
 371                                 reg = <0x20000 0x100>, <0x20180 0x20>,
 372                                       <0x20250 0x8>;
 373                         };
 374
 375                         mpic: interrupt-controller@20a00 {
 376                                 compatible = "marvell,mpic";
 377                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 378                                 #interrupt-cells = <1>;
 379                                 #size-cells = <1>;
 380                                 interrupt-controller;
 381                                 msi-controller;
 382                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 383                         };
 384
 385                         timer: timer@20300 {
 386                                 compatible = "marvell,armada-380-timer",
 387                                              "marvell,armada-xp-timer";
 388                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 389                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 390                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 391                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 392                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 393                                                       <&mpic 5>,
 394                                                       <&mpic 6>;
 395                                 clocks = <&coreclk 2>, <&refclk>;
 396                                 clock-names = "nbclk", "fixed";
 397                         };
 398
 399                         watchdog: watchdog@20300 {
 400                                 compatible = "marvell,armada-380-wdt";
 401                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
 402                                 clocks = <&coreclk 2>, <&refclk>;
 403                                 clock-names = "nbclk", "fixed";
 404                         };
 405
 406                         cpurst: cpurst@20800 {
 407                                 compatible = "marvell,armada-370-cpu-reset";
 408                                 reg = <0x20800 0x10>;
 409                         };
 410
 411                         mpcore-soc-ctrl@20d20 {
 412                                 compatible = "marvell,armada-380-mpcore-soc-ctrl";
 413                                 reg = <0x20d20 0x6c>;
 414                         };
 415
 416                         coherencyfab: coherency-fabric@21010 {
 417                                 compatible = "marvell,armada-380-coherency-fabric";
 418                                 reg = <0x21010 0x1c>;
 419                         };
 420
 421                         pmsu: pmsu@22000 {
 422                                 compatible = "marvell,armada-380-pmsu";
 423                                 reg = <0x22000 0x1000>;
 424                         };
 425
 426                         /*
 427                          * As a special exception to the "order by
 428                          * register address" rule, the eth0 node is
 429                          * placed here to ensure that it gets
 430                          * registered as the first interface, since
 431                          * the network subsystem doesn't allow naming
 432                          * interfaces using DT aliases. Without this,
 433                          * the ordering of interfaces is different
 434                          * from the one used in U-Boot and the
 435                          * labeling of interfaces on the boards, which
 436                          * is very confusing for users.
 437                          */
 438                         eth0: ethernet@70000 {
 439                                 compatible = "marvell,armada-370-neta";
 440                                 reg = <0x70000 0x4000>;
 441                                 interrupts-extended = <&mpic 8>;
 442                                 clocks = <&gateclk 4>;
 443                                 tx-csum-limit = <9800>;
 444                                 status = "disabled";
 445                         };
 446
 447                         eth1: ethernet@30000 {
 448                                 compatible = "marvell,armada-370-neta";
 449                                 reg = <0x30000 0x4000>;
 450                                 interrupts-extended = <&mpic 10>;
 451                                 clocks = <&gateclk 3>;
 452                                 status = "disabled";
 453                         };
 454
 455                         eth2: ethernet@34000 {
 456                                 compatible = "marvell,armada-370-neta";
 457                                 reg = <0x34000 0x4000>;
 458                                 interrupts-extended = <&mpic 12>;
 459                                 clocks = <&gateclk 2>;
 460                                 status = "disabled";
 461                         };
 462
 463                         usb0: usb@58000 {
 464                                 compatible = "marvell,orion-ehci";
 465                                 reg = <0x58000 0x500>;
 466                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 467                                 clocks = <&gateclk 18>;
 468                                 status = "disabled";
 469                         };
 470
 471                         xor0: xor@60800 {
 472                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
 473                                 reg = <0x60800 0x100
 474                                        0x60a00 0x100>;
 475                                 clocks = <&gateclk 22>;
 476                                 status = "okay";
 477
 478                                 xor00 {
 479                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 480                                         dmacap,memcpy;
 481                                         dmacap,xor;
 482                                 };
 483                                 xor01 {
 484                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 485                                         dmacap,memcpy;
 486                                         dmacap,xor;
 487                                         dmacap,memset;
 488                                 };
 489                         };
 490
 491                         xor1: xor@60900 {
 492                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
 493                                 reg = <0x60900 0x100
 494                                        0x60b00 0x100>;
 495                                 clocks = <&gateclk 28>;
 496                                 status = "okay";
 497
 498                                 xor10 {
 499                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 500                                         dmacap,memcpy;
 501                                         dmacap,xor;
 502                                 };
 503                                 xor11 {
 504                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 505                                         dmacap,memcpy;
 506                                         dmacap,xor;
 507                                         dmacap,memset;
 508                                 };
 509                         };
 510
 511                         mdio: mdio@72004 {
 512                                 #address-cells = <1>;
 513                                 #size-cells = <0>;
 514                                 compatible = "marvell,orion-mdio";
 515                                 reg = <0x72004 0x4>;
 516                                 clocks = <&gateclk 4>;
 517                         };
 518
 519                         cesa: crypto@90000 {
 520                                 compatible = "marvell,armada-38x-crypto";
 521                                 reg = <0x90000 0x10000>;
 522                                 reg-names = "regs";
 523                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 524                                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 525                                 clocks = <&gateclk 23>, <&gateclk 21>,
 526                                          <&gateclk 14>, <&gateclk 16>;
 527                                 clock-names = "cesa0", "cesa1",
 528                                               "cesaz0", "cesaz1";
 529                                 marvell,crypto-srams = <&crypto_sram0>,
 530                                                        <&crypto_sram1>;
 531                                 marvell,crypto-sram-size = <0x800>;
 532                         };
 533
 534                         rtc: rtc@a3800 {
 535                                 compatible = "marvell,armada-380-rtc";
 536                                 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
 537                                 reg-names = "rtc", "rtc-soc";
 538                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 539                         };
 540
 541                         ahci0: sata@a8000 {
 542                                 compatible = "marvell,armada-380-ahci";
 543                                 reg = <0xa8000 0x2000>;
 544                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 545                                 clocks = <&gateclk 15>;
 546                                 status = "disabled";
 547                         };
 548
 549                         bm: bm@c8000 {
 550                                 compatible = "marvell,armada-380-neta-bm";
 551                                 reg = <0xc8000 0xac>;
 552                                 clocks = <&gateclk 13>;
 553                                 internal-mem = <&bm_bppi>;
 554                                 status = "disabled";
 555                         };
 556
 557                         ahci1: sata@e0000 {
 558                                 compatible = "marvell,armada-380-ahci";
 559                                 reg = <0xe0000 0x2000>;
 560                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 561                                 clocks = <&gateclk 30>;
 562                                 status = "disabled";
 563                         };
 564
 565                         coredivclk: clock@e4250 {
 566                                 compatible = "marvell,armada-380-corediv-clock";
 567                                 reg = <0xe4250 0xc>;
 568                                 #clock-cells = <1>;
 569                                 clocks = <&mainpll>;
 570                                 clock-output-names = "nand";
 571                         };
 572
 573                         thermal: thermal@e8078 {
 574                                 compatible = "marvell,armada380-thermal";
 575                                 reg = <0xe4078 0x4>, <0xe4074 0x4>;
 576                                 status = "okay";
 577                         };
 578
 579                         nand: flash@d0000 {
 580                                 compatible = "marvell,armada370-nand";
 581                                 reg = <0xd0000 0x54>;
 582                                 #address-cells = <1>;
 583                                 #size-cells = <1>;
 584                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&coredivclk 0>;
 586                                 status = "disabled";
 587                         };
 588
 589                         sdhci: sdhci@d8000 {
 590                                 compatible = "marvell,armada-380-sdhci";
 591                                 reg-names = "sdhci", "mbus", "conf-sdio3";
 592                                 reg = <0xd8000 0x1000>,
 593                                         <0xdc000 0x100>,
 594                                         <0x18454 0x4>;
 595                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 596                                 clocks = <&gateclk 17>;
 597                                 mrvl,clk-delay-cycles = <0x1F>;
 598                                 status = "disabled";
 599                         };
 600
 601                         usb3_0: usb3@f0000 {
 602                                 compatible = "marvell,armada-380-xhci";
 603                                 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
 604                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 605                                 clocks = <&gateclk 9>;
 606                                 status = "disabled";
 607                         };
 608
 609                         usb3_1: usb3@f8000 {
 610                                 compatible = "marvell,armada-380-xhci";
 611                                 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
 612                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&gateclk 10>;
 614                                 status = "disabled";
 615                         };
 616                 };
 617
 618                 crypto_sram0: sa-sram0 {
 619                         compatible = "mmio-sram";
 620                         reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
 621                         clocks = <&gateclk 23>;
 622                         #address-cells = <1>;
 623                         #size-cells = <1>;
 624                         ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
 625                 };
 626
 627                 crypto_sram1: sa-sram1 {
 628                         compatible = "mmio-sram";
 629                         reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
 630                         clocks = <&gateclk 21>;
 631                         #address-cells = <1>;
 632                         #size-cells = <1>;
 633                         ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
 634                 };
 635
 636                 bm_bppi: bm-bppi {
 637                         compatible = "mmio-sram";
 638                         reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
 639                         ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
 640                         #address-cells = <1>;
 641                         #size-cells = <1>;
 642                         clocks = <&gateclk 13>;
 643                         no-memory-wc;
 644                         status = "disabled";
 645                 };
 646
 647                 spi0: spi@10600 {
 648                         compatible = "marvell,armada-380-spi",
 649                                         "marvell,orion-spi";
 650                         reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653                         cell-index = <0>;
 654                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 655                         clocks = <&coreclk 0>;
 656                         status = "disabled";
 657                 };
 658
 659                 spi1: spi@10680 {
 660                         compatible = "marvell,armada-380-spi",
 661                                         "marvell,orion-spi";
 662                         reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                         cell-index = <1>;
 666                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&coreclk 0>;
 668                         status = "disabled";
 669                 };
 670         };
 671
 672         clocks {
 673                 /* 1 GHz fixed main PLL */
 674                 mainpll: mainpll {
 675                         compatible = "fixed-clock";
 676                         #clock-cells = <0>;
 677                         clock-frequency = <1000000000>;
 678                 };
 679
 680                 /* 25 MHz reference crystal */
 681                 refclk: oscillator {
 682                         compatible = "fixed-clock";
 683                         #clock-cells = <0>;
 684                         clock-frequency = <25000000>;
 685                 };
 686         };
 687 };