arch/arm/boot/dts/armada-xp.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License as
  18  *     published by the Free Software Foundation; either version 2 of the
  19  *     License, or (at your option) any later version.
  20  *
  21  *     This file is distributed in the hope that it will be useful
  22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  *     GNU General Public License for more details.
  25  *
  26  * Or, alternatively
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  *
  49  * Contains definitions specific to the Armada XP SoC that are not
  50  * common to all Armada SoCs.
  51  */
  52
  53 #include "armada-370-xp.dtsi"
  54
  55 / {
  56         model = "Marvell Armada XP family SoC";
  57         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
  58
  59         aliases {
  60                 serial2 = &uart2;
  61                 serial3 = &uart3;
  62         };
  63
  64         soc {
  65                 compatible = "marvell,armadaxp-mbus", "simple-bus";
  66
  67                 bootrom {
  68                         compatible = "marvell,bootrom";
  69                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  70                 };
  71
  72                 internal-regs {
  73                         sdramc@1400 {
  74                                 compatible = "marvell,armada-xp-sdram-controller";
  75                                 reg = <0x1400 0x500>;
  76                         };
  77
  78                         L2: l2-cache {
  79                                 compatible = "marvell,aurora-system-cache";
  80                                 reg = <0x08000 0x1000>;
  81                                 cache-id-part = <0x100>;
  82                                 cache-level = <2>;
  83                                 cache-unified;
  84                                 wt-override;
  85                         };
  86
  87                         spi0: spi@10600 {
  88                                 compatible = "marvell,armada-xp-spi",
  89                                                 "marvell,orion-spi";
  90                                 pinctrl-0 = <&spi0_pins>;
  91                                 pinctrl-names = "default";
  92                         };
  93
  94                         spi1: spi@10680 {
  95                                 compatible = "marvell,armada-xp-spi",
  96                                                 "marvell,orion-spi";
  97                         };
  98
  99
 100                         i2c0: i2c@11000 {
 101                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 102                                 reg = <0x11000 0x100>;
 103                         };
 104
 105                         i2c1: i2c@11100 {
 106                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 107                                 reg = <0x11100 0x100>;
 108                         };
 109
 110                         uart2: serial@12200 {
 111                                 compatible = "snps,dw-apb-uart";
 112                                 pinctrl-0 = <&uart2_pins>;
 113                                 pinctrl-names = "default";
 114                                 reg = <0x12200 0x100>;
 115                                 reg-shift = <2>;
 116                                 interrupts = <43>;
 117                                 reg-io-width = <1>;
 118                                 clocks = <&coreclk 0>;
 119                                 status = "disabled";
 120                         };
 121
 122                         uart3: serial@12300 {
 123                                 compatible = "snps,dw-apb-uart";
 124                                 pinctrl-0 = <&uart3_pins>;
 125                                 pinctrl-names = "default";
 126                                 reg = <0x12300 0x100>;
 127                                 reg-shift = <2>;
 128                                 interrupts = <44>;
 129                                 reg-io-width = <1>;
 130                                 clocks = <&coreclk 0>;
 131                                 status = "disabled";
 132                         };
 133
 134                         system-controller@18200 {
 135                                 compatible = "marvell,armada-370-xp-system-controller";
 136                                 reg = <0x18200 0x500>;
 137                         };
 138
 139                         gateclk: clock-gating-control@18220 {
 140                                 compatible = "marvell,armada-xp-gating-clock";
 141                                 reg = <0x18220 0x4>;
 142                                 clocks = <&coreclk 0>;
 143                                 #clock-cells = <1>;
 144                         };
 145
 146                         coreclk: mvebu-sar@18230 {
 147                                 compatible = "marvell,armada-xp-core-clock";
 148                                 reg = <0x18230 0x08>;
 149                                 #clock-cells = <1>;
 150                         };
 151
 152                         thermal@182b0 {
 153                                 compatible = "marvell,armadaxp-thermal";
 154                                 reg = <0x182b0 0x4
 155                                         0x184d0 0x4>;
 156                                 status = "okay";
 157                         };
 158
 159                         cpuclk: clock-complex@18700 {
 160                                 #clock-cells = <1>;
 161                                 compatible = "marvell,armada-xp-cpu-clock";
 162                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
 163                                 clocks = <&coreclk 1>;
 164                         };
 165
 166                         interrupt-controller@20a00 {
 167                               reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 168                         };
 169
 170                         timer@20300 {
 171                                 compatible = "marvell,armada-xp-timer";
 172                                 clocks = <&coreclk 2>, <&refclk>;
 173                                 clock-names = "nbclk", "fixed";
 174                         };
 175
 176                         watchdog@20300 {
 177                                 compatible = "marvell,armada-xp-wdt";
 178                                 clocks = <&coreclk 2>, <&refclk>;
 179                                 clock-names = "nbclk", "fixed";
 180                         };
 181
 182                         cpurst@20800 {
 183                                 compatible = "marvell,armada-370-cpu-reset";
 184                                 reg = <0x20800 0x20>;
 185                         };
 186
 187                         cpu-config@21000 {
 188                                 compatible = "marvell,armada-xp-cpu-config";
 189                                 reg = <0x21000 0x8>;
 190                         };
 191
 192                         eth2: ethernet@30000 {
 193                                 compatible = "marvell,armada-xp-neta";
 194                                 reg = <0x30000 0x4000>;
 195                                 interrupts = <12>;
 196                                 clocks = <&gateclk 2>;
 197                                 status = "disabled";
 198                         };
 199
 200                         usb@50000 {
 201                                 clocks = <&gateclk 18>;
 202                         };
 203
 204                         usb@51000 {
 205                                 clocks = <&gateclk 19>;
 206                         };
 207
 208                         usb@52000 {
 209                                 compatible = "marvell,orion-ehci";
 210                                 reg = <0x52000 0x500>;
 211                                 interrupts = <47>;
 212                                 clocks = <&gateclk 20>;
 213                                 status = "disabled";
 214                         };
 215
 216                         xor@60900 {
 217                                 compatible = "marvell,orion-xor";
 218                                 reg = <0x60900 0x100
 219                                        0x60b00 0x100>;
 220                                 clocks = <&gateclk 22>;
 221                                 status = "okay";
 222
 223                                 xor10 {
 224                                         interrupts = <51>;
 225                                         dmacap,memcpy;
 226                                         dmacap,xor;
 227                                 };
 228                                 xor11 {
 229                                         interrupts = <52>;
 230                                         dmacap,memcpy;
 231                                         dmacap,xor;
 232                                         dmacap,memset;
 233                                 };
 234                         };
 235
 236                         ethernet@70000 {
 237                                 compatible = "marvell,armada-xp-neta";
 238                         };
 239
 240                         ethernet@74000 {
 241                                 compatible = "marvell,armada-xp-neta";
 242                         };
 243
 244                         crypto@90000 {
 245                                 compatible = "marvell,armada-xp-crypto";
 246                                 reg = <0x90000 0x10000>;
 247                                 reg-names = "regs";
 248                                 interrupts = <48>, <49>;
 249                                 clocks = <&gateclk 23>, <&gateclk 23>;
 250                                 clock-names = "cesa0", "cesa1";
 251                                 marvell,crypto-srams = <&crypto_sram0>,
 252                                                        <&crypto_sram1>;
 253                                 marvell,crypto-sram-size = <0x800>;
 254                         };
 255
 256                         xor@f0900 {
 257                                 compatible = "marvell,orion-xor";
 258                                 reg = <0xF0900 0x100
 259                                        0xF0B00 0x100>;
 260                                 clocks = <&gateclk 28>;
 261                                 status = "okay";
 262
 263                                 xor00 {
 264                                         interrupts = <94>;
 265                                         dmacap,memcpy;
 266                                         dmacap,xor;
 267                                 };
 268                                 xor01 {
 269                                         interrupts = <95>;
 270                                         dmacap,memcpy;
 271                                         dmacap,xor;
 272                                         dmacap,memset;
 273                                 };
 274                         };
 275                 };
 276
 277                 crypto_sram0: sa-sram0 {
 278                         compatible = "mmio-sram";
 279                         reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
 280                         clocks = <&gateclk 23>;
 281                         #address-cells = <1>;
 282                         #size-cells = <1>;
 283                         ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
 284                 };
 285
 286                 crypto_sram1: sa-sram1 {
 287                         compatible = "mmio-sram";
 288                         reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
 289                         clocks = <&gateclk 23>;
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                         ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
 293                 };
 294         };
 295
 296         clocks {
 297                 /* 25 MHz reference crystal */
 298                 refclk: oscillator {
 299                         compatible = "fixed-clock";
 300                         #clock-cells = <0>;
 301                         clock-frequency = <25000000>;
 302                 };
 303         };
 304 };
 305
 306 &pinctrl {
 307         ge0_gmii_pins: ge0-gmii-pins {
 308                 marvell,pins =
 309                      "mpp0",  "mpp1",  "mpp2",  "mpp3",
 310                      "mpp4",  "mpp5",  "mpp6",  "mpp7",
 311                      "mpp8",  "mpp9",  "mpp10", "mpp11",
 312                      "mpp12", "mpp13", "mpp14", "mpp15",
 313                      "mpp16", "mpp17", "mpp18", "mpp19",
 314                      "mpp20", "mpp21", "mpp22", "mpp23";
 315                 marvell,function = "ge0";
 316         };
 317
 318         ge0_rgmii_pins: ge0-rgmii-pins {
 319                 marvell,pins =
 320                      "mpp0", "mpp1", "mpp2", "mpp3",
 321                      "mpp4", "mpp5", "mpp6", "mpp7",
 322                      "mpp8", "mpp9", "mpp10", "mpp11";
 323                 marvell,function = "ge0";
 324         };
 325
 326         ge1_rgmii_pins: ge1-rgmii-pins {
 327                 marvell,pins =
 328                      "mpp12", "mpp13", "mpp14", "mpp15",
 329                      "mpp16", "mpp17", "mpp18", "mpp19",
 330                      "mpp20", "mpp21", "mpp22", "mpp23";
 331                 marvell,function = "ge1";
 332         };
 333
 334         sdio_pins: sdio-pins {
 335                 marvell,pins = "mpp30", "mpp31", "mpp32",
 336                                "mpp33", "mpp34", "mpp35";
 337                 marvell,function = "sd0";
 338         };
 339
 340         spi0_pins: spi0-pins {
 341                 marvell,pins = "mpp36", "mpp37",
 342                                "mpp38", "mpp39";
 343                 marvell,function = "spi0";
 344         };
 345
 346         uart2_pins: uart2-pins {
 347                 marvell,pins = "mpp42", "mpp43";
 348                 marvell,function = "uart2";
 349         };
 350
 351         uart3_pins: uart3-pins {
 352                 marvell,pins = "mpp44", "mpp45";
 353                 marvell,function = "uart3";
 354         };
 355 };