arch/arm/boot/dts/bcm11351.dtsi

   1 /*
   2  * Copyright (C) 2012-2013 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 #include "skeleton.dtsi"
  18
  19 / {
  20         model = "BCM11351 SoC";
  21         compatible = "brcm,bcm11351";
  22         interrupt-parent = <&gic>;
  23
  24         chosen {
  25                 bootargs = "console=ttyS0,115200n8";
  26         };
  27
  28         gic: interrupt-controller@3ff00100 {
  29                 compatible = "arm,cortex-a9-gic";
  30                 #interrupt-cells = <3>;
  31                 #address-cells = <0>;
  32                 interrupt-controller;
  33                 reg = <0x3ff01000 0x1000>,
  34                       <0x3ff00100 0x100>;
  35         };
  36
  37         smc@0x3404c000 {
  38                 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
  39                 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
  40         };
  41
  42         uart@3e000000 {
  43                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  44                 status = "disabled";
  45                 reg = <0x3e000000 0x1000>;
  46                 clock-frequency = <13000000>;
  47                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  48                 reg-shift = <2>;
  49                 reg-io-width = <4>;
  50         };
  51
  52         L2: l2-cache {
  53                 compatible = "brcm,bcm11351-a2-pl310-cache";
  54                 reg = <0x3ff20000 0x1000>;
  55                 cache-unified;
  56                 cache-level = <2>;
  57         };
  58
  59         watchdog@35002f40 {
  60                 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
  61                 reg = <0x35002f40 0x6c>;
  62         };
  63
  64         timer@35006000 {
  65                 compatible = "brcm,kona-timer";
  66                 reg = <0x35006000 0x1000>;
  67                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  68                 clock-frequency = <32768>;
  69         };
  70
  71         sdio1: sdio@3f180000 {
  72                 compatible = "brcm,kona-sdhci";
  73                 reg = <0x3f180000 0x10000>;
  74                 interrupts = <0x0 77 0x4>;
  75                 status = "disabled";
  76         };
  77
  78         sdio2: sdio@3f190000 {
  79                 compatible = "brcm,kona-sdhci";
  80                 reg = <0x3f190000 0x10000>;
  81                 interrupts = <0x0 76 0x4>;
  82                 status = "disabled";
  83         };
  84
  85         sdio3: sdio@3f1a0000 {
  86                 compatible = "brcm,kona-sdhci";
  87                 reg = <0x3f1a0000 0x10000>;
  88                 interrupts = <0x0 74 0x4>;
  89                 status = "disabled";
  90         };
  91
  92         sdio4: sdio@3f1b0000 {
  93                 compatible = "brcm,kona-sdhci";
  94                 reg = <0x3f1b0000 0x10000>;
  95                 interrupts = <0x0 73 0x4>;
  96                 status = "disabled";
  97         };
  98
  99 };