2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
41 compatible = "arm,arm926ej-s";
47 compatible = "simple-bus";
50 reg = <0x80000000 0x80000>;
54 compatible = "simple-bus";
57 reg = <0x80000000 0x3c900>;
60 icoll: interrupt-controller@80000000 {
61 compatible = "fsl,imx28-icoll", "fsl,icoll";
63 #interrupt-cells = <1>;
64 reg = <0x80000000 0x2000>;
67 hsadc: hsadc@80002000 {
68 reg = <0x80002000 0x2000>;
70 dmas = <&dma_apbh 12>;
75 dma_apbh: dma-apbh@80004000 {
76 compatible = "fsl,imx28-dma-apbh";
77 reg = <0x80004000 0x2000>;
78 interrupts = <82 83 84 85
82 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
83 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
84 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
85 "hsadc", "lcdif", "empty", "empty";
91 perfmon: perfmon@80006000 {
92 reg = <0x80006000 0x800>;
97 gpmi: gpmi-nand@8000c000 {
98 compatible = "fsl,imx28-gpmi-nand";
101 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
102 reg-names = "gpmi-nand", "bch";
104 interrupt-names = "bch";
106 clock-names = "gpmi_io";
107 dmas = <&dma_apbh 4>;
113 #address-cells = <1>;
115 reg = <0x80010000 0x2000>;
118 dmas = <&dma_apbh 0>;
124 #address-cells = <1>;
126 reg = <0x80012000 0x2000>;
129 dmas = <&dma_apbh 1>;
135 #address-cells = <1>;
137 reg = <0x80014000 0x2000>;
140 dmas = <&dma_apbh 2>;
146 #address-cells = <1>;
148 reg = <0x80016000 0x2000>;
151 dmas = <&dma_apbh 3>;
156 pinctrl: pinctrl@80018000 {
157 #address-cells = <1>;
159 compatible = "fsl,imx28-pinctrl", "simple-bus";
160 reg = <0x80018000 0x2000>;
163 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
167 interrupt-controller;
168 #interrupt-cells = <2>;
172 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
176 interrupt-controller;
177 #interrupt-cells = <2>;
181 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
185 interrupt-controller;
186 #interrupt-cells = <2>;
190 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
194 interrupt-controller;
195 #interrupt-cells = <2>;
199 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
203 interrupt-controller;
204 #interrupt-cells = <2>;
207 duart_pins_a: duart@0 {
210 0x3102 /* MX28_PAD_PWM0__DUART_RX */
211 0x3112 /* MX28_PAD_PWM1__DUART_TX */
213 fsl,drive-strength = <0>;
218 duart_pins_b: duart@1 {
221 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
222 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
224 fsl,drive-strength = <0>;
229 duart_4pins_a: duart-4pins@0 {
232 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
233 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
234 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
235 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
237 fsl,drive-strength = <0>;
242 gpmi_pins_a: gpmi-nand@0 {
245 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
246 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
247 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
248 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
249 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
250 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
251 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
252 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
253 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
254 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
255 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
256 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
257 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
258 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
259 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
261 fsl,drive-strength = <0>;
266 gpmi_status_cfg: gpmi-status-cfg {
268 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
269 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
270 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
272 fsl,drive-strength = <2>;
275 auart0_pins_a: auart0@0 {
278 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
279 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
280 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
281 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
283 fsl,drive-strength = <0>;
288 auart0_2pins_a: auart0-2pins@0 {
291 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
292 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
294 fsl,drive-strength = <0>;
299 auart1_pins_a: auart1@0 {
302 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
303 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
304 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
305 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
307 fsl,drive-strength = <0>;
312 auart1_2pins_a: auart1-2pins@0 {
315 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
316 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
318 fsl,drive-strength = <0>;
323 auart2_2pins_a: auart2-2pins@0 {
326 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
327 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
329 fsl,drive-strength = <0>;
334 auart2_2pins_b: auart2-2pins@1 {
337 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
338 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
340 fsl,drive-strength = <0>;
345 auart3_pins_a: auart3@0 {
348 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
349 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
350 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
351 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
353 fsl,drive-strength = <0>;
358 auart3_2pins_a: auart3-2pins@0 {
361 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
362 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
364 fsl,drive-strength = <0>;
369 auart3_2pins_b: auart3-2pins@1 {
372 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
373 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
375 fsl,drive-strength = <0>;
380 auart4_2pins_a: auart4@0 {
383 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
384 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
386 fsl,drive-strength = <0>;
391 mac0_pins_a: mac0@0 {
394 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
395 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
396 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
397 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
398 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
399 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
400 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
401 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
402 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
404 fsl,drive-strength = <1>;
409 mac1_pins_a: mac1@0 {
412 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
413 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
414 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
415 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
416 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
417 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
419 fsl,drive-strength = <1>;
424 mmc0_8bit_pins_a: mmc0-8bit@0 {
427 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
428 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
429 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
430 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
431 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
432 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
433 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
434 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
435 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
436 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
437 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
439 fsl,drive-strength = <1>;
444 mmc0_4bit_pins_a: mmc0-4bit@0 {
447 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
448 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
449 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
450 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
451 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
452 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
453 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
455 fsl,drive-strength = <1>;
460 mmc0_cd_cfg: mmc0-cd-cfg {
462 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
467 mmc0_sck_cfg: mmc0-sck-cfg {
469 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
471 fsl,drive-strength = <2>;
475 i2c0_pins_a: i2c0@0 {
478 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
479 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
481 fsl,drive-strength = <1>;
486 i2c0_pins_b: i2c0@1 {
489 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
490 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
492 fsl,drive-strength = <1>;
497 i2c1_pins_a: i2c1@0 {
500 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
501 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
503 fsl,drive-strength = <1>;
508 saif0_pins_a: saif0@0 {
511 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
512 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
513 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
514 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
516 fsl,drive-strength = <2>;
521 saif0_pins_b: saif0@1 {
524 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
525 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
526 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
528 fsl,drive-strength = <2>;
533 saif1_pins_a: saif1@0 {
536 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
538 fsl,drive-strength = <2>;
543 pwm0_pins_a: pwm0@0 {
546 0x3100 /* MX28_PAD_PWM0__PWM_0 */
548 fsl,drive-strength = <0>;
553 pwm2_pins_a: pwm2@0 {
556 0x3120 /* MX28_PAD_PWM2__PWM_2 */
558 fsl,drive-strength = <0>;
563 pwm3_pins_a: pwm3@0 {
566 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
568 fsl,drive-strength = <0>;
573 pwm3_pins_b: pwm3@1 {
576 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
578 fsl,drive-strength = <0>;
583 pwm4_pins_a: pwm4@0 {
586 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
588 fsl,drive-strength = <0>;
593 lcdif_24bit_pins_a: lcdif-24bit@0 {
596 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
597 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
598 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
599 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
600 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
601 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
602 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
603 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
604 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
605 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
606 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
607 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
608 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
609 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
610 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
611 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
612 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
613 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
614 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
615 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
616 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
617 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
618 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
619 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
621 fsl,drive-strength = <0>;
626 lcdif_16bit_pins_a: lcdif-16bit@0 {
629 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
630 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
631 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
632 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
633 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
634 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
635 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
636 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
637 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
638 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
639 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
640 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
641 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
642 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
643 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
644 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
646 fsl,drive-strength = <0>;
651 can0_pins_a: can0@0 {
654 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
655 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
657 fsl,drive-strength = <0>;
662 can1_pins_a: can1@0 {
665 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
666 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
668 fsl,drive-strength = <0>;
673 spi2_pins_a: spi2@0 {
676 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
677 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
678 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
679 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
681 fsl,drive-strength = <1>;
686 spi3_pins_a: spi3@0 {
689 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */
690 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */
691 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */
692 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */
693 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */
694 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */
696 fsl,drive-strength = <1>;
701 usbphy0_pins_a: usbphy0@0 {
704 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
706 fsl,drive-strength = <2>;
711 usbphy0_pins_b: usbphy0@1 {
714 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
716 fsl,drive-strength = <2>;
721 usbphy1_pins_a: usbphy1@0 {
724 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
726 fsl,drive-strength = <2>;
732 digctl: digctl@8001c000 {
733 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
734 reg = <0x8001c000 0x2000>;
740 reg = <0x80022000 0x2000>;
744 dma_apbx: dma-apbx@80024000 {
745 compatible = "fsl,imx28-dma-apbx";
746 reg = <0x80024000 0x2000>;
747 interrupts = <78 79 66 0
751 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
752 "saif0", "saif1", "i2c0", "i2c1",
753 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
754 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
761 reg = <0x80028000 0x2000>;
762 interrupts = <52 53 54>;
763 compatible = "fsl-dcp";
767 reg = <0x8002a000 0x2000>;
772 ocotp: ocotp@8002c000 {
773 compatible = "fsl,ocotp";
774 reg = <0x8002c000 0x2000>;
779 reg = <0x8002e000 0x2000>;
783 lcdif: lcdif@80030000 {
784 compatible = "fsl,imx28-lcdif";
785 reg = <0x80030000 0x2000>;
788 dmas = <&dma_apbh 13>;
794 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
795 reg = <0x80032000 0x2000>;
797 clocks = <&clks 58>, <&clks 58>;
798 clock-names = "ipg", "per";
803 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
804 reg = <0x80034000 0x2000>;
806 clocks = <&clks 59>, <&clks 59>;
807 clock-names = "ipg", "per";
811 simdbg: simdbg@8003c000 {
812 reg = <0x8003c000 0x200>;
816 simgpmisel: simgpmisel@8003c200 {
817 reg = <0x8003c200 0x100>;
821 simsspsel: simsspsel@8003c300 {
822 reg = <0x8003c300 0x100>;
826 simmemsel: simmemsel@8003c400 {
827 reg = <0x8003c400 0x100>;
831 gpiomon: gpiomon@8003c500 {
832 reg = <0x8003c500 0x100>;
836 simenet: simenet@8003c700 {
837 reg = <0x8003c700 0x100>;
841 armjtag: armjtag@8003c800 {
842 reg = <0x8003c800 0x100>;
848 compatible = "simple-bus";
849 #address-cells = <1>;
851 reg = <0x80040000 0x40000>;
854 clks: clkctrl@80040000 {
855 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
856 reg = <0x80040000 0x2000>;
860 saif0: saif@80042000 {
861 compatible = "fsl,imx28-saif";
862 reg = <0x80042000 0x2000>;
866 dmas = <&dma_apbx 4>;
871 power: power@80044000 {
872 reg = <0x80044000 0x2000>;
876 saif1: saif@80046000 {
877 compatible = "fsl,imx28-saif";
878 reg = <0x80046000 0x2000>;
881 dmas = <&dma_apbx 5>;
886 lradc: lradc@80050000 {
887 compatible = "fsl,imx28-lradc";
888 reg = <0x80050000 0x2000>;
889 interrupts = <10 14 15 16 17 18 19
894 spdif: spdif@80054000 {
895 reg = <0x80054000 0x2000>;
897 dmas = <&dma_apbx 2>;
902 mxs_rtc: rtc@80056000 {
903 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
904 reg = <0x80056000 0x2000>;
909 #address-cells = <1>;
911 compatible = "fsl,imx28-i2c";
912 reg = <0x80058000 0x2000>;
914 clock-frequency = <100000>;
915 dmas = <&dma_apbx 6>;
921 #address-cells = <1>;
923 compatible = "fsl,imx28-i2c";
924 reg = <0x8005a000 0x2000>;
926 clock-frequency = <100000>;
927 dmas = <&dma_apbx 7>;
933 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
934 reg = <0x80064000 0x2000>;
937 fsl,pwm-number = <8>;
941 timer: timrot@80068000 {
942 compatible = "fsl,imx28-timrot", "fsl,timrot";
943 reg = <0x80068000 0x2000>;
944 interrupts = <48 49 50 51>;
948 auart0: serial@8006a000 {
949 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
950 reg = <0x8006a000 0x2000>;
952 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
953 dma-names = "rx", "tx";
958 auart1: serial@8006c000 {
959 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
960 reg = <0x8006c000 0x2000>;
962 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
963 dma-names = "rx", "tx";
968 auart2: serial@8006e000 {
969 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
970 reg = <0x8006e000 0x2000>;
972 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
973 dma-names = "rx", "tx";
978 auart3: serial@80070000 {
979 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
980 reg = <0x80070000 0x2000>;
982 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
983 dma-names = "rx", "tx";
988 auart4: serial@80072000 {
989 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
990 reg = <0x80072000 0x2000>;
992 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
993 dma-names = "rx", "tx";
998 duart: serial@80074000 {
999 compatible = "arm,pl011", "arm,primecell";
1000 reg = <0x80074000 0x1000>;
1002 clocks = <&clks 45>, <&clks 26>;
1003 clock-names = "uart", "apb_pclk";
1004 status = "disabled";
1007 usbphy0: usbphy@8007c000 {
1008 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1009 reg = <0x8007c000 0x2000>;
1010 clocks = <&clks 62>;
1011 status = "disabled";
1014 usbphy1: usbphy@8007e000 {
1015 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1016 reg = <0x8007e000 0x2000>;
1017 clocks = <&clks 63>;
1018 status = "disabled";
1024 compatible = "simple-bus";
1025 #address-cells = <1>;
1027 reg = <0x80080000 0x80000>;
1030 usb0: usb@80080000 {
1031 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1032 reg = <0x80080000 0x10000>;
1034 clocks = <&clks 60>;
1035 fsl,usbphy = <&usbphy0>;
1036 status = "disabled";
1039 usb1: usb@80090000 {
1040 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1041 reg = <0x80090000 0x10000>;
1043 clocks = <&clks 61>;
1044 fsl,usbphy = <&usbphy1>;
1045 status = "disabled";
1048 dflpt: dflpt@800c0000 {
1049 reg = <0x800c0000 0x10000>;
1050 status = "disabled";
1053 mac0: ethernet@800f0000 {
1054 compatible = "fsl,imx28-fec";
1055 reg = <0x800f0000 0x4000>;
1057 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1058 clock-names = "ipg", "ahb", "enet_out";
1059 status = "disabled";
1062 mac1: ethernet@800f4000 {
1063 compatible = "fsl,imx28-fec";
1064 reg = <0x800f4000 0x4000>;
1066 clocks = <&clks 57>, <&clks 57>;
1067 clock-names = "ipg", "ahb";
1068 status = "disabled";
1071 etn_switch: switch@800f8000 {
1072 reg = <0x800f8000 0x8000>;
1073 status = "disabled";