arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6qdl.dtsi"
  12 #include "imx6dl-pinfunc.h"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                 };
  24
  25                 cpu@1 {
  26                         compatible = "arm,cortex-a9";
  27                         reg = <1>;
  28                         next-level-cache = <&L2>;
  29                 };
  30         };
  31
  32         soc {
  33                 aips1: aips-bus@02000000 {
  34                         iomuxc: iomuxc@020e0000 {
  35                                 compatible = "fsl,imx6dl-iomuxc";
  36                                 reg = <0x020e0000 0x4000>;
  37
  38                                 enet {
  39                                         pinctrl_enet_1: enetgrp-1 {
  40                                                 fsl,pins = <
  41                                                         MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
  42                                                         MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
  43                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  44                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  45                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  46                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  47                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  48                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  49                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  50                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  51                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  52                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  53                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  54                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  55                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  56                                                         MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
  57                                                 >;
  58                                         };
  59
  60                                         pinctrl_enet_2: enetgrp-2 {
  61                                                 fsl,pins = <
  62                                                         MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
  63                                                         MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
  64                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  65                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  66                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  67                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  68                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  69                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  70                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  71                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  72                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  73                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  74                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  75                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  76                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  77                                                 >;
  78                                         };
  79                                 };
  80
  81                                 gpmi-nand {
  82                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
  83                                                 fsl,pins = <
  84                                                         MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
  85                                                         MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
  86                                                         MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
  87                                                         MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  88                                                         MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
  89                                                         MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
  90                                                         MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
  91                                                         MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
  92                                                         MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
  93                                                         MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
  94                                                         MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
  95                                                         MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
  96                                                         MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
  97                                                         MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
  98                                                         MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
  99                                                         MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 100                                                         MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 101                                                 >;
 102                                         };
 103                                 };
 104
 105                                 uart1 {
 106                                         pinctrl_uart1_1: uart1grp-1 {
 107                                                 fsl,pins = <
 108                                                         MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 109                                                         MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 110                                                 >;
 111                                         };
 112                                 };
 113
 114                                 uart4 {
 115                                         pinctrl_uart4_1: uart4grp-1 {
 116                                                 fsl,pins = <
 117                                                         MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 118                                                         MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 119                                                 >;
 120                                         };
 121                                 };
 122
 123                                 usbotg {
 124                                         pinctrl_usbotg_2: usbotggrp-2 {
 125                                                 fsl,pins = <
 126                                                         MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 127                                                 >;
 128                                         };
 129                                 };
 130
 131                                 usdhc2 {
 132                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 133                                                 fsl,pins = <
 134                                                         MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
 135                                                         MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
 136                                                         MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 137                                                         MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 138                                                         MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 139                                                         MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 140                                                         MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
 141                                                         MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
 142                                                         MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
 143                                                         MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
 144                                                 >;
 145                                         };
 146                                 };
 147
 148                                 usdhc3 {
 149                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 150                                                 fsl,pins = <
 151                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 152                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 153                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 154                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 155                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 156                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 157                                                         MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 158                                                         MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 159                                                         MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 160                                                         MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 161                                                 >;
 162                                         };
 163
 164                                         pinctrl_usdhc3_2: usdhc3grp_2 {
 165                                                 fsl,pins = <
 166                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 167                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 168                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 169                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 170                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 171                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 172                                                 >;
 173                                         };
 174                                 };
 175
 176
 177                         };
 178
 179                         pxp: pxp@020f0000 {
 180                                 reg = <0x020f0000 0x4000>;
 181                                 interrupts = <0 98 0x04>;
 182                         };
 183
 184                         epdc: epdc@020f4000 {
 185                                 reg = <0x020f4000 0x4000>;
 186                                 interrupts = <0 97 0x04>;
 187                         };
 188
 189                         lcdif: lcdif@020f8000 {
 190                                 reg = <0x020f8000 0x4000>;
 191                                 interrupts = <0 39 0x04>;
 192                         };
 193                 };
 194
 195                 aips2: aips-bus@02100000 {
 196                         i2c4: i2c@021f8000 {
 197                                 #address-cells = <1>;
 198                                 #size-cells = <0>;
 199                                 compatible = "fsl,imx1-i2c";
 200                                 reg = <0x021f8000 0x4000>;
 201                                 interrupts = <0 35 0x04>;
 202                                 status = "disabled";
 203                         };
 204                 };
 205         };
 206 };