arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 i2c3 = &i2c4;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 996000  1250000
  32                                 792000  1175000
  33                                 396000  1150000
  34                         >;
  35                         fsl,soc-operating-points = <
  36                                 /* ARM kHz  SOC-PU uV */
  37                                 996000  1175000
  38                                 792000  1175000
  39                                 396000  1175000
  40                         >;
  41                         clock-latency = <61036>; /* two CLK32 periods */
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         soc {
  63                 ocram: sram@00900000 {
  64                         compatible = "mmio-sram";
  65                         reg = <0x00900000 0x20000>;
  66                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  67                 };
  68
  69                 aips1: aips-bus@02000000 {
  70                         iomuxc: iomuxc@020e0000 {
  71                                 compatible = "fsl,imx6dl-iomuxc";
  72                         };
  73
  74                         pxp: pxp@020f0000 {
  75                                 reg = <0x020f0000 0x4000>;
  76                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  77                         };
  78
  79                         epdc: epdc@020f4000 {
  80                                 reg = <0x020f4000 0x4000>;
  81                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  82                         };
  83
  84                         lcdif: lcdif@020f8000 {
  85                                 reg = <0x020f8000 0x4000>;
  86                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
  87                         };
  88                 };
  89
  90                 aips2: aips-bus@02100000 {
  91                         i2c4: i2c@021f8000 {
  92                                 #address-cells = <1>;
  93                                 #size-cells = <0>;
  94                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  95                                 reg = <0x021f8000 0x4000>;
  96                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  97                                 clocks = <&clks IMX6DL_CLK_I2C4>;
  98                                 status = "disabled";
  99                         };
 100                 };
 101         };
 102
 103         capture-subsystem {
 104                 compatible = "fsl,imx-capture-subsystem";
 105                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
 106         };
 107
 108         display-subsystem {
 109                 compatible = "fsl,imx-display-subsystem";
 110                 ports = <&ipu1_di0>, <&ipu1_di1>;
 111         };
 112
 113         gpu-subsystem {
 114                 compatible = "fsl,imx-gpu-subsystem";
 115                 cores = <&gpu_2d>, <&gpu_3d>;
 116         };
 117 };
 118
 119 &gpio1 {
 120         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
 121                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
 122                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
 123                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
 124                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
 125                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
 126                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
 127 };
 128
 129 &gpio2 {
 130         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
 131                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
 132                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
 133                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
 134                       <&iomuxc 28 113 4>;
 135 };
 136
 137 &gpio3 {
 138         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
 139                       <&iomuxc 16 81 16>;
 140 };
 141
 142 &gpio4 {
 143         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
 144                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
 145                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
 146                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
 147                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
 148 };
 149
 150 &gpio5 {
 151         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
 152                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
 153                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
 154                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
 155 };
 156
 157 &gpio6 {
 158         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
 159                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
 160                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
 161                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
 162                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
 163                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
 164 };
 165
 166 &gpio7 {
 167         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
 168                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
 169                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
 170 };
 171
 172 &gpr {
 173         ipu1_csi0_mux: ipu1_csi0_mux@34 {
 174                 compatible = "video-mux";
 175                 mux-controls = <&mux 0>;
 176                 #address-cells = <1>;
 177                 #size-cells = <0>;
 178
 179                 port@0 {
 180                         reg = <0>;
 181
 182                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 183                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 184                         };
 185                 };
 186
 187                 port@1 {
 188                         reg = <1>;
 189
 190                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
 191                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
 192                         };
 193                 };
 194
 195                 port@2 {
 196                         reg = <2>;
 197
 198                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
 199                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
 200                         };
 201                 };
 202
 203                 port@3 {
 204                         reg = <3>;
 205
 206                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
 207                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
 208                         };
 209                 };
 210
 211                 port@4 {
 212                         reg = <4>;
 213
 214                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 215                         };
 216                 };
 217
 218                 port@5 {
 219                         reg = <5>;
 220
 221                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 222                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 223                         };
 224                 };
 225         };
 226
 227         ipu1_csi1_mux: ipu1_csi1_mux@34 {
 228                 compatible = "video-mux";
 229                 mux-controls = <&mux 1>;
 230                 #address-cells = <1>;
 231                 #size-cells = <0>;
 232
 233                 port@0 {
 234                         reg = <0>;
 235
 236                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
 237                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
 238                         };
 239                 };
 240
 241                 port@1 {
 242                         reg = <1>;
 243
 244                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
 245                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
 246                         };
 247                 };
 248
 249                 port@2 {
 250                         reg = <2>;
 251
 252                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
 253                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
 254                         };
 255                 };
 256
 257                 port@3 {
 258                         reg = <3>;
 259
 260                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
 261                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
 262                         };
 263                 };
 264
 265                 port@4 {
 266                         reg = <4>;
 267
 268                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
 269                         };
 270                 };
 271
 272                 port@5 {
 273                         reg = <5>;
 274
 275                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
 276                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
 277                         };
 278                 };
 279         };
 280 };
 281
 282 &gpt {
 283         compatible = "fsl,imx6dl-gpt";
 284 };
 285
 286 &hdmi {
 287         compatible = "fsl,imx6dl-hdmi";
 288 };
 289
 290 &ipu1_csi1 {
 291         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
 292                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
 293         };
 294 };
 295
 296 &ldb {
 297         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 298                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 299                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 300         clock-names = "di0_pll", "di1_pll",
 301                       "di0_sel", "di1_sel",
 302                       "di0", "di1";
 303 };
 304
 305 &mipi_csi {
 306         port@1 {
 307                 reg = <1>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310
 311                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
 312                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 313                 };
 314
 315                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
 316                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
 317                 };
 318         };
 319
 320         port@2 {
 321                 reg = <2>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324
 325                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
 326                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
 327                 };
 328
 329                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
 330                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
 331                 };
 332         };
 333
 334         port@3 {
 335                 reg = <3>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338
 339                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
 340                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
 341                 };
 342
 343                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
 344                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
 345                 };
 346         };
 347
 348         port@4 {
 349                 reg = <4>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352
 353                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
 354                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
 355                 };
 356
 357                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
 358                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
 359                 };
 360         };
 361 };
 362
 363 &mux {
 364         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
 365                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
 366                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 367                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 368                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 369                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 370                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 371 };
 372
 373 &vpu {
 374         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 375 };