arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 996000  1275000
  28                                 792000  1175000
  29                                 396000  1075000
  30                         >;
  31                         fsl,soc-operating-points = <
  32                                 /* ARM kHz  SOC-PU uV */
  33                                 996000  1175000
  34                                 792000  1175000
  35                                 396000  1175000
  36                         >;
  37                         clock-latency = <61036>; /* two CLK32 periods */
  38                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  39                                  <&clks 17>, <&clks 170>;
  40                         clock-names = "arm", "pll2_pfd2_396m", "step",
  41                                       "pll1_sw", "pll1_sys";
  42                         arm-supply = <&reg_arm>;
  43                         pu-supply = <&reg_pu>;
  44                         soc-supply = <&reg_soc>;
  45                 };
  46
  47                 cpu@1 {
  48                         compatible = "arm,cortex-a9";
  49                         device_type = "cpu";
  50                         reg = <1>;
  51                         next-level-cache = <&L2>;
  52                 };
  53         };
  54
  55         soc {
  56
  57                 busfreq { /* BUSFREQ */
  58                         compatible = "fsl,imx6_busfreq";
  59                         clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
  60                                 <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
  61                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
  62                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
  63                         interrupts = <0 107 0x04>, <0 112 0x4>;
  64                         interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
  65                         fsl,max_ddr_freq = <400000000>;
  66                 };
  67
  68                 gpu: gpu@00130000 {
  69                         compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
  70                         reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
  71                               <0x0 0x0>;
  72                         reg-names = "iobase_3d", "iobase_2d",
  73                                     "phys_baseaddr";
  74                         interrupts = <0 9 0x04>, <0 10 0x04>;
  75                         interrupt-names = "irq_3d", "irq_2d";
  76                         clocks = <&clks 143>, <&clks 27>,
  77                                  <&clks 121>, <&clks 122>,
  78                                  <&clks 0>;
  79                         clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
  80                                       "gpu2d_clk", "gpu3d_clk",
  81                                       "gpu3d_shader_clk";
  82                         resets = <&src 0>, <&src 3>;
  83                         reset-names = "gpu3d", "gpu2d";
  84                         pu-supply = <&reg_pu>;
  85                 };
  86
  87                 ocram: sram@00900000 {
  88                         compatible = "mmio-sram";
  89                         reg = <0x00904000 0x1C000>;
  90                         clocks = <&clks 142>;
  91                 };
  92
  93                 hdmi_core: hdmi_core@00120000 {
  94                         compatible = "fsl,imx6dl-hdmi-core";
  95                         reg = <0x00120000 0x9000>;
  96                         clocks = <&clks 124>, <&clks 123>;
  97                         clock-names = "hdmi_isfr", "hdmi_iahb";
  98                         status = "disabled";
  99                 };
 100
 101                 hdmi_video: hdmi_video@020e0000 {
 102                         compatible = "fsl,imx6dl-hdmi-video";
 103                         reg =  <0x020e0000 0x1000>;
 104                         reg-names = "hdmi_gpr";
 105                         interrupts = <0 115 0x04>;
 106                         clocks = <&clks 124>, <&clks 123>;
 107                         clock-names = "hdmi_isfr", "hdmi_iahb";
 108                         status = "disabled";
 109                 };
 110
 111                 hdmi_audio: hdmi_audio@00120000 {
 112                         compatible = "fsl,imx6dl-hdmi-audio";
 113                         clocks = <&clks 124>, <&clks 123>;
 114                         clock-names = "hdmi_isfr", "hdmi_iahb";
 115                         dmas = <&sdma 2 22 0>;
 116                         dma-names = "tx";
 117                         status = "disabled";
 118                 };
 119
 120                 hdmi_cec: hdmi_cec@00120000 {
 121                         compatible = "fsl,imx6dl-hdmi-cec";
 122                         interrupts = <0 115 0x04>;
 123                         status = "disabled";
 124                 };
 125
 126                 aips1: aips-bus@02000000 {
 127                         vpu@02040000 {
 128                                 compatible = "fsl,imx6dl-vpu";
 129                                 iramsize = <0>;
 130                                 status = "okay";
 131                         };
 132
 133                         iomuxc: iomuxc@020e0000 {
 134                                 compatible = "fsl,imx6dl-iomuxc";
 135                         };
 136
 137                         pxp: pxp@020f0000 {
 138                                 compatible = "fsl,imx6dl-pxp-dma";
 139                                 reg = <0x020f0000 0x4000>;
 140                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 141                                 clocks = <&clks 133>;
 142                                 clock-names = "pxp-axi";
 143                                 status = "disabled";
 144                         };
 145
 146                         epdc: epdc@020f4000 {
 147                                 compatible = "fsl,imx6dl-epdc";
 148                                 reg = <0x020f4000 0x4000>;
 149                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 150                                 clocks = <&clks 133>, <&clks 137>;
 151                                 clock-names = "epdc_axi", "epdc_pix";
 152                         };
 153
 154                         lcdif: lcdif@020f8000 {
 155                                 reg = <0x020f8000 0x4000>;
 156                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 157                         };
 158                 };
 159
 160                 aips2: aips-bus@02100000 {
 161                         mipi_dsi: mipi@021e0000 {
 162                                 compatible = "fsl,imx6dl-mipi-dsi";
 163                                 reg = <0x021e0000 0x4000>;
 164                                 interrupts = <0 102 0x04>;
 165                                 gpr = <&gpr>;
 166                                 clocks = <&clks 138>, <&clks 204>;
 167                                 clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
 168                                 status = "disabled";
 169                         };
 170
 171                         i2c4: i2c@021f8000 {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 175                                 reg = <0x021f8000 0x4000>;
 176                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 177                                 status = "disabled";
 178                         };
 179                 };
 180         };
 181
 182         display-subsystem {
 183                 compatible = "fsl,imx-display-subsystem";
 184                 ports = <&ipu1_di0>, <&ipu1_di1>;
 185         };
 186 };
 187
 188 &hdmi {
 189         compatible = "fsl,imx6dl-hdmi";
 190 };
 191
 192 &ldb {
 193         clocks = <&clks 33>, <&clks 34>,
 194                  <&clks 39>, <&clks 40>,
 195                  <&clks 135>, <&clks 136>;
 196         clock-names = "di0_pll", "di1_pll",
 197                       "di0_sel", "di1_sel",
 198                       "di0", "di1";
 199 };