arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 ipu1 = &ipu2;
  18                 spi4 = &ecspi5;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         next-level-cache = <&L2>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 1200000 1275000
  33                                 996000  1250000
  34                                 852000  1250000
  35                                 792000  1150000
  36                                 396000  975000
  37                         >;
  38                         fsl,soc-operating-points = <
  39                                 /* ARM kHz  SOC-PU uV */
  40                                 1200000 1275000
  41                                 996000  1250000
  42                                 852000  1250000
  43                                 792000  1175000
  44                                 396000  1175000
  45                         >;
  46                         clock-latency = <61036>; /* two CLK32 periods */
  47                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  48                                  <&clks 17>, <&clks 170>;
  49                         clock-names = "arm", "pll2_pfd2_396m", "step",
  50                                       "pll1_sw", "pll1_sys";
  51                         arm-supply = <&reg_arm>;
  52                         pu-supply = <&reg_pu>;
  53                         soc-supply = <&reg_soc>;
  54                 };
  55
  56                 cpu@1 {
  57                         compatible = "arm,cortex-a9";
  58                         device_type = "cpu";
  59                         reg = <1>;
  60                         next-level-cache = <&L2>;
  61                 };
  62
  63                 cpu@2 {
  64                         compatible = "arm,cortex-a9";
  65                         device_type = "cpu";
  66                         reg = <2>;
  67                         next-level-cache = <&L2>;
  68                 };
  69
  70                 cpu@3 {
  71                         compatible = "arm,cortex-a9";
  72                         device_type = "cpu";
  73                         reg = <3>;
  74                         next-level-cache = <&L2>;
  75                 };
  76         };
  77
  78         soc {
  79
  80                 busfreq { /* BUSFREQ */
  81                         compatible = "fsl,imx6_busfreq";
  82                         clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
  83                                 <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
  84                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
  85                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
  86                         interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
  87                         interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
  88                         fsl,max_ddr_freq = <528000000>;
  89                 };
  90
  91                 gpu: gpu@00130000 {
  92                         compatible = "fsl,imx6q-gpu";
  93                         reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
  94                               <0x02204000 0x4000>, <0x0 0x0>;
  95                         reg-names = "iobase_3d", "iobase_2d",
  96                                     "iobase_vg", "phys_baseaddr";
  97                         interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
  98                         interrupt-names = "irq_3d", "irq_2d", "irq_vg";
  99                         clocks = <&clks 26>, <&clks 143>,
 100                                  <&clks 27>, <&clks 121>,
 101                                  <&clks 122>, <&clks 74>;
 102                         clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
 103                                       "gpu3d_axi_clk", "gpu2d_clk",
 104                                       "gpu3d_clk", "gpu3d_shader_clk";
 105                         resets = <&src 0>, <&src 3>, <&src 3>;
 106                         reset-names = "gpu3d", "gpu2d", "gpuvg";
 107                         pu-supply = <&reg_pu>;
 108                 };
 109
 110                 ocram: sram@00900000 {
 111                         compatible = "mmio-sram";
 112                         reg = <0x00904000 0x3C000>;
 113                         clocks = <&clks 142>;
 114                 };
 115
 116                 hdmi_core: hdmi_core@00120000 {
 117                         compatible = "fsl,imx6q-hdmi-core";
 118                         reg = <0x00120000 0x9000>;
 119                         clocks = <&clks 124>, <&clks 123>;
 120                         clock-names = "hdmi_isfr", "hdmi_iahb";
 121                         status = "disabled";
 122                 };
 123
 124                 hdmi_video: hdmi_video@020e0000 {
 125                         compatible = "fsl,imx6q-hdmi-video";
 126                         reg = <0x020e0000 0x1000>;
 127                         reg-names = "hdmi_gpr";
 128                         interrupts = <0 115 0x04>;
 129                         clocks = <&clks 124>, <&clks 123>;
 130                         clock-names = "hdmi_isfr", "hdmi_iahb";
 131                         status = "disabled";
 132                 };
 133
 134                 hdmi_audio: hdmi_audio@00120000 {
 135                         compatible = "fsl,imx6q-hdmi-audio";
 136                         clocks = <&clks 124>, <&clks 123>;
 137                         clock-names = "hdmi_isfr", "hdmi_iahb";
 138                         dmas = <&sdma 2 22 0>;
 139                         dma-names = "tx";
 140                         status = "disabled";
 141                 };
 142
 143                 hdmi_cec: hdmi_cec@00120000 {
 144                         compatible = "fsl,imx6q-hdmi-cec";
 145                         interrupts = <0 115 0x04>;
 146                         status = "disabled";
 147                 };
 148
 149
 150                 aips-bus@02000000 { /* AIPS1 */
 151                         spba-bus@02000000 {
 152                                 ecspi5: ecspi@02018000 {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 156                                         reg = <0x02018000 0x4000>;
 157                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 158                                         clocks = <&clks 116>, <&clks 116>;
 159                                         clock-names = "ipg", "per";
 160                                         status = "disabled";
 161                                 };
 162                         };
 163
 164                         vpu@02040000 {
 165                                 compatible = "fsl,imx6q-vpu";
 166                                 status = "okay";
 167                         };
 168
 169                         iomuxc: iomuxc@020e0000 {
 170                                 compatible = "fsl,imx6q-iomuxc";
 171                         };
 172                 };
 173
 174                 aips-bus@02100000 { /* AIPS2 */
 175                         mipi_dsi: mipi@021e0000 {
 176                                 compatible = "fsl,imx6q-mipi-dsi";
 177                                 reg = <0x021e0000 0x4000>;
 178                                 interrupts = <0 102 0x04>;
 179                                 gpr = <&gpr>;
 180                                 clocks = <&clks 138>, <&clks 204>;
 181                                 clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
 182                                 status = "disabled";
 183                         };
 184                 };
 185
 186                 sata: sata@02200000 {
 187                         compatible = "fsl,imx6q-ahci";
 188                         reg = <0x02200000 0x4000>;
 189                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 190                         clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
 191                         clock-names = "sata", "sata_ref", "ahb";
 192                         status = "disabled";
 193                 };
 194
 195                 ipu2: ipu@02800000 {
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                         compatible = "fsl,imx6q-ipu";
 199                         reg = <0x02800000 0x400000>;
 200                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&clks 133>, <&clks 134>, <&clks 137>,
 203                                  <&clks 41>, <&clks 42>,
 204                                  <&clks 135>, <&clks 136>;
 205                         clock-names = "bus", "di0", "di1",
 206                                       "di0_sel", "di1_sel",
 207                                       "ldb_di0", "ldb_di1";
 208                         resets = <&src 4>;
 209                         bypass_reset = <0>;
 210
 211                         ipu2_di0: port@2 {
 212                                 #address-cells = <1>;
 213                                 #size-cells = <0>;
 214                                 reg = <2>;
 215
 216                                 ipu2_di0_disp0: endpoint@0 {
 217                                 };
 218
 219                                 ipu2_di0_hdmi: endpoint@1 {
 220                                         remote-endpoint = <&hdmi_mux_2>;
 221                                 };
 222
 223                                 ipu2_di0_mipi: endpoint@2 {
 224                                 };
 225
 226                                 ipu2_di0_lvds0: endpoint@3 {
 227                                         remote-endpoint = <&lvds0_mux_2>;
 228                                 };
 229
 230                                 ipu2_di0_lvds1: endpoint@4 {
 231                                         remote-endpoint = <&lvds1_mux_2>;
 232                                 };
 233                         };
 234
 235                         ipu2_di1: port@3 {
 236                                 #address-cells = <1>;
 237                                 #size-cells = <0>;
 238                                 reg = <3>;
 239
 240                                 ipu2_di1_hdmi: endpoint@1 {
 241                                         remote-endpoint = <&hdmi_mux_3>;
 242                                 };
 243
 244                                 ipu2_di1_mipi: endpoint@2 {
 245                                 };
 246
 247                                 ipu2_di1_lvds0: endpoint@3 {
 248                                         remote-endpoint = <&lvds0_mux_3>;
 249                                 };
 250
 251                                 ipu2_di1_lvds1: endpoint@4 {
 252                                         remote-endpoint = <&lvds1_mux_3>;
 253                                 };
 254                         };
 255                 };
 256         };
 257
 258         display-subsystem {
 259                 compatible = "fsl,imx-display-subsystem";
 260                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 261         };
 262 };
 263
 264 &hdmi {
 265         compatible = "fsl,imx6q-hdmi";
 266
 267         port@2 {
 268                 reg = <2>;
 269
 270                 hdmi_mux_2: endpoint {
 271                         remote-endpoint = <&ipu2_di0_hdmi>;
 272                 };
 273         };
 274
 275         port@3 {
 276                 reg = <3>;
 277
 278                 hdmi_mux_3: endpoint {
 279                         remote-endpoint = <&ipu2_di1_hdmi>;
 280                 };
 281         };
 282 };
 283
 284 &ldb {
 285         lvds-channel@0 {
 286                 port@2 {
 287                         reg = <2>;
 288
 289                         lvds0_mux_2: endpoint {
 290                                 remote-endpoint = <&ipu2_di0_lvds0>;
 291                         };
 292                 };
 293
 294                 port@3 {
 295                         reg = <3>;
 296
 297                         lvds0_mux_3: endpoint {
 298                                 remote-endpoint = <&ipu2_di1_lvds0>;
 299                         };
 300                 };
 301         };
 302
 303         lvds-channel@1 {
 304                 port@2 {
 305                         reg = <2>;
 306
 307                         lvds1_mux_2: endpoint {
 308                                 remote-endpoint = <&ipu2_di0_lvds1>;
 309                         };
 310                 };
 311
 312                 port@3 {
 313                         reg = <3>;
 314
 315                         lvds1_mux_3: endpoint {
 316                                 remote-endpoint = <&ipu2_di1_lvds1>;
 317                         };
 318                 };
 319         };
 320 };
 321
 322 &mipi_dsi {
 323         port@2 {
 324                 reg = <2>;
 325
 326                 mipi_mux_2: endpoint {
 327                         remote-endpoint = <&ipu2_di0_mipi>;
 328                 };
 329         };
 330
 331         port@3 {
 332                 reg = <3>;
 333
 334                 mipi_mux_3: endpoint {
 335                         remote-endpoint = <&ipu2_di1_mipi>;
 336                 };
 337         };
 338 };