arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         memory {
  24                 reg = <0x10000000 0x80000000>;
  25         };
  26
  27         leds {
  28                 compatible = "gpio-leds";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_gpio_leds>;
  31
  32                 user {
  33                         label = "debug";
  34                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  35                 };
  36         };
  37
  38         sound-spdif {
  39                 compatible = "fsl,imx-audio-spdif",
  40                            "fsl,imx-sabreauto-spdif";
  41                 model = "imx-spdif";
  42                 spdif-controller = <&spdif>;
  43                 spdif-in;
  44         };
  45
  46         backlight {
  47                 compatible = "pwm-backlight";
  48                 pwms = <&pwm3 0 5000000>;
  49                 brightness-levels = <0 4 8 16 32 64 128 255>;
  50                 default-brightness-level = <7>;
  51                 status = "okay";
  52         };
  53
  54         mxcfb1: fb@0 {
  55                 compatible = "fsl,mxc_sdc_fb";
  56                 disp_dev = "ldb";
  57                 interface_pix_fmt = "RGB666";
  58                 mode_str ="LDB-XGA";
  59                 default_bpp = <16>;
  60                 int_clk = <0>;
  61                 late_init = <0>;
  62                 status = "disabled";
  63         };
  64
  65         mxcfb2: fb@1 {
  66                 compatible = "fsl,mxc_sdc_fb";
  67                 disp_dev = "ldb";
  68                 interface_pix_fmt = "RGB666";
  69                 mode_str ="LDB-XGA";
  70                 default_bpp = <16>;
  71                 int_clk = <0>;
  72                 late_init = <0>;
  73                 status = "disabled";
  74         };
  75
  76         mxcfb3: fb@2 {
  77                 compatible = "fsl,mxc_sdc_fb";
  78                 disp_dev = "lcd";
  79                 interface_pix_fmt = "RGB565";
  80                 mode_str ="CLAA-WVGA";
  81                 default_bpp = <16>;
  82                 int_clk = <0>;
  83                 late_init = <0>;
  84                 status = "disabled";
  85         };
  86
  87         mxcfb4: fb@3 {
  88                 compatible = "fsl,mxc_sdc_fb";
  89                 disp_dev = "ldb";
  90                 interface_pix_fmt = "RGB666";
  91                 mode_str ="LDB-XGA";
  92                 default_bpp = <16>;
  93                 int_clk = <0>;
  94                 late_init = <0>;
  95                 status = "disabled";
  96         };
  97
  98         lcd@0 {
  99                 compatible = "fsl,lcd";
 100                 ipu_id = <0>;
 101                 disp_id = <0>;
 102                 default_ifmt = "RGB565";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_ipu1_1>;
 105                 status = "okay";
 106         };
 107
 108         v4l2_cap_0 {
 109                 compatible = "fsl,imx6q-v4l2-capture";
 110                 ipu_id = <0>;
 111                 csi_id = <0>;
 112                 mclk_source = <0>;
 113                 status = "okay";
 114         };
 115
 116         v4l2_cap_1 {
 117                 compatible = "fsl,imx6q-v4l2-capture";
 118                 ipu_id = <0>;
 119                 csi_id = <1>;
 120                 mclk_source = <0>;
 121                 status = "okay";
 122         };
 123
 124         v4l2_out {
 125                 compatible = "fsl,mxc_v4l2_output";
 126                 status = "okay";
 127         };
 128 };
 129
 130 &ecspi1 {
 131         fsl,spi-num-chipselects = <1>;
 132         cs-gpios = <&gpio3 19 0>;
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_ecspi1_1>;
 135         status = "disabled"; /* pin conflict with WEIM NOR */
 136
 137         flash: m25p80@0 {
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 compatible = "st,m25p32";
 141                 spi-max-frequency = <20000000>;
 142                 reg = <0>;
 143         };
 144 };
 145
 146 &fec {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_enet>;
 149         phy-mode = "rgmii";
 150         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 151                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 152         status = "okay";
 153 };
 154
 155 &gpmi {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_gpmi_nand>;
 158         status = "okay";
 159 };
 160
 161 &i2c2 {
 162         clock-frequency = <100000>;
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_i2c2>;
 165         status = "okay";
 166
 167         pmic: pfuze100@08 {
 168                 compatible = "fsl,pfuze100";
 169                 reg = <0x08>;
 170
 171                 regulators {
 172                         sw1a_reg: sw1ab {
 173                                 regulator-min-microvolt = <300000>;
 174                                 regulator-max-microvolt = <1875000>;
 175                                 regulator-boot-on;
 176                                 regulator-always-on;
 177                                 regulator-ramp-delay = <6250>;
 178                         };
 179
 180                         sw1c_reg: sw1c {
 181                                 regulator-min-microvolt = <300000>;
 182                                 regulator-max-microvolt = <1875000>;
 183                                 regulator-boot-on;
 184                                 regulator-always-on;
 185                                 regulator-ramp-delay = <6250>;
 186                         };
 187
 188                         sw2_reg: sw2 {
 189                                 regulator-min-microvolt = <800000>;
 190                                 regulator-max-microvolt = <3300000>;
 191                                 regulator-boot-on;
 192                                 regulator-always-on;
 193                         };
 194
 195                         sw3a_reg: sw3a {
 196                                 regulator-min-microvolt = <400000>;
 197                                 regulator-max-microvolt = <1975000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         sw3b_reg: sw3b {
 203                                 regulator-min-microvolt = <400000>;
 204                                 regulator-max-microvolt = <1975000>;
 205                                 regulator-boot-on;
 206                                 regulator-always-on;
 207                         };
 208
 209                         sw4_reg: sw4 {
 210                                 regulator-min-microvolt = <800000>;
 211                                 regulator-max-microvolt = <3300000>;
 212                         };
 213
 214                         swbst_reg: swbst {
 215                                 regulator-min-microvolt = <5000000>;
 216                                 regulator-max-microvolt = <5150000>;
 217                         };
 218
 219                         snvs_reg: vsnvs {
 220                                 regulator-min-microvolt = <1000000>;
 221                                 regulator-max-microvolt = <3000000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225
 226                         vref_reg: vrefddr {
 227                                 regulator-boot-on;
 228                                 regulator-always-on;
 229                         };
 230
 231                         vgen1_reg: vgen1 {
 232                                 regulator-min-microvolt = <800000>;
 233                                 regulator-max-microvolt = <1550000>;
 234                         };
 235
 236                         vgen2_reg: vgen2 {
 237                                 regulator-min-microvolt = <800000>;
 238                                 regulator-max-microvolt = <1550000>;
 239                         };
 240
 241                         vgen3_reg: vgen3 {
 242                                 regulator-min-microvolt = <1800000>;
 243                                 regulator-max-microvolt = <3300000>;
 244                         };
 245
 246                         vgen4_reg: vgen4 {
 247                                 regulator-min-microvolt = <1800000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                                 regulator-always-on;
 250                         };
 251
 252                         vgen5_reg: vgen5 {
 253                                 regulator-min-microvolt = <1800000>;
 254                                 regulator-max-microvolt = <3300000>;
 255                                 regulator-always-on;
 256                         };
 257
 258                         vgen6_reg: vgen6 {
 259                                 regulator-min-microvolt = <1800000>;
 260                                 regulator-max-microvolt = <3300000>;
 261                                 regulator-always-on;
 262                         };
 263                 };
 264         };
 265 };
 266
 267 &iomuxc {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_hog>;
 270
 271         imx6qdl-sabreauto {
 272                 pinctrl_hog: hoggrp {
 273                         fsl,pins = <
 274                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 275                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 276                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 277                         >;
 278                 };
 279
 280                 pinctrl_ecspi1: ecspi1grp {
 281                         fsl,pins = <
 282                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 283                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 284                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 285                         >;
 286                 };
 287
 288                 pinctrl_ecspi1_cs: ecspi1cs {
 289                         fsl,pins = <
 290                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 291                         >;
 292                 };
 293
 294                 pinctrl_enet: enetgrp {
 295                         fsl,pins = <
 296                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 297                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 298                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 299                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 300                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 301                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 302                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 303                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 304                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 305                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 306                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 307                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 308                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 309                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 310                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 311                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 312                         >;
 313                 };
 314
 315                 pinctrl_gpio_leds: gpioledsgrp {
 316                         fsl,pins = <
 317                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 318                         >;
 319                 };
 320
 321                 pinctrl_gpmi_nand: gpminandgrp {
 322                         fsl,pins = <
 323                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 324                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 325                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 326                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 327                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 328                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 329                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 330                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 331                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 332                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 333                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 334                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 335                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 336                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 337                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 338                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 339                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 340                         >;
 341                 };
 342
 343                 pinctrl_i2c2: i2c2grp {
 344                         fsl,pins = <
 345                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 346                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 347                         >;
 348                 };
 349
 350                 pinctrl_pwm3: pwm1grp {
 351                         fsl,pins = <
 352                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 353                         >;
 354                 };
 355
 356                 pinctrl_spdif: spdifgrp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 359                         >;
 360                 };
 361
 362                 pinctrl_uart4: uart4grp {
 363                         fsl,pins = <
 364                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 365                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 366                         >;
 367                 };
 368
 369                 pinctrl_usdhc3: usdhc3grp {
 370                         fsl,pins = <
 371                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 372                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 373                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 374                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 375                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 376                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 377                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 378                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 379                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 380                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 381                         >;
 382                 };
 383
 384                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 385                         fsl,pins = <
 386                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 387                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 388                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 389                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 390                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 391                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 392                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 393                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 394                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 395                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 396                         >;
 397                 };
 398
 399                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 402                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 403                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 404                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 405                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 406                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 407                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 408                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 409                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 410                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 411                         >;
 412                 };
 413
 414                 pinctrl_weim_cs0: weimcs0grp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 417                         >;
 418                 };
 419
 420                 pinctrl_weim_nor: weimnorgrp {
 421                         fsl,pins = <
 422                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 423                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 424                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 425                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 426                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 427                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 428                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 429                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 430                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 431                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 432                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 433                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 434                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 435                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 436                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 437                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 438                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 439                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 440                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 441                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 442                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 443                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 444                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 445                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 446                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 447                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 448                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 449                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 450                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 451                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 452                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 453                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 454                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 455                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 456                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 457                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 458                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 459                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 460                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 461                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 462                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 463                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 464                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 465                         >;
 466                 };
 467         };
 468 };
 469
 470 &flexcan1 {
 471         pinctrl-names = "default";
 472         pinctrl-0 = <&pinctrl_flexcan1_1>;
 473         pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
 474         trx-en-gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
 475         trx-stby-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
 476         status = "disabled"; /* pin conflict with fec */
 477 };
 478
 479 &flexcan2 {
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_flexcan2_1>;
 482         trx-en-gpio = <&max7310_c 6 GPIO_ACTIVE_HIGH>;
 483         trx-stby-gpio = <&max7310_c 5 GPIO_ACTIVE_HIGH>;
 484         status = "okay";
 485 };
 486
 487 &ldb {
 488         status = "okay";
 489
 490         lvds-channel@0 {
 491                 fsl,data-mapping = "spwg";
 492                 fsl,data-width = <18>;
 493                 status = "okay";
 494
 495                 display-timings {
 496                         native-mode = <&timing0>;
 497                         timing0: hsd100pxn1 {
 498                                 clock-frequency = <65000000>;
 499                                 hactive = <1024>;
 500                                 vactive = <768>;
 501                                 hback-porch = <220>;
 502                                 hfront-porch = <40>;
 503                                 vback-porch = <21>;
 504                                 vfront-porch = <7>;
 505                                 hsync-len = <60>;
 506                                 vsync-len = <10>;
 507                         };
 508                 };
 509         };
 510 };
 511
 512 &pwm3 {
 513         pinctrl-names = "default";
 514         pinctrl-0 = <&pinctrl_pwm3>;
 515         status = "okay";
 516 };
 517
 518 &spdif {
 519         pinctrl-names = "default";
 520         pinctrl-0 = <&pinctrl_spdif>;
 521         status = "okay";
 522 };
 523
 524 &gpmi {
 525         pinctrl-names = "default";
 526         pinctrl-0 = <&pinctrl_gpmi_nand_1>;
 527         status = "okay";
 528 };
 529
 530 &uart4 {
 531         pinctrl-names = "default";
 532         pinctrl-0 = <&pinctrl_uart4>;
 533         status = "okay";
 534 };
 535
 536 &usdhc3 {
 537         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 538         pinctrl-0 = <&pinctrl_usdhc3>;
 539         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 540         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 541         cd-gpios = <&gpio6 15 0>;
 542         wp-gpios = <&gpio1 13 0>;
 543         status = "okay";
 544 };
 545
 546 &weim {
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 549         #address-cells = <2>;
 550         #size-cells = <1>;
 551         ranges = <0 0 0x08000000 0x08000000>;
 552         status = "disabled"; /* pin conflict with SPI NOR */
 553
 554         nor@0,0 {
 555                 compatible = "cfi-flash";
 556                 reg = <0 0 0x02000000>;
 557                 #address-cells = <1>;
 558                 #size-cells = <1>;
 559                 bank-width = <2>;
 560                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 561                                 0x0000c000 0x1404a38e 0x00000000>;
 562         };
 563 };
 564
 565 &ldb {
 566         ipu_id = <1>;
 567         disp_id = <1>;
 568         ext_ref = <1>;
 569         mode = "sep0";
 570         sec_ipu_id = <1>;
 571         sec_disp_id = <0>;
 572         status = "okay";
 573 };
 574
 575 &pwm3 {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&pinctrl_pwm3_1>;
 578         status = "okay";
 579 };