arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/input/input.h>
  16
  17 / {
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x10000000 0x40000000>;
  24         };
  25
  26         regulators {
  27                 compatible = "simple-bus";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 reg_usb_otg_vbus: regulator@0 {
  32                         compatible = "regulator-fixed";
  33                         reg = <0>;
  34                         regulator-name = "usb_otg_vbus";
  35                         regulator-min-microvolt = <5000000>;
  36                         regulator-max-microvolt = <5000000>;
  37                         gpio = <&gpio3 22 0>;
  38                         enable-active-high;
  39                         vin-supply = <&swbst_reg>;
  40                 };
  41
  42                 reg_usb_h1_vbus: regulator@1 {
  43                         compatible = "regulator-fixed";
  44                         reg = <1>;
  45                         regulator-name = "usb_h1_vbus";
  46                         regulator-min-microvolt = <5000000>;
  47                         regulator-max-microvolt = <5000000>;
  48                         gpio = <&gpio1 29 0>;
  49                         enable-active-high;
  50                         vin-supply = <&swbst_reg>;
  51                 };
  52
  53                 reg_audio: regulator@2 {
  54                         compatible = "regulator-fixed";
  55                         reg = <2>;
  56                         regulator-name = "wm8962-supply";
  57                         gpio = <&gpio4 10 0>;
  58                         enable-active-high;
  59                 };
  60
  61                 reg_pcie: regulator@3 {
  62                         compatible = "regulator-fixed";
  63                         reg = <3>;
  64                         pinctrl-names = "default";
  65                         pinctrl-0 = <&pinctrl_pcie_reg>;
  66                         regulator-name = "MPCIE_3V3";
  67                         regulator-min-microvolt = <3300000>;
  68                         regulator-max-microvolt = <3300000>;
  69                         gpio = <&gpio3 19 0>;
  70                         regulator-always-on;
  71                         enable-active-high;
  72                 };
  73         };
  74
  75         gpio-keys {
  76                 compatible = "gpio-keys";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_gpio_keys>;
  79
  80                 power {
  81                         label = "Power Button";
  82                         gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  83                         wakeup-source;
  84                         linux,code = <KEY_POWER>;
  85                 };
  86
  87                 volume-up {
  88                         label = "Volume Up";
  89                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  90                         wakeup-source;
  91                         linux,code = <KEY_VOLUMEUP>;
  92                 };
  93
  94                 volume-down {
  95                         label = "Volume Down";
  96                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  97                         wakeup-source;
  98                         linux,code = <KEY_VOLUMEDOWN>;
  99                 };
 100         };
 101
 102         sound {
 103                 compatible = "fsl,imx6q-sabresd-wm8962",
 104                            "fsl,imx-audio-wm8962";
 105                 model = "wm8962-audio";
 106                 ssi-controller = <&ssi2>;
 107                 audio-codec = <&codec>;
 108                 audio-routing =
 109                         "Headphone Jack", "HPOUTL",
 110                         "Headphone Jack", "HPOUTR",
 111                         "Ext Spk", "SPKOUTL",
 112                         "Ext Spk", "SPKOUTR",
 113                         "AMIC", "MICBIAS",
 114                         "IN3R", "AMIC";
 115                 mux-int-port = <2>;
 116                 mux-ext-port = <3>;
 117         };
 118
 119         backlight_lvds: backlight-lvds {
 120                 compatible = "pwm-backlight";
 121                 pwms = <&pwm1 0 5000000>;
 122                 brightness-levels = <0 4 8 16 32 64 128 255>;
 123                 default-brightness-level = <7>;
 124                 status = "okay";
 125         };
 126
 127         leds {
 128                 compatible = "gpio-leds";
 129                 pinctrl-names = "default";
 130                 pinctrl-0 = <&pinctrl_gpio_leds>;
 131
 132                 red {
 133                         gpios = <&gpio1 2 0>;
 134                         default-state = "on";
 135                 };
 136         };
 137
 138         panel {
 139                 compatible = "hannstar,hsd100pxn1";
 140                 backlight = <&backlight_lvds>;
 141
 142                 port {
 143                         panel_in: endpoint {
 144                                 remote-endpoint = <&lvds0_out>;
 145                         };
 146                 };
 147         };
 148 };
 149
 150 &ipu1_csi0_from_ipu1_csi0_mux {
 151         bus-width = <8>;
 152         data-shift = <12>; /* Lines 19:12 used */
 153         hsync-active = <1>;
 154         vsync-active = <1>;
 155 };
 156
 157 &ipu1_csi0_mux_from_parallel_sensor {
 158         remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
 159 };
 160
 161 &ipu1_csi0 {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 164 };
 165
 166 &mipi_csi {
 167         status = "okay";
 168
 169         port@0 {
 170                 reg = <0>;
 171
 172                 mipi_csi2_in: endpoint {
 173                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 174                         clock-lanes = <0>;
 175                         data-lanes = <1 2>;
 176                 };
 177         };
 178 };
 179
 180 &audmux {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_audmux>;
 183         status = "okay";
 184 };
 185
 186 &clks {
 187         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 188                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 189         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 190                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 191 };
 192
 193 &ecspi1 {
 194         cs-gpios = <&gpio4 9 0>;
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_ecspi1>;
 197         status = "okay";
 198
 199         flash: m25p80@0 {
 200                 #address-cells = <1>;
 201                 #size-cells = <1>;
 202                 compatible = "st,m25p32", "jedec,spi-nor";
 203                 spi-max-frequency = <20000000>;
 204                 reg = <0>;
 205         };
 206 };
 207
 208 &fec {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_enet>;
 211         phy-mode = "rgmii";
 212         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 213         status = "okay";
 214 };
 215
 216 &hdmi {
 217         ddc-i2c-bus = <&i2c2>;
 218         status = "okay";
 219 };
 220
 221 &i2c1 {
 222         clock-frequency = <100000>;
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_i2c1>;
 225         status = "okay";
 226
 227         codec: wm8962@1a {
 228                 compatible = "wlf,wm8962";
 229                 reg = <0x1a>;
 230                 clocks = <&clks IMX6QDL_CLK_CKO>;
 231                 DCVDD-supply = <&reg_audio>;
 232                 DBVDD-supply = <&reg_audio>;
 233                 AVDD-supply = <&reg_audio>;
 234                 CPVDD-supply = <&reg_audio>;
 235                 MICVDD-supply = <&reg_audio>;
 236                 PLLVDD-supply = <&reg_audio>;
 237                 SPKVDD1-supply = <&reg_audio>;
 238                 SPKVDD2-supply = <&reg_audio>;
 239                 gpio-cfg = <
 240                         0x0000 /* 0:Default */
 241                         0x0000 /* 1:Default */
 242                         0x0013 /* 2:FN_DMICCLK */
 243                         0x0000 /* 3:Default */
 244                         0x8014 /* 4:FN_DMICCDAT */
 245                         0x0000 /* 5:Default */
 246                 >;
 247         };
 248
 249         ov5642: camera@3c {
 250                 compatible = "ovti,ov5642";
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&pinctrl_ov5642>;
 253                 clocks = <&clks IMX6QDL_CLK_CKO>;
 254                 clock-names = "xclk";
 255                 reg = <0x3c>;
 256                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 257                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 258                                                 rev B board is VGEN5 */
 259                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 260                 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
 261                 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 262                 status = "disabled";
 263
 264                 port {
 265                         ov5642_to_ipu1_csi0_mux: endpoint {
 266                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 267                                 bus-width = <8>;
 268                                 hsync-active = <1>;
 269                                 vsync-active = <1>;
 270                         };
 271                 };
 272         };
 273 };
 274
 275 &i2c2 {
 276         clock-frequency = <100000>;
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_i2c2>;
 279         status = "okay";
 280
 281         ov5640: camera@3c {
 282                 compatible = "ovti,ov5640";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&pinctrl_ov5640>;
 285                 reg = <0x3c>;
 286                 clocks = <&clks IMX6QDL_CLK_CKO>;
 287                 clock-names = "xclk";
 288                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 289                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 290                                                 rev B board is VGEN5 */
 291                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 292                 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
 293                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 294
 295                 port {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298
 299                         ov5640_to_mipi_csi2: endpoint {
 300                                 remote-endpoint = <&mipi_csi2_in>;
 301                                 clock-lanes = <0>;
 302                                 data-lanes = <1 2>;
 303                         };
 304                 };
 305         };
 306
 307         pmic: pfuze100@08 {
 308                 compatible = "fsl,pfuze100";
 309                 reg = <0x08>;
 310
 311                 regulators {
 312                         sw1a_reg: sw1ab {
 313                                 regulator-min-microvolt = <300000>;
 314                                 regulator-max-microvolt = <1875000>;
 315                                 regulator-boot-on;
 316                                 regulator-always-on;
 317                                 regulator-ramp-delay = <6250>;
 318                         };
 319
 320                         sw1c_reg: sw1c {
 321                                 regulator-min-microvolt = <300000>;
 322                                 regulator-max-microvolt = <1875000>;
 323                                 regulator-boot-on;
 324                                 regulator-always-on;
 325                                 regulator-ramp-delay = <6250>;
 326                         };
 327
 328                         sw2_reg: sw2 {
 329                                 regulator-min-microvolt = <800000>;
 330                                 regulator-max-microvolt = <3300000>;
 331                                 regulator-boot-on;
 332                                 regulator-always-on;
 333                                 regulator-ramp-delay = <6250>;
 334                         };
 335
 336                         sw3a_reg: sw3a {
 337                                 regulator-min-microvolt = <400000>;
 338                                 regulator-max-microvolt = <1975000>;
 339                                 regulator-boot-on;
 340                                 regulator-always-on;
 341                         };
 342
 343                         sw3b_reg: sw3b {
 344                                 regulator-min-microvolt = <400000>;
 345                                 regulator-max-microvolt = <1975000>;
 346                                 regulator-boot-on;
 347                                 regulator-always-on;
 348                         };
 349
 350                         sw4_reg: sw4 {
 351                                 regulator-min-microvolt = <800000>;
 352                                 regulator-max-microvolt = <3300000>;
 353                         };
 354
 355                         swbst_reg: swbst {
 356                                 regulator-min-microvolt = <5000000>;
 357                                 regulator-max-microvolt = <5150000>;
 358                         };
 359
 360                         snvs_reg: vsnvs {
 361                                 regulator-min-microvolt = <1000000>;
 362                                 regulator-max-microvolt = <3000000>;
 363                                 regulator-boot-on;
 364                                 regulator-always-on;
 365                         };
 366
 367                         vref_reg: vrefddr {
 368                                 regulator-boot-on;
 369                                 regulator-always-on;
 370                         };
 371
 372                         vgen1_reg: vgen1 {
 373                                 regulator-min-microvolt = <800000>;
 374                                 regulator-max-microvolt = <1550000>;
 375                         };
 376
 377                         vgen2_reg: vgen2 {
 378                                 regulator-min-microvolt = <800000>;
 379                                 regulator-max-microvolt = <1550000>;
 380                         };
 381
 382                         vgen3_reg: vgen3 {
 383                                 regulator-min-microvolt = <1800000>;
 384                                 regulator-max-microvolt = <3300000>;
 385                         };
 386
 387                         vgen4_reg: vgen4 {
 388                                 regulator-min-microvolt = <1800000>;
 389                                 regulator-max-microvolt = <3300000>;
 390                                 regulator-always-on;
 391                         };
 392
 393                         vgen5_reg: vgen5 {
 394                                 regulator-min-microvolt = <1800000>;
 395                                 regulator-max-microvolt = <3300000>;
 396                                 regulator-always-on;
 397                         };
 398
 399                         vgen6_reg: vgen6 {
 400                                 regulator-min-microvolt = <1800000>;
 401                                 regulator-max-microvolt = <3300000>;
 402                                 regulator-always-on;
 403                         };
 404                 };
 405         };
 406 };
 407
 408 &i2c3 {
 409         clock-frequency = <100000>;
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_i2c3>;
 412         status = "okay";
 413
 414         egalax_ts@04 {
 415                 compatible = "eeti,egalax_ts";
 416                 reg = <0x04>;
 417                 interrupt-parent = <&gpio6>;
 418                 interrupts = <7 2>;
 419                 wakeup-gpios = <&gpio6 7 0>;
 420         };
 421 };
 422
 423 &iomuxc {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_hog>;
 426
 427         imx6qdl-sabresd {
 428                 pinctrl_hog: hoggrp {
 429                         fsl,pins = <
 430                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
 431                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
 432                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
 433                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
 434                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 435                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
 436                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 437                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
 438                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 439                         >;
 440                 };
 441
 442                 pinctrl_audmux: audmuxgrp {
 443                         fsl,pins = <
 444                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 445                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 446                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 447                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 448                         >;
 449                 };
 450
 451                 pinctrl_ecspi1: ecspi1grp {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 454                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 455                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 456                                 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 457                         >;
 458                 };
 459
 460                 pinctrl_enet: enetgrp {
 461                         fsl,pins = <
 462                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 463                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 464                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 465                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 466                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 467                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 468                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 469                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 470                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 471                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 472                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 473                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 474                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 475                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 476                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 477                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 478                         >;
 479                 };
 480
 481                 pinctrl_gpio_keys: gpio_keysgrp {
 482                         fsl,pins = <
 483                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 484                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
 485                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
 486                         >;
 487                 };
 488
 489                 pinctrl_i2c1: i2c1grp {
 490                         fsl,pins = <
 491                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 492                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 493                         >;
 494                 };
 495
 496                 pinctrl_i2c2: i2c2grp {
 497                         fsl,pins = <
 498                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 499                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 500                         >;
 501                 };
 502
 503                 pinctrl_i2c3: i2c3grp {
 504                         fsl,pins = <
 505                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 506                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 507                         >;
 508                 };
 509
 510                 pinctrl_ipu1_csi0: ipu1csi0grp {
 511                         fsl,pins = <
 512                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 513                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 514                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 515                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 516                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 517                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 518                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 519                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 520                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 521                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 522                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 523                         >;
 524                 };
 525
 526                 pinctrl_ov5640: ov5640grp {
 527                         fsl,pins = <
 528                                 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
 529                                 MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
 530                         >;
 531                 };
 532
 533                 pinctrl_ov5642: ov5642grp {
 534                         fsl,pins = <
 535                                 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
 536                                 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
 537                         >;
 538                 };
 539
 540                 pinctrl_pcie: pciegrp {
 541                         fsl,pins = <
 542                                 MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 543                         >;
 544                 };
 545
 546                 pinctrl_pcie_reg: pciereggrp {
 547                         fsl,pins = <
 548                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
 549                         >;
 550                 };
 551
 552                 pinctrl_pwm1: pwm1grp {
 553                         fsl,pins = <
 554                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 555                         >;
 556                 };
 557
 558                 pinctrl_uart1: uart1grp {
 559                         fsl,pins = <
 560                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 561                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 562                         >;
 563                 };
 564
 565                 pinctrl_usbotg: usbotggrp {
 566                         fsl,pins = <
 567                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 568                         >;
 569                 };
 570
 571                 pinctrl_usdhc2: usdhc2grp {
 572                         fsl,pins = <
 573                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 574                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 575                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 576                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 577                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 578                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 579                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 580                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 581                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 582                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 583                         >;
 584                 };
 585
 586                 pinctrl_usdhc3: usdhc3grp {
 587                         fsl,pins = <
 588                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 589                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 590                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 591                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 592                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 593                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 594                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 595                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 596                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 597                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 598                         >;
 599                 };
 600
 601                 pinctrl_usdhc4: usdhc4grp {
 602                         fsl,pins = <
 603                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 604                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 605                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 606                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 607                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 608                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 609                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 610                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 611                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 612                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 613                         >;
 614                 };
 615
 616                 pinctrl_wdog: wdoggrp {
 617                         fsl,pins = <
 618                                 MX6QDL_PAD_GPIO_1__WDOG2_B              0x1b0b0
 619                         >;
 620                 };
 621         };
 622
 623         gpio_leds {
 624                 pinctrl_gpio_leds: gpioledsgrp {
 625                         fsl,pins = <
 626                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 627                         >;
 628                 };
 629         };
 630 };
 631
 632 &ldb {
 633         status = "okay";
 634
 635         lvds-channel@1 {
 636                 fsl,data-mapping = "spwg";
 637                 fsl,data-width = <18>;
 638                 status = "okay";
 639
 640                 port@4 {
 641                         reg = <4>;
 642
 643                         lvds0_out: endpoint {
 644                                 remote-endpoint = <&panel_in>;
 645                         };
 646                 };
 647         };
 648 };
 649
 650 &pcie {
 651         pinctrl-names = "default";
 652         pinctrl-0 = <&pinctrl_pcie>;
 653         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 654         status = "okay";
 655 };
 656
 657 &pwm1 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&pinctrl_pwm1>;
 660         status = "okay";
 661 };
 662
 663 &reg_arm {
 664        vin-supply = <&sw1a_reg>;
 665 };
 666
 667 &reg_pu {
 668        vin-supply = <&sw1c_reg>;
 669 };
 670
 671 &reg_soc {
 672        vin-supply = <&sw1c_reg>;
 673 };
 674
 675 &snvs_poweroff {
 676         status = "okay";
 677 };
 678
 679 &ssi2 {
 680         status = "okay";
 681 };
 682
 683 &uart1 {
 684         pinctrl-names = "default";
 685         pinctrl-0 = <&pinctrl_uart1>;
 686         status = "okay";
 687 };
 688
 689 &usbh1 {
 690         vbus-supply = <&reg_usb_h1_vbus>;
 691         status = "okay";
 692 };
 693
 694 &usbotg {
 695         vbus-supply = <&reg_usb_otg_vbus>;
 696         pinctrl-names = "default";
 697         pinctrl-0 = <&pinctrl_usbotg>;
 698         disable-over-current;
 699         status = "okay";
 700 };
 701
 702 &usdhc2 {
 703         pinctrl-names = "default";
 704         pinctrl-0 = <&pinctrl_usdhc2>;
 705         bus-width = <8>;
 706         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 707         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 708         status = "okay";
 709 };
 710
 711 &usdhc3 {
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&pinctrl_usdhc3>;
 714         bus-width = <8>;
 715         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 716         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 717         status = "okay";
 718 };
 719
 720 &usdhc4 {
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&pinctrl_usdhc4>;
 723         bus-width = <8>;
 724         non-removable;
 725         no-1-8-v;
 726         status = "okay";
 727 };
 728
 729 &wdog1 {
 730         status = "disabled";
 731 };
 732
 733 &wdog2 {
 734         pinctrl-names = "default";
 735         pinctrl-0 = <&pinctrl_wdog>;
 736         fsl,ext-reset-output;
 737         status = "okay";
 738 };