arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/pwm/pwm.h>
  15
  16 / {
  17         aliases {
  18                 can0 = &can2;
  19                 can1 = &can1;
  20                 ethernet0 = &fec;
  21                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  22                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  23                 pwm0 = &pwm1;
  24                 pwm1 = &pwm2;
  25                 reg_can_xcvr = &reg_can_xcvr;
  26                 stk5led = &user_led;
  27                 usbotg = &usbotg;
  28                 sdhc0 = &usdhc1;
  29                 sdhc1 = &usdhc2;
  30         };
  31
  32         memory {
  33                 reg = <0 0>; /* will be filled by U-Boot */
  34         };
  35
  36         clocks {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 mclk: clock@0 {
  40                         compatible = "fixed-clock";
  41                         reg = <0>;
  42                         #clock-cells = <0>;
  43                         clock-frequency = <27000000>;
  44                 };
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49
  50                 power {
  51                         label = "Power Button";
  52                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_POWER>;
  54                         gpio-key,wakeup;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60
  61                 user_led: user {
  62                         label = "Heartbeat";
  63                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         regulators {
  69                 compatible = "simple-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 reg_3v3_etn: regulator@0 {
  74                         compatible = "regulator-fixed";
  75                         reg = <0>;
  76                         regulator-name = "3V3_ETN";
  77                         regulator-min-microvolt = <3300000>;
  78                         regulator-max-microvolt = <3300000>;
  79                         pinctrl-names = "default";
  80                         pinctrl-0 = <&pinctrl_etnphy_power>;
  81                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  82                         enable-active-high;
  83                 };
  84
  85                 reg_2v5: regulator@1 {
  86                         compatible = "regulator-fixed";
  87                         reg = <1>;
  88                         regulator-name = "2V5";
  89                         regulator-min-microvolt = <2500000>;
  90                         regulator-max-microvolt = <2500000>;
  91                         regulator-always-on;
  92                 };
  93
  94                 reg_3v3: regulator@2 {
  95                         compatible = "regulator-fixed";
  96                         reg = <2>;
  97                         regulator-name = "3V3";
  98                         regulator-min-microvolt = <3300000>;
  99                         regulator-max-microvolt = <3300000>;
 100                         regulator-always-on;
 101                 };
 102
 103                 reg_can_xcvr: regulator@3 {
 104                         compatible = "regulator-fixed";
 105                         reg = <3>;
 106                         regulator-name = "CAN XCVR";
 107                         regulator-min-microvolt = <3300000>;
 108                         regulator-max-microvolt = <3300000>;
 109                         pinctrl-names = "default";
 110                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 111                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 112                         enable-active-low;
 113                 };
 114
 115                 reg_lcd0_pwr: regulator@4 {
 116                         compatible = "regulator-fixed";
 117                         reg = <4>;
 118                         regulator-name = "LCD0 POWER";
 119                         regulator-min-microvolt = <3300000>;
 120                         regulator-max-microvolt = <3300000>;
 121                         pinctrl-names = "default";
 122                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
 123                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 124                         enable-active-high;
 125                         regulator-boot-on;
 126                         regulator-always-on;
 127                         status = "disabled";
 128                 };
 129
 130                 reg_lcd1_pwr: regulator@5 {
 131                         compatible = "regulator-fixed";
 132                         reg = <5>;
 133                         regulator-name = "LCD1 POWER";
 134                         regulator-min-microvolt = <3300000>;
 135                         regulator-max-microvolt = <3300000>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
 138                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 139                         enable-active-high;
 140                         regulator-boot-on;
 141                         regulator-always-on;
 142                         status = "disabled";
 143                 };
 144
 145                 reg_usbh1_vbus: regulator@6 {
 146                         compatible = "regulator-fixed";
 147                         reg = <6>;
 148                         regulator-name = "usbh1_vbus";
 149                         regulator-min-microvolt = <5000000>;
 150                         regulator-max-microvolt = <5000000>;
 151                         pinctrl-names = "default";
 152                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 153                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 154                         enable-active-high;
 155                 };
 156
 157                 reg_usbotg_vbus: regulator@7 {
 158                         compatible = "regulator-fixed";
 159                         reg = <7>;
 160                         regulator-name = "usbotg_vbus";
 161                         regulator-min-microvolt = <5000000>;
 162                         regulator-max-microvolt = <5000000>;
 163                         pinctrl-names = "default";
 164                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 165                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 166                         enable-active-high;
 167                 };
 168         };
 169
 170         sound {
 171                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 172                              "fsl,imx-audio-sgtl5000";
 173                 model = "sgtl5000-audio";
 174                 ssi-controller = <&ssi1>;
 175                 audio-codec = <&sgtl5000>;
 176                 audio-routing =
 177                         "MIC_IN", "Mic Jack",
 178                         "Mic Jack", "Mic Bias",
 179                         "Headphone Jack", "HP_OUT";
 180                 mux-int-port = <1>;
 181                 mux-ext-port = <5>;
 182         };
 183
 184         v4l2_out {
 185                 compatible = "fsl,mxc_v4l2_output";
 186                 status = "okay";
 187         };
 188 };
 189
 190 &audmux {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_audmux>;
 193         status = "okay";
 194 };
 195
 196 &can1 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_flexcan1>;
 199         xceiver-supply = <&reg_can_xcvr>;
 200         status = "okay";
 201 };
 202
 203 &can2 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_flexcan2>;
 206         xceiver-supply = <&reg_can_xcvr>;
 207         status = "okay";
 208 };
 209
 210 &ecspi1 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_ecspi1>;
 213         fsl,spi-num-chipselects = <2>;
 214         cs-gpios = <
 215                 &gpio2 30 GPIO_ACTIVE_HIGH
 216                 &gpio3 19 GPIO_ACTIVE_HIGH
 217         >;
 218         status = "okay";
 219
 220         spidev0: spi@0 {
 221                 compatible = "spidev";
 222                 reg = <0>;
 223                 spi-max-frequency = <54000000>;
 224         };
 225
 226         spidev1: spi@1 {
 227                 compatible = "spidev";
 228                 reg = <1>;
 229                 spi-max-frequency = <54000000>;
 230         };
 231 };
 232
 233 &fec {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_enet>;
 236         phy-mode = "rmii";
 237         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 238         phy-supply = <&reg_3v3_etn>;
 239         status = "okay";
 240 };
 241
 242 &gpmi {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_gpmi_nand>;
 245         nand-on-flash-bbt;
 246         fsl,no-blockmark-swap;
 247         status = "okay";
 248 };
 249
 250 &i2c1 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_i2c1>;
 253         clock-frequency = <400000>;
 254         status = "okay";
 255
 256         ds1339: rtc@68 {
 257                 compatible = "dallas,ds1339";
 258                 reg = <0x68>;
 259         };
 260 };
 261
 262 &i2c3 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_i2c3>;
 265         clock-frequency = <400000>;
 266         status = "okay";
 267
 268         sgtl5000: sgtl5000@0a {
 269                 compatible = "fsl,sgtl5000";
 270                 reg = <0x0a>;
 271                 VDDA-supply = <&reg_2v5>;
 272                 VDDIO-supply = <&reg_3v3>;
 273                 clocks = <&mclk>;
 274         };
 275
 276         polytouch: edt-ft5x06@38 {
 277                 compatible = "edt,edt-ft5x06";
 278                 reg = <0x38>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 281                 interrupt-parent = <&gpio6>;
 282                 interrupts = <15 0>;
 283                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 284                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 285                 linux,wakeup;
 286         };
 287
 288         touchscreen: tsc2007@48 {
 289                 compatible = "ti,tsc2007";
 290                 reg = <0x48>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&pinctrl_tsc2007>;
 293                 interrupt-parent = <&gpio3>;
 294                 interrupts = <26 0>;
 295                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 296                 ti,x-plate-ohms = <660>;
 297                 linux,wakeup;
 298         };
 299 };
 300
 301 &iomuxc {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_hog>;
 304
 305         imx6qdl-tx6 {
 306                 pinctrl_hog: hoggrp {
 307                         fsl,pins = <
 308                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 309                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 310                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 311                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 312                         >;
 313                 };
 314
 315                 pinctrl_audmux: audmuxgrp {
 316                         fsl,pins = <
 317                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 318                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 319                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 320                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 321                         >;
 322                 };
 323
 324                 pinctrl_disp0_1: disp0grp-1 {
 325                         fsl,pins = <
 326                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 327                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 328                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 329                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 330                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 331                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 332                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 333                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 334                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 335                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 336                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 337                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 338                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 339                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 340                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 341                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 342                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 343                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 344                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 345                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 346                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 347                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 348                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 349                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 350                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 351                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 352                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 353                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 354                         >;
 355                 };
 356
 357                 pinctrl_disp0_2: disp0grp-2 {
 358                         fsl,pins = <
 359                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 360                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 361                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 362                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 363                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 364                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 365                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 366                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 367                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 368                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 369                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 370                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 371                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 372                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 373                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 374                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 375                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 376                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 377                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 378                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 379                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 380                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 381                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 382                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 383                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 384                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 385                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 386                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 387                         >;
 388                 };
 389
 390                 pinctrl_ecspi1: ecspi1grp {
 391                         fsl,pins = <
 392                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 393                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 394                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 395                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 396                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 397                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 398                         >;
 399                 };
 400
 401                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 402                         fsl,pins = <
 403                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 404                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 405                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 406                         >;
 407                 };
 408
 409                 pinctrl_enet: enetgrp {
 410                         fsl,pins = <
 411                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 412                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 413                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 414                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 415                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 416                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 417                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 418                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 419                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 420                         >;
 421                 };
 422
 423                 pinctrl_etnphy_power: etnphy-pwrgrp {
 424                         fsl,pins = <
 425                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 426                         >;
 427                 };
 428
 429                 pinctrl_flexcan1: flexcan1grp {
 430                         fsl,pins = <
 431                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 432                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 433                         >;
 434                 };
 435
 436                 pinctrl_flexcan2: flexcan2grp {
 437                         fsl,pins = <
 438                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 439                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 440                         >;
 441                 };
 442
 443                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 444                         fsl,pins = <
 445                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 446                         >;
 447                 };
 448
 449                 pinctrl_gpmi_nand: gpminandgrp {
 450                         fsl,pins = <
 451                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 452                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 453                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 454                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 455                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 456                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 457                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 458                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 459                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 460                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 461                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 462                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 463                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 464                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 465                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 466                         >;
 467                 };
 468
 469                 pinctrl_i2c1: i2c1grp {
 470                         fsl,pins = <
 471                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 472                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 473                         >;
 474                 };
 475
 476                 pinctrl_i2c3: i2c3grp {
 477                         fsl,pins = <
 478                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 479                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 480                         >;
 481                 };
 482
 483                 pinctrl_kpp: kppgrp {
 484                         fsl,pins = <
 485                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 486                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 487                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 488                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 489                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 490                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 491                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 492                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 493                         >;
 494                 };
 495
 496                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
 497                         fsl,pins = <
 498                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 499                         >;
 500                 };
 501
 502                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
 503                         fsl,pins = <
 504                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 505                         >;
 506                 };
 507
 508                 pinctrl_pwm1: pwm1grp {
 509                         fsl,pins = <
 510                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 511                         >;
 512                 };
 513
 514                 pinctrl_pwm2: pwm2grp {
 515                         fsl,pins = <
 516                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 517                         >;
 518                 };
 519
 520                 pinctrl_tsc2007: tsc2007grp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 523                         >;
 524                 };
 525
 526                 pinctrl_uart1: uart1grp {
 527                         fsl,pins = <
 528                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 529                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 530                         >;
 531                 };
 532
 533                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 534                         fsl,pins = <
 535                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 536                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 537                         >;
 538                 };
 539
 540                 pinctrl_uart2: uart2grp {
 541                         fsl,pins = <
 542                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 543                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 544                         >;
 545                 };
 546
 547                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 548                         fsl,pins = <
 549                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 550                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 551                         >;
 552                 };
 553
 554                 pinctrl_uart3: uart3grp {
 555                         fsl,pins = <
 556                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 557                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 558                         >;
 559                 };
 560
 561                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 562                         fsl,pins = <
 563                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 564                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 565                         >;
 566                 };
 567
 568                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 569                         fsl,pins = <
 570                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 571                         >;
 572                 };
 573
 574                 pinctrl_usbotg: usbotggrp {
 575                         fsl,pins = <
 576                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 577                         >;
 578                 };
 579
 580                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 583                         >;
 584                 };
 585
 586                 pinctrl_usdhc1: usdhc1grp {
 587                         fsl,pins = <
 588                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 589                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 590                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 591                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 592                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 593                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 594                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 595                         >;
 596                 };
 597
 598                 pinctrl_usdhc2: usdhc2grp {
 599                         fsl,pins = <
 600                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 601                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 602                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 603                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 604                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 605                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 606                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 607                         >;
 608                 };
 609         };
 610 };
 611
 612 &kpp {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_kpp>;
 615         /* sample keymap */
 616         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 617         linux,keymap = <
 618                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 619                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 620                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 621                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 622                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 623                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 624                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 625                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 626                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 627                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 628                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 629         >;
 630 };
 631
 632 &pwm1 {
 633         pinctrl-names = "default";
 634         pinctrl-0 = <&pinctrl_pwm1>;
 635         #pwm-cells = <3>;
 636         status = "disabled";
 637 };
 638
 639 &pwm2 {
 640         pinctrl-names = "default";
 641         pinctrl-0 = <&pinctrl_pwm2>;
 642         #pwm-cells = <3>;
 643         status = "okay";
 644 };
 645
 646 &ssi1 {
 647         fsl,mode = "i2s-slave";
 648         status = "okay";
 649 };
 650
 651 &uart1 {
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&pinctrl_uart1>;
 654         status = "okay";
 655 };
 656
 657 &uart2 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 660         status = "okay";
 661 };
 662
 663 &uart3 {
 664         pinctrl-names = "default";
 665         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 666         status = "okay";
 667 };
 668
 669 &usbh1 {
 670         vbus-supply = <&reg_usbh1_vbus>;
 671         dr_mode = "host";
 672         disable-over-current;
 673         status = "okay";
 674 };
 675
 676 &usbotg {
 677         vbus-supply = <&reg_usbotg_vbus>;
 678         pinctrl-names = "default";
 679         pinctrl-0 = <&pinctrl_usbotg>;
 680         dr_mode = "peripheral";
 681         disable-over-current;
 682         status = "okay";
 683 };
 684
 685 &usdhc1 {
 686         pinctrl-names = "default";
 687         pinctrl-0 = <&pinctrl_usdhc1>;
 688         bus-width = <4>;
 689         no-1-8-v;
 690         cd-gpios = <&gpio7 2 0>;
 691         fsl,wp-controller;
 692         status = "okay";
 693 };
 694
 695 &usdhc2 {
 696         pinctrl-names = "default";
 697         pinctrl-0 = <&pinctrl_usdhc2>;
 698         bus-width = <4>;
 699         no-1-8-v;
 700         cd-gpios = <&gpio7 3 0>;
 701         fsl,wp-controller;
 702         status = "okay";
 703 };
 704
 705 &vpu {
 706         pu-supply = <&reg_3v3>;
 707 };