arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46 #include <dt-bindings/sound/fsl-imx-audmux.h>
  47
  48 / {
  49         aliases {
  50                 can0 = &can2;
  51                 can1 = &can1;
  52                 ethernet0 = &fec;
  53                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  54                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  55                 pwm0 = &pwm1;
  56                 pwm1 = &pwm2;
  57                 reg_can_xcvr = &reg_can_xcvr;
  58                 stk5led = &user_led;
  59                 usbotg = &usbotg;
  60                 sdhc0 = &usdhc1;
  61                 sdhc1 = &usdhc2;
  62         };
  63
  64         memory {
  65                 reg = <0 0>; /* will be filled by U-Boot */
  66         };
  67
  68         clocks {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 mclk: clock@0 {
  73                         compatible = "fixed-clock";
  74                         reg = <0>;
  75                         #clock-cells = <0>;
  76                         clock-frequency = <26000000>;
  77                 };
  78         };
  79
  80         gpio-keys {
  81                 compatible = "gpio-keys";
  82
  83                 power {
  84                         label = "Power Button";
  85                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  86                         linux,code = <KEY_POWER>;
  87                         wakeup-source;
  88                 };
  89         };
  90
  91         leds {
  92                 compatible = "gpio-leds";
  93
  94                 user_led: user {
  95                         label = "Heartbeat";
  96                         pinctrl-names = "default";
  97                         pinctrl-0 = <&pinctrl_user_led>;
  98                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  99                         linux,default-trigger = "heartbeat";
 100                 };
 101         };
 102
 103         reg_3v3_etn: regulator-3v3-etn {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "3V3_ETN";
 106                 regulator-min-microvolt = <3300000>;
 107                 regulator-max-microvolt = <3300000>;
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_etnphy_power>;
 110                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 111                 enable-active-high;
 112         };
 113
 114         reg_2v5: regulator-2v5 {
 115                 compatible = "regulator-fixed";
 116                 regulator-name = "2V5";
 117                 regulator-min-microvolt = <2500000>;
 118                 regulator-max-microvolt = <2500000>;
 119                 regulator-always-on;
 120         };
 121
 122         reg_3v3: regulator-3v3 {
 123                 compatible = "regulator-fixed";
 124                 regulator-name = "3V3";
 125                 regulator-min-microvolt = <3300000>;
 126                 regulator-max-microvolt = <3300000>;
 127                 regulator-always-on;
 128         };
 129
 130         reg_can_xcvr: regulator-can-xcvr {
 131                 compatible = "regulator-fixed";
 132                 regulator-name = "CAN XCVR";
 133                 regulator-min-microvolt = <3300000>;
 134                 regulator-max-microvolt = <3300000>;
 135                 pinctrl-names = "default";
 136                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 137                 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
 138         };
 139
 140         reg_lcd0_pwr: regulator-lcd0-pwr {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "LCD0 POWER";
 143                 regulator-min-microvolt = <3300000>;
 144                 regulator-max-microvolt = <3300000>;
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&pinctrl_lcd0_pwr>;
 147                 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 148                 enable-active-high;
 149                 status = "disabled";
 150         };
 151
 152         reg_lcd1_pwr: regulator-lcd1-pwr {
 153                 compatible = "regulator-fixed";
 154                 regulator-name = "LCD1 POWER";
 155                 regulator-min-microvolt = <3300000>;
 156                 regulator-max-microvolt = <3300000>;
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pinctrl_lcd1_pwr>;
 159                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 160                 enable-active-high;
 161                 status = "disabled";
 162         };
 163
 164         reg_usbh1_vbus: regulator-usbh1-vbus {
 165                 compatible = "regulator-fixed";
 166                 regulator-name = "usbh1_vbus";
 167                 regulator-min-microvolt = <5000000>;
 168                 regulator-max-microvolt = <5000000>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
 171                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 172                 enable-active-high;
 173         };
 174
 175         reg_usbotg_vbus: regulator-usbotg-vbus {
 176                 compatible = "regulator-fixed";
 177                 regulator-name = "usbotg_vbus";
 178                 regulator-min-microvolt = <5000000>;
 179                 regulator-max-microvolt = <5000000>;
 180                 pinctrl-names = "default";
 181                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
 182                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 183                 enable-active-high;
 184         };
 185
 186         sound {
 187                 compatible = "karo,imx6qdl-tx6-sgtl5000",
 188                              "simple-audio-card";
 189                 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&pinctrl_audmux>;
 192                 simple-audio-card,format = "i2s";
 193                 simple-audio-card,bitclock-master = <&codec_dai>;
 194                 simple-audio-card,frame-master = <&codec_dai>;
 195                 simple-audio-card,widgets =
 196                         "Microphone", "Mic Jack",
 197                         "Line", "Line In",
 198                         "Line", "Line Out",
 199                         "Headphone", "Headphone Jack";
 200                 simple-audio-card,routing =
 201                         "MIC_IN", "Mic Jack",
 202                         "Mic Jack", "Mic Bias",
 203                         "Headphone Jack", "HP_OUT";
 204
 205                 cpu_dai: simple-audio-card,cpu {
 206                         sound-dai = <&ssi1>;
 207                 };
 208
 209                 codec_dai: simple-audio-card,codec {
 210                         sound-dai = <&sgtl5000>;
 211                 };
 212         };
 213 };
 214
 215 &audmux {
 216         status = "okay";
 217
 218         ssi1 {
 219                 fsl,audmux-port = <0>;
 220                 fsl,port-config = <
 221                         (IMX_AUDMUX_V2_PTCR_SYN |
 222                         IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 223                         IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 224                         IMX_AUDMUX_V2_PTCR_TFSDIR |
 225                         IMX_AUDMUX_V2_PTCR_TCLKDIR)
 226                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 227                 >;
 228         };
 229
 230         pins5 {
 231                 fsl,audmux-port = <4>;
 232                 fsl,port-config = <
 233                         IMX_AUDMUX_V2_PTCR_SYN
 234                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 235                 >;
 236         };
 237 };
 238
 239 &can1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_flexcan1>;
 242         xceiver-supply = <&reg_can_xcvr>;
 243         status = "okay";
 244 };
 245
 246 &can2 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_flexcan2>;
 249         xceiver-supply = <&reg_can_xcvr>;
 250         status = "okay";
 251 };
 252
 253 &ecspi1 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_ecspi1>;
 256         cs-gpios = <
 257                 &gpio2 30 GPIO_ACTIVE_HIGH
 258                 &gpio3 19 GPIO_ACTIVE_HIGH
 259         >;
 260         status = "disabled";
 261
 262         spidev0: spi@0 {
 263                 compatible = "spidev";
 264                 reg = <0>;
 265                 spi-max-frequency = <54000000>;
 266         };
 267
 268         spidev1: spi@1 {
 269                 compatible = "spidev";
 270                 reg = <1>;
 271                 spi-max-frequency = <54000000>;
 272         };
 273 };
 274
 275 &fec {
 276         pinctrl-names = "default", "sleep";
 277         pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
 278         pinctrl-1 = <&pinctrl_enet_sleep &pinctrl_enet_mdio_sleep
 279                      &pinctrl_etnphy_rst_sleep>;
 280         clocks = <&clks IMX6QDL_CLK_ENET>,
 281                  <&clks IMX6QDL_CLK_ENET>,
 282                  <&clks IMX6QDL_CLK_ENET_REF>,
 283                  <&clks IMX6QDL_CLK_ENET_REF>;
 284         clock-names = "ipg", "ahb", "ptp", "enet_out";
 285         phy-mode = "rmii";
 286         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 287         phy-reset-post-delay = <10>;
 288         phy-handle = <&etnphy>;
 289         phy-supply = <&reg_3v3_etn>;
 290         status = "okay";
 291
 292         mdio {
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295
 296                 etnphy: ethernet-phy@0 {
 297                         compatible = "ethernet-phy-ieee802.3-c22";
 298                         reg = <0>;
 299                         pinctrl-names = "default";
 300                         pinctrl-0 = <&pinctrl_etnphy_int>;
 301                         interrupt-parent = <&gpio7>;
 302                         interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
 303                 };
 304         };
 305 };
 306
 307 &gpmi {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_gpmi_nand>;
 310         nand-on-flash-bbt;
 311         fsl,no-blockmark-swap;
 312         status = "okay";
 313 };
 314
 315 &i2c1 {
 316         pinctrl-names = "default", "gpio";
 317         pinctrl-0 = <&pinctrl_i2c1>;
 318         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 319         scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
 320         sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 321         clock-frequency = <400000>;
 322         status = "okay";
 323
 324         ds1339: rtc@68 {
 325                 compatible = "dallas,ds1339";
 326                 reg = <0x68>;
 327                 trickle-resistor-ohms = <250>;
 328                 trickle-diode-disable;
 329         };
 330 };
 331
 332 &i2c3 {
 333         pinctrl-names = "default", "gpio";
 334         pinctrl-0 = <&pinctrl_i2c3>;
 335         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 336         scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 337         sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 338         clock-frequency = <400000>;
 339         status = "okay";
 340
 341         sgtl5000: sgtl5000@0a {
 342                 compatible = "fsl,sgtl5000";
 343                 #sound-dai-cells = <0>;
 344                 reg = <0x0a>;
 345                 VDDA-supply = <&reg_2v5>;
 346                 VDDIO-supply = <&reg_3v3>;
 347                 clocks = <&mclk>;
 348         };
 349
 350         polytouch: edt-ft5x06@38 {
 351                 compatible = "edt,edt-ft5x06";
 352                 reg = <0x38>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 355                 interrupt-parent = <&gpio6>;
 356                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 357                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 358                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 359                 wakeup-source;
 360         };
 361
 362         touchscreen: tsc2007@48 {
 363                 compatible = "ti,tsc2007";
 364                 reg = <0x48>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pinctrl_tsc2007>;
 367                 interrupt-parent = <&gpio3>;
 368                 interrupts = <26 0>;
 369                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 370                 ti,x-plate-ohms = <660>;
 371                 wakeup-source;
 372         };
 373 };
 374
 375 &iomuxc {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_hog>;
 378
 379         pinctrl_hog: hoggrp {
 380                 fsl,pins = <
 381                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 382                 >;
 383         };
 384
 385         pinctrl_audmux: audmuxgrp {
 386                 fsl,pins = <
 387                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 388                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 389                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 390                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 391                 >;
 392         };
 393
 394         pinctrl_disp0_1: disp0grp-1 {
 395                 fsl,pins = <
 396                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 397                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 398                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 399                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 400                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 401                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 402                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 403                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 404                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 405                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 406                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 407                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 408                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 409                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 410                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 411                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 412                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 413                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 414                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 415                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 416                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 417                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 418                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 419                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 420                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 421                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 422                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 423                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 424                 >;
 425         };
 426
 427         pinctrl_disp0_2: disp0grp-2 {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 430                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 431                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 432                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 433                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 434                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 435                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 436                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 437                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 438                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 439                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 440                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 441                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 442                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 443                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 444                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 445                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 446                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 447                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 448                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 449                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 450                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 451                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 452                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 453                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 454                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 455                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 456                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 457                 >;
 458         };
 459
 460         pinctrl_ecspi1: ecspi1grp {
 461                 fsl,pins = <
 462                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 463                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 464                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 465                         MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 466                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 467                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 468                 >;
 469         };
 470
 471         pinctrl_edt_ft5x06: edt-ft5x06grp {
 472                 fsl,pins = <
 473                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 474                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 475                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 476                 >;
 477         };
 478
 479         pinctrl_enet: enetgrp {
 480                 fsl,pins = <
 481                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4000b018
 482                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 483                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 484                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 485                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 486                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 487                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 488                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 489                 >;
 490         };
 491
 492         pinctrl_enet_sleep: enet-sleepgrp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x038b0
 495                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x038b0
 496                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x038b0
 497                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x038b0
 498                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x038b0
 499                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x038b0
 500                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x038b0
 501                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x038b0
 502                 >;
 503         };
 504
 505         pinctrl_enet_mdio: enet-mdiogrp {
 506                 fsl,pins = <
 507                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 508                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 509                 >;
 510         };
 511
 512         pinctrl_enet_mdio_sleep: enet-mdio-sleepgrp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_ENET_MDC__GPIO1_IO31         0x038b0
 515                         MX6QDL_PAD_ENET_MDIO__GPIO1_IO22        0x038b0
 516                 >;
 517         };
 518
 519         pinctrl_etnphy_int: etnphy-intgrp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 522                 >;
 523         };
 524
 525         pinctrl_etnphy_power: etnphy-pwrgrp {
 526                 fsl,pins = <
 527                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 528                 >;
 529         };
 530
 531         pinctrl_etnphy_rst: etnphy-rstgrp {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 534                 >;
 535         };
 536
 537         pinctrl_etnphy_rst_sleep: etnphy-rst-sleepgrp {
 538                 fsl,pins = <
 539                         MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x038b0
 540                 >;
 541         };
 542
 543         pinctrl_flexcan1: flexcan1grp {
 544                 fsl,pins = <
 545                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 546                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 547                 >;
 548         };
 549
 550         pinctrl_flexcan2: flexcan2grp {
 551                 fsl,pins = <
 552                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 553                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 554                 >;
 555         };
 556
 557         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 558                 fsl,pins = <
 559                         MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 560                 >;
 561         };
 562
 563         pinctrl_gpmi_nand: gpminandgrp {
 564                 fsl,pins = <
 565                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 566                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 567                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 568                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 569                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 570                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 571                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 572                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 573                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 574                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 575                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 576                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 577                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 578                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 579                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 580                 >;
 581         };
 582
 583         pinctrl_i2c1: i2c1grp {
 584                 fsl,pins = <
 585                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 586                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 587                 >;
 588         };
 589
 590         pinctrl_i2c1_gpio: i2c1-gpiogrp {
 591                 fsl,pins = <
 592                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x4001b8b1
 593                         MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x4001b8b1
 594                 >;
 595         };
 596
 597         pinctrl_i2c3: i2c3grp {
 598                 fsl,pins = <
 599                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 600                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 601                 >;
 602         };
 603
 604         pinctrl_i2c3_gpio: i2c3-gpiogrp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x4001b8b1
 607                         MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x4001b8b1
 608                 >;
 609         };
 610
 611         pinctrl_kpp: kppgrp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 614                         MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 615                         MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 616                         MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 617                         MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 618                         MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 619                         MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 620                         MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 621                 >;
 622         };
 623
 624         pinctrl_lcd0_pwr: lcd0-pwrgrp {
 625                 fsl,pins = <
 626                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 627                 >;
 628         };
 629
 630         pinctrl_lcd1_pwr: lcd-pwrgrp {
 631                 fsl,pins = <
 632                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 633                 >;
 634         };
 635
 636         pinctrl_pwm1: pwm1grp {
 637                 fsl,pins = <
 638                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 639                 >;
 640         };
 641
 642         pinctrl_pwm2: pwm2grp {
 643                 fsl,pins = <
 644                         MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 645                 >;
 646         };
 647
 648         pinctrl_tsc2007: tsc2007grp {
 649                 fsl,pins = <
 650                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 651                 >;
 652         };
 653
 654         pinctrl_uart1: uart1grp {
 655                 fsl,pins = <
 656                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 657                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 658                 >;
 659         };
 660
 661         pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 662                 fsl,pins = <
 663                         MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 664                         MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 665                 >;
 666         };
 667
 668         pinctrl_uart2: uart2grp {
 669                 fsl,pins = <
 670                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 671                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 672                 >;
 673         };
 674
 675         pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 676                 fsl,pins = <
 677                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 678                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 679                 >;
 680         };
 681
 682         pinctrl_uart3: uart3grp {
 683                 fsl,pins = <
 684                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 685                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 686                 >;
 687         };
 688
 689         pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 690                 fsl,pins = <
 691                         MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 692                         MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 693                 >;
 694         };
 695
 696         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 697                 fsl,pins = <
 698                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 699                 >;
 700         };
 701
 702         pinctrl_usbotg: usbotggrp {
 703                 fsl,pins = <
 704                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 705                 >;
 706         };
 707
 708         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 709                 fsl,pins = <
 710                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 711                 >;
 712         };
 713
 714         pinctrl_usdhc1: usdhc1grp {
 715                 fsl,pins = <
 716                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 717                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 718                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 719                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 720                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 721                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 722                         MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 723                 >;
 724         };
 725
 726         pinctrl_usdhc2: usdhc2grp {
 727                 fsl,pins = <
 728                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 729                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 730                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 731                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 732                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 733                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 734                         MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 735                 >;
 736         };
 737
 738         pinctrl_user_led: user-ledgrp {
 739                 fsl,pins = <
 740                         MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 741                 >;
 742         };
 743 };
 744
 745 &kpp {
 746         pinctrl-names = "default";
 747         pinctrl-0 = <&pinctrl_kpp>;
 748         /* sample keymap */
 749         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 750         linux,keymap = <
 751                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 752                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 753                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 754                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 755                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 756                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 757                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 758                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 759                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 760                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 761                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 762         >;
 763         status = "okay";
 764 };
 765
 766 &pwm1 {
 767         pinctrl-names = "default";
 768         pinctrl-0 = <&pinctrl_pwm1>;
 769         #pwm-cells = <3>;
 770         status = "disabled";
 771 };
 772
 773 &pwm2 {
 774         pinctrl-names = "default";
 775         pinctrl-0 = <&pinctrl_pwm2>;
 776         #pwm-cells = <3>;
 777         status = "okay";
 778 };
 779
 780 &ssi1 {
 781         status = "okay";
 782 };
 783
 784 &uart1 {
 785         pinctrl-names = "default";
 786         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 787         uart-has-rtscts;
 788         status = "okay";
 789 };
 790
 791 &uart2 {
 792         pinctrl-names = "default";
 793         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 794         uart-has-rtscts;
 795         status = "okay";
 796 };
 797
 798 &uart3 {
 799         pinctrl-names = "default";
 800         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 801         uart-has-rtscts;
 802         status = "okay";
 803 };
 804
 805 &usbh1 {
 806         vbus-supply = <&reg_usbh1_vbus>;
 807         dr_mode = "host";
 808         disable-over-current;
 809         status = "okay";
 810 };
 811
 812 &usbotg {
 813         vbus-supply = <&reg_usbotg_vbus>;
 814         pinctrl-names = "default";
 815         pinctrl-0 = <&pinctrl_usbotg>;
 816         dr_mode = "peripheral";
 817         disable-over-current;
 818         status = "okay";
 819 };
 820
 821 &usdhc1 {
 822         pinctrl-names = "default";
 823         pinctrl-0 = <&pinctrl_usdhc1>;
 824         bus-width = <4>;
 825         no-1-8-v;
 826         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
 827         fsl,wp-controller;
 828         status = "okay";
 829 };
 830
 831 &usdhc2 {
 832         pinctrl-names = "default";
 833         pinctrl-0 = <&pinctrl_usdhc2>;
 834         bus-width = <4>;
 835         no-1-8-v;
 836         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
 837         fsl,wp-controller;
 838         status = "okay";
 839 };