ARM: dts: tx6: add enet_out clock for FEC
[karo-tx-linux.git] / arch / arm / boot / dts / imx6qdl-tx6.dtsi
1 /*
2  * Copyright 2014 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * The code contained herein is licensed under the GNU General Public
5  * License. You may obtain a copy of the GNU General Public License
6  * Version 2 at the following locations:
7  *
8  * http://www.opensource.org/licenses/gpl-license.html
9  * http://www.gnu.org/copyleft/gpl.html
10  */
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pwm/pwm.h>
15
16 / {
17         aliases {
18                 can0 = &can2;
19                 can1 = &can1;
20                 ethernet0 = &fec;
21                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
22                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
23                 pwm0 = &pwm1;
24                 pwm1 = &pwm2;
25                 reg_can_xcvr = &reg_can_xcvr;
26                 stk5led = &user_led;
27                 usbotg = &usbotg;
28                 sdhc0 = &usdhc1;
29                 sdhc1 = &usdhc2;
30         };
31
32         memory {
33                 reg = <0 0>; /* will be filled by U-Boot */
34         };
35
36         clocks {
37                 #address-cells = <1>;
38                 #size-cells = <0>;
39                 mclk: clock@0 {
40                         compatible = "fixed-clock";
41                         reg = <0>;
42                         #clock-cells = <0>;
43                         clock-frequency = <27000000>;
44                 };
45         };
46
47         gpio-keys {
48                 compatible = "gpio-keys";
49
50                 power {
51                         label = "Power Button";
52                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
53                         linux,code = <KEY_POWER>;
54                         gpio-key,wakeup;
55                 };
56         };
57
58         leds {
59                 compatible = "gpio-leds";
60
61                 user_led: user {
62                         label = "Heartbeat";
63                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
64                         linux,default-trigger = "heartbeat";
65                 };
66         };
67
68         regulators {
69                 compatible = "simple-bus";
70                 #address-cells = <1>;
71                 #size-cells = <0>;
72
73                 reg_3v3_etn: regulator@0 {
74                         compatible = "regulator-fixed";
75                         reg = <0>;
76                         regulator-name = "3V3_ETN";
77                         regulator-min-microvolt = <3300000>;
78                         regulator-max-microvolt = <3300000>;
79                         pinctrl-names = "default";
80                         pinctrl-0 = <&pinctrl_etnphy_power>;
81                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
82                         enable-active-high;
83                 };
84
85                 reg_2v5: regulator@1 {
86                         compatible = "regulator-fixed";
87                         reg = <1>;
88                         regulator-name = "2V5";
89                         regulator-min-microvolt = <2500000>;
90                         regulator-max-microvolt = <2500000>;
91                         regulator-always-on;
92                 };
93
94                 reg_3v3: regulator@2 {
95                         compatible = "regulator-fixed";
96                         reg = <2>;
97                         regulator-name = "3V3";
98                         regulator-min-microvolt = <3300000>;
99                         regulator-max-microvolt = <3300000>;
100                         regulator-always-on;
101                 };
102
103                 reg_can_xcvr: regulator@3 {
104                         compatible = "regulator-fixed";
105                         reg = <3>;
106                         regulator-name = "CAN XCVR";
107                         regulator-min-microvolt = <3300000>;
108                         regulator-max-microvolt = <3300000>;
109                         pinctrl-names = "default";
110                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
111                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
112                         enable-active-low;
113                 };
114
115                 reg_lcd0_pwr: regulator@4 {
116                         compatible = "regulator-fixed";
117                         reg = <4>;
118                         regulator-name = "LCD0 POWER";
119                         regulator-min-microvolt = <3300000>;
120                         regulator-max-microvolt = <3300000>;
121                         pinctrl-names = "default";
122                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
123                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
124                         enable-active-high;
125                         regulator-boot-on;
126                         regulator-always-on;
127                         status = "disabled";
128                 };
129
130                 reg_lcd1_pwr: regulator@5 {
131                         compatible = "regulator-fixed";
132                         reg = <5>;
133                         regulator-name = "LCD1 POWER";
134                         regulator-min-microvolt = <3300000>;
135                         regulator-max-microvolt = <3300000>;
136                         pinctrl-names = "default";
137                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
138                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
139                         enable-active-high;
140                         regulator-boot-on;
141                         regulator-always-on;
142                         status = "disabled";
143                 };
144
145                 reg_usbh1_vbus: regulator@6 {
146                         compatible = "regulator-fixed";
147                         reg = <6>;
148                         regulator-name = "usbh1_vbus";
149                         regulator-min-microvolt = <5000000>;
150                         regulator-max-microvolt = <5000000>;
151                         pinctrl-names = "default";
152                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
153                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
154                         enable-active-high;
155                 };
156
157                 reg_usbotg_vbus: regulator@7 {
158                         compatible = "regulator-fixed";
159                         reg = <7>;
160                         regulator-name = "usbotg_vbus";
161                         regulator-min-microvolt = <5000000>;
162                         regulator-max-microvolt = <5000000>;
163                         pinctrl-names = "default";
164                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
165                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
166                         enable-active-high;
167                 };
168         };
169
170         sound {
171                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
172                              "fsl,imx-audio-sgtl5000";
173                 model = "sgtl5000-audio";
174                 ssi-controller = <&ssi1>;
175                 audio-codec = <&sgtl5000>;
176                 audio-routing =
177                         "MIC_IN", "Mic Jack",
178                         "Mic Jack", "Mic Bias",
179                         "Headphone Jack", "HP_OUT";
180                 mux-int-port = <1>;
181                 mux-ext-port = <5>;
182         };
183
184         v4l2_out {
185                 compatible = "fsl,mxc_v4l2_output";
186                 status = "okay";
187         };
188 };
189
190 &audmux {
191         pinctrl-names = "default";
192         pinctrl-0 = <&pinctrl_audmux>;
193         status = "okay";
194 };
195
196 &can1 {
197         pinctrl-names = "default";
198         pinctrl-0 = <&pinctrl_flexcan1>;
199         xceiver-supply = <&reg_can_xcvr>;
200         status = "okay";
201 };
202
203 &can2 {
204         pinctrl-names = "default";
205         pinctrl-0 = <&pinctrl_flexcan2>;
206         xceiver-supply = <&reg_can_xcvr>;
207         status = "okay";
208 };
209
210 &ecspi1 {
211         pinctrl-names = "default";
212         pinctrl-0 = <&pinctrl_ecspi1>;
213         fsl,spi-num-chipselects = <2>;
214         cs-gpios = <
215                 &gpio2 30 GPIO_ACTIVE_HIGH
216                 &gpio3 19 GPIO_ACTIVE_HIGH
217         >;
218         status = "okay";
219
220         spidev0: spi@0 {
221                 compatible = "spidev";
222                 reg = <0>;
223                 spi-max-frequency = <54000000>;
224         };
225
226         spidev1: spi@1 {
227                 compatible = "spidev";
228                 reg = <1>;
229                 spi-max-frequency = <54000000>;
230         };
231 };
232
233 &fec {
234         pinctrl-names = "default";
235         pinctrl-0 = <&pinctrl_enet>;
236         phy-mode = "rmii";
237         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
238         phy-supply = <&reg_3v3_etn>;
239         clocks = <&clks 117>, <&clks 117>, <&clks 190>, <&clks 190>;
240         clock-names = "ipg", "ahb", "ptp", "enet_out";
241         status = "okay";
242 };
243
244 &gpmi {
245         pinctrl-names = "default";
246         pinctrl-0 = <&pinctrl_gpmi_nand>;
247         nand-on-flash-bbt;
248         fsl,no-blockmark-swap;
249         status = "okay";
250 };
251
252 &i2c1 {
253         pinctrl-names = "default";
254         pinctrl-0 = <&pinctrl_i2c1>;
255         clock-frequency = <400000>;
256         status = "okay";
257
258         ds1339: rtc@68 {
259                 compatible = "dallas,ds1339";
260                 reg = <0x68>;
261         };
262 };
263
264 &i2c3 {
265         pinctrl-names = "default";
266         pinctrl-0 = <&pinctrl_i2c3>;
267         clock-frequency = <400000>;
268         status = "okay";
269
270         sgtl5000: sgtl5000@0a {
271                 compatible = "fsl,sgtl5000";
272                 reg = <0x0a>;
273                 VDDA-supply = <&reg_2v5>;
274                 VDDIO-supply = <&reg_3v3>;
275                 clocks = <&mclk>;
276         };
277
278         polytouch: edt-ft5x06@38 {
279                 compatible = "edt,edt-ft5x06";
280                 reg = <0x38>;
281                 pinctrl-names = "default";
282                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
283                 interrupt-parent = <&gpio6>;
284                 interrupts = <15 0>;
285                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
286                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
287                 linux,wakeup;
288         };
289
290         touchscreen: tsc2007@48 {
291                 compatible = "ti,tsc2007";
292                 reg = <0x48>;
293                 pinctrl-names = "default";
294                 pinctrl-0 = <&pinctrl_tsc2007>;
295                 interrupt-parent = <&gpio3>;
296                 interrupts = <26 0>;
297                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
298                 ti,x-plate-ohms = <660>;
299                 linux,wakeup;
300         };
301 };
302
303 &iomuxc {
304         pinctrl-names = "default";
305         pinctrl-0 = <&pinctrl_hog>;
306
307         imx6qdl-tx6 {
308                 pinctrl_hog: hoggrp {
309                         fsl,pins = <
310                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
311                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
312                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
313                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
314                         >;
315                 };
316
317                 pinctrl_audmux: audmuxgrp {
318                         fsl,pins = <
319                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
320                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
321                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
322                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
323                         >;
324                 };
325
326                 pinctrl_disp0_1: disp0grp-1 {
327                         fsl,pins = <
328                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
329                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
330                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
331                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
332                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
333                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
334                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
335                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
336                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
337                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
338                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
339                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
340                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
341                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
342                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
343                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
344                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
345                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
346                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
347                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
348                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
349                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
350                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
351                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
352                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
353                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
354                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
355                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
356                         >;
357                 };
358
359                 pinctrl_disp0_2: disp0grp-2 {
360                         fsl,pins = <
361                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
362                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
363                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
364                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
365                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
366                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
367                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
368                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
369                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
370                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
371                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
372                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
373                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
374                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
375                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
376                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
377                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
378                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
379                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
380                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
381                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
382                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
383                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
384                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
385                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
386                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
387                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
388                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
389                         >;
390                 };
391
392                 pinctrl_ecspi1: ecspi1grp {
393                         fsl,pins = <
394                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
395                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
396                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
397                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
398                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
399                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
400                         >;
401                 };
402
403                 pinctrl_edt_ft5x06: edt-ft5x06grp {
404                         fsl,pins = <
405                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
406                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
407                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
408                         >;
409                 };
410
411                 pinctrl_enet: enetgrp {
412                         fsl,pins = <
413                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
414                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
415                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
416                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
417                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
418                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
419                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
420                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
421                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
422                         >;
423                 };
424
425                 pinctrl_etnphy_power: etnphy-pwrgrp {
426                         fsl,pins = <
427                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
428                         >;
429                 };
430
431                 pinctrl_flexcan1: flexcan1grp {
432                         fsl,pins = <
433                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
434                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
435                         >;
436                 };
437
438                 pinctrl_flexcan2: flexcan2grp {
439                         fsl,pins = <
440                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
441                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
442                         >;
443                 };
444
445                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
446                         fsl,pins = <
447                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
448                         >;
449                 };
450
451                 pinctrl_gpmi_nand: gpminandgrp {
452                         fsl,pins = <
453                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
454                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
455                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
456                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
457                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
458                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
459                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
460                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
461                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
462                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
463                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
464                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
465                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
466                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
467                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
468                         >;
469                 };
470
471                 pinctrl_i2c1: i2c1grp {
472                         fsl,pins = <
473                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
474                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
475                         >;
476                 };
477
478                 pinctrl_i2c3: i2c3grp {
479                         fsl,pins = <
480                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
481                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
482                         >;
483                 };
484
485                 pinctrl_kpp: kppgrp {
486                         fsl,pins = <
487                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
488                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
489                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
490                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
491                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
492                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
493                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
494                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
495                         >;
496                 };
497
498                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
499                         fsl,pins = <
500                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
501                         >;
502                 };
503
504                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
505                         fsl,pins = <
506                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
507                         >;
508                 };
509
510                 pinctrl_pwm1: pwm1grp {
511                         fsl,pins = <
512                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
513                         >;
514                 };
515
516                 pinctrl_pwm2: pwm2grp {
517                         fsl,pins = <
518                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
519                         >;
520                 };
521
522                 pinctrl_tsc2007: tsc2007grp {
523                         fsl,pins = <
524                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
525                         >;
526                 };
527
528                 pinctrl_uart1: uart1grp {
529                         fsl,pins = <
530                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
531                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
532                         >;
533                 };
534
535                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
536                         fsl,pins = <
537                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
538                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
539                         >;
540                 };
541
542                 pinctrl_uart2: uart2grp {
543                         fsl,pins = <
544                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
545                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
546                         >;
547                 };
548
549                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
550                         fsl,pins = <
551                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
552                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
553                         >;
554                 };
555
556                 pinctrl_uart3: uart3grp {
557                         fsl,pins = <
558                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
559                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
560                         >;
561                 };
562
563                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
564                         fsl,pins = <
565                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
566                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
567                         >;
568                 };
569
570                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
571                         fsl,pins = <
572                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
573                         >;
574                 };
575
576                 pinctrl_usbotg: usbotggrp {
577                         fsl,pins = <
578                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
579                         >;
580                 };
581
582                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
583                         fsl,pins = <
584                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
585                         >;
586                 };
587
588                 pinctrl_usdhc1: usdhc1grp {
589                         fsl,pins = <
590                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
591                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
592                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
593                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
594                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
595                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
596                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
597                         >;
598                 };
599
600                 pinctrl_usdhc2: usdhc2grp {
601                         fsl,pins = <
602                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
603                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
604                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
605                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
606                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
607                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
608                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
609                         >;
610                 };
611         };
612 };
613
614 &kpp {
615         pinctrl-names = "default";
616         pinctrl-0 = <&pinctrl_kpp>;
617         /* sample keymap */
618         /* row/col 0,1 are mapped to KPP row/col 6,7 */
619         linux,keymap = <
620                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
621                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
622                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
623                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
624                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
625                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
626                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
627                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
628                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
629                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
630                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
631         >;
632 };
633
634 &pwm1 {
635         pinctrl-names = "default";
636         pinctrl-0 = <&pinctrl_pwm1>;
637         #pwm-cells = <3>;
638         status = "disabled";
639 };
640
641 &pwm2 {
642         pinctrl-names = "default";
643         pinctrl-0 = <&pinctrl_pwm2>;
644         #pwm-cells = <3>;
645         status = "okay";
646 };
647
648 &ssi1 {
649         fsl,mode = "i2s-slave";
650         status = "okay";
651 };
652
653 &uart1 {
654         pinctrl-names = "default";
655         pinctrl-0 = <&pinctrl_uart1>;
656         status = "okay";
657 };
658
659 &uart2 {
660         pinctrl-names = "default";
661         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
662         status = "okay";
663 };
664
665 &uart3 {
666         pinctrl-names = "default";
667         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
668         status = "okay";
669 };
670
671 &usbh1 {
672         vbus-supply = <&reg_usbh1_vbus>;
673         dr_mode = "host";
674         disable-over-current;
675         status = "okay";
676 };
677
678 &usbotg {
679         vbus-supply = <&reg_usbotg_vbus>;
680         pinctrl-names = "default";
681         pinctrl-0 = <&pinctrl_usbotg>;
682         dr_mode = "peripheral";
683         disable-over-current;
684         status = "okay";
685 };
686
687 &usdhc1 {
688         pinctrl-names = "default";
689         pinctrl-0 = <&pinctrl_usdhc1>;
690         bus-width = <4>;
691         no-1-8-v;
692         cd-gpios = <&gpio7 2 0>;
693         fsl,wp-controller;
694         status = "okay";
695 };
696
697 &usdhc2 {
698         pinctrl-names = "default";
699         pinctrl-0 = <&pinctrl_usdhc2>;
700         bus-width = <4>;
701         no-1-8-v;
702         cd-gpios = <&gpio7 3 0>;
703         fsl,wp-controller;
704         status = "okay";
705 };
706
707 &vpu {
708         pu-supply = <&reg_3v3>;
709 };