arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         aliases {
  17                 can0 = &can2;
  18                 can1 = &can1;
  19                 display = &display;
  20                 ethernet0 = &fec;
  21                 lcdif_23bit_pins_a = &tx6_pinctrl_disp0_1;
  22                 lcdif_24bit_pins_a = &tx6_pinctrl_disp0_2;
  23                 lvds0 = &lvds0;
  24                 lvds1 = &lvds1;
  25                 pwm0 = &pwm1;
  26                 pwm1 = &pwm2;
  27                 reg_can_xcvr = &reg_can_xcvr;
  28                 stk5led = &user_led;
  29                 usbotg = &usbotg;
  30                 sdhc0 = &usdhc1;
  31                 sdhc1 = &usdhc2;
  32         };
  33
  34         memory {
  35                 reg = <0 0>; /* will be filled by U-Boot */
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 mclk: codec_clock {
  42                         compatible = "fixed-clock";
  43                         reg = <0>;
  44                         #clock-cells = <0>;
  45                         clock-frequency = <27000000>;
  46                 };
  47         };
  48
  49         backlight: backlight@0 {
  50                 compatible = "pwm-backlight";
  51                 pwms = <&pwm2 0 500000>;
  52                 power-supply = <&reg_3v3>;
  53                 /*
  54                  * a poor man's way to create an inverse 1:1 relationship
  55                  * between the PWM value and the actual duty cycle
  56                  */
  57                 brightness-levels = <100
  58                                       99 98 97 96 95 94 93 92 91 90
  59                                       89 88 87 86 85 84 83 82 81 80
  60                                       79 78 77 76 75 74 73 72 71 70
  61                                       69 68 67 66 65 64 63 62 61 60
  62                                       59 58 57 56 55 54 53 52 51 50
  63                                       49 48 47 46 45 44 43 42 41 40
  64                                       39 38 37 36 35 34 33 32 31 30
  65                                       29 28 27 26 25 24 23 22 21 20
  66                                       19 18 17 16 15 14 13 12 11 10
  67                                        9  8  7  6  5  4  3  2  1  0>;
  68                 default-brightness-level = <50>;
  69         };
  70
  71         backlight@1 {
  72                 compatible = "pwm-backlight";
  73                 pwms = <&pwm1 0 500000>;
  74                 power-supply = <&reg_3v3>;
  75                 /*
  76                  * a poor man's way to create a 1:1 relationship between
  77                  * the PWM value and the actual duty cycle
  78                  */
  79                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  80                                      10 11 12 13 14 15 16 17 18 19
  81                                      20 21 22 23 24 25 26 27 28 29
  82                                      30 31 32 33 34 35 36 37 38 39
  83                                      40 41 42 43 44 45 46 47 48 49
  84                                      50 51 52 53 54 55 56 57 58 59
  85                                      60 61 62 63 64 65 66 67 68 69
  86                                      70 71 72 73 74 75 76 77 78 79
  87                                      80 81 82 83 84 85 86 87 88 89
  88                                      90 91 92 93 94 95 96 97 98 99
  89                                     100>;
  90                 default-brightness-level = <50>;
  91                 status = "disabled";
  92         };
  93
  94         display: display@di0 {
  95                 compatible = "fsl,imx-parallel-display";
  96                 crtcs = <&ipu1 0>;
  97                 interface-pix-fmt = "rgb24";
  98                 pinctrl-names = "default";
  99                 pinctrl-0 = <&tx6_pinctrl_disp0_1>;
 100                 status = "okay";
 101
 102                 display-timings {
 103                         VGA {
 104                                 clock-frequency = <25200000>;
 105                                 hactive = <640>;
 106                                 vactive = <480>;
 107                                 hback-porch = <48>;
 108                                 hsync-len = <96>;
 109                                 hfront-porch = <16>;
 110                                 vback-porch = <31>;
 111                                 vsync-len = <2>;
 112                                 vfront-porch = <12>;
 113                                 hsync-active = <0>;
 114                                 vsync-active = <0>;
 115                                 de-active = <1>;
 116                                 pixelclk-active = <0>;
 117                         };
 118
 119                         ETV570 {
 120                                 clock-frequency = <25200000>;
 121                                 hactive = <640>;
 122                                 vactive = <480>;
 123                                 hback-porch = <114>;
 124                                 hsync-len = <30>;
 125                                 hfront-porch = <16>;
 126                                 vback-porch = <32>;
 127                                 vsync-len = <3>;
 128                                 vfront-porch = <10>;
 129                                 hsync-active = <0>;
 130                                 vsync-active = <0>;
 131                                 de-active = <1>;
 132                                 pixelclk-active = <0>;
 133                         };
 134
 135                         ET0350 {
 136                                 clock-frequency = <6413760>;
 137                                 hactive = <320>;
 138                                 vactive = <240>;
 139                                 hback-porch = <34>;
 140                                 hsync-len = <34>;
 141                                 hfront-porch = <20>;
 142                                 vback-porch = <15>;
 143                                 vsync-len = <3>;
 144                                 vfront-porch = <4>;
 145                                 hsync-active = <0>;
 146                                 vsync-active = <0>;
 147                                 de-active = <1>;
 148                                 pixelclk-active = <0>;
 149                         };
 150
 151                         ET0430 {
 152                                 clock-frequency = <9009000>;
 153                                 hactive = <480>;
 154                                 vactive = <272>;
 155                                 hback-porch = <2>;
 156                                 hsync-len = <41>;
 157                                 hfront-porch = <2>;
 158                                 vback-porch = <2>;
 159                                 vsync-len = <10>;
 160                                 vfront-porch = <2>;
 161                                 hsync-active = <0>;
 162                                 vsync-active = <0>;
 163                                 de-active = <1>;
 164                                 pixelclk-active = <1>;
 165                         };
 166
 167                         ET0500 {
 168                                 clock-frequency = <33264000>;
 169                                 hactive = <800>;
 170                                 vactive = <480>;
 171                                 hback-porch = <88>;
 172                                 hsync-len = <128>;
 173                                 hfront-porch = <40>;
 174                                 vback-porch = <33>;
 175                                 vsync-len = <2>;
 176                                 vfront-porch = <10>;
 177                                 hsync-active = <0>;
 178                                 vsync-active = <0>;
 179                                 de-active = <1>;
 180                                 pixelclk-active = <0>;
 181                         };
 182
 183                         ET0700 { /* same as ET0500 */
 184                                 clock-frequency = <33264000>;
 185                                 hactive = <800>;
 186                                 vactive = <480>;
 187                                 hback-porch = <88>;
 188                                 hsync-len = <128>;
 189                                 hfront-porch = <40>;
 190                                 vback-porch = <33>;
 191                                 vsync-len = <2>;
 192                                 vfront-porch = <10>;
 193                                 hsync-active = <0>;
 194                                 vsync-active = <0>;
 195                                 de-active = <1>;
 196                                 pixelclk-active = <0>;
 197                         };
 198
 199                         ETQ570 {
 200                                 clock-frequency = <6596040>;
 201                                 hactive = <320>;
 202                                 vactive = <240>;
 203                                 hback-porch = <38>;
 204                                 hsync-len = <30>;
 205                                 hfront-porch = <30>;
 206                                 vback-porch = <16>;
 207                                 vsync-len = <3>;
 208                                 vfront-porch = <4>;
 209                                 hsync-active = <0>;
 210                                 vsync-active = <0>;
 211                                 de-active = <1>;
 212                                 pixelclk-active = <0>;
 213                         };
 214                 };
 215         };
 216
 217         gpio-keys {
 218                 compatible = "gpio-keys";
 219
 220                 power {
 221                         label = "Power Button";
 222                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 223                         linux,code = <KEY_POWER>;
 224                         gpio-key,wakeup;
 225                 };
 226         };
 227
 228         leds {
 229                 compatible = "gpio-leds";
 230
 231                 user_led: user {
 232                         label = "Heartbeat";
 233                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
 234                         linux,default-trigger = "heartbeat";
 235                 };
 236         };
 237
 238         regulators {
 239                 compatible = "simple-bus";
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242
 243                 reg_3v3_etn: regulator@0 {
 244                         compatible = "regulator-fixed";
 245                         reg = <0>;
 246                         regulator-name = "3V3_ETN";
 247                         regulator-min-microvolt = <3300000>;
 248                         regulator-max-microvolt = <3300000>;
 249                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 250                         enable-active-high;
 251                 };
 252
 253                 reg_2v5: regulator@1 {
 254                         compatible = "regulator-fixed";
 255                         reg = <1>;
 256                         regulator-name = "2V5";
 257                         regulator-min-microvolt = <2500000>;
 258                         regulator-max-microvolt = <2500000>;
 259                         regulator-always-on;
 260                 };
 261
 262                 reg_3v3: regulator@2 {
 263                         compatible = "regulator-fixed";
 264                         reg = <2>;
 265                         regulator-name = "3V3";
 266                         regulator-min-microvolt = <3300000>;
 267                         regulator-max-microvolt = <3300000>;
 268                         regulator-always-on;
 269                 };
 270
 271                 reg_can_xcvr: regulator@3 {
 272                         compatible = "regulator-fixed";
 273                         reg = <3>;
 274                         regulator-name = "CAN XCVR";
 275                         regulator-min-microvolt = <3300000>;
 276                         regulator-max-microvolt = <3300000>;
 277                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 278                         enable-active-low;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_tx6qdl_flexcan_xcvr>;
 281                 };
 282
 283                 reg_lcd_pwr0: regulator@4 {
 284                         compatible = "regulator-fixed";
 285                         reg = <4>;
 286                         regulator-name = "LCD0 POWER";
 287                         regulator-min-microvolt = <3300000>;
 288                         regulator-max-microvolt = <3300000>;
 289                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 290                         enable-active-high;
 291                 };
 292
 293                 reg_lcd_pwr1: regulator@5 {
 294                         compatible = "regulator-fixed";
 295                         reg = <5>;
 296                         regulator-name = "LCD1 POWER";
 297                         regulator-min-microvolt = <3300000>;
 298                         regulator-max-microvolt = <3300000>;
 299                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 300                         enable-active-high;
 301                 };
 302
 303                 reg_lcd_reset: regulator@6 {
 304                         compatible = "regulator-fixed";
 305                         reg = <6>;
 306                         regulator-name = "LCD RESET";
 307                         regulator-min-microvolt = <3300000>;
 308                         regulator-max-microvolt = <3300000>;
 309                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 310                         startup-delay-us = <300000>;
 311                         enable-active-high;
 312                         regulator-always-on;
 313                 };
 314
 315                 reg_usbh1_vbus: regulator@7 {
 316                         compatible = "regulator-fixed";
 317                         reg = <7>;
 318                         regulator-name = "usbh1_vbus";
 319                         regulator-min-microvolt = <5000000>;
 320                         regulator-max-microvolt = <5000000>;
 321                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 322                         enable-active-high;
 323                 };
 324
 325                 reg_usbotg_vbus: regulator@8 {
 326                         compatible = "regulator-fixed";
 327                         reg = <8>;
 328                         regulator-name = "usbotg_vbus";
 329                         regulator-min-microvolt = <5000000>;
 330                         regulator-max-microvolt = <5000000>;
 331                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 332                         enable-active-high;
 333                 };
 334         };
 335
 336         sound {
 337                 compatible = "fsl,imx6qdl-tx6qdl-sgtl5000",
 338                              "fsl,imx-audio-sgtl5000";
 339                 model = "sgtl5000-audio";
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&pinctrl_audmux_5>;
 342                 ssi-controller = <&ssi1>;
 343                 audio-codec = <&sgtl5000>;
 344                 audio-routing =
 345                         "MIC_IN", "Mic Jack",
 346                         "Mic Jack", "Mic Bias",
 347                         "Headphone Jack", "HP_OUT";
 348                 mux-int-port = <1>;
 349                 mux-ext-port = <5>;
 350         };
 351 };
 352
 353 &audmux {
 354         status = "okay";
 355 };
 356
 357 &can1 {
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_flexcan1_3>;
 360         xceiver-supply = <&reg_can_xcvr>;
 361
 362         status = "okay";
 363 };
 364
 365 &can2 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_flexcan2_1>;
 368         xceiver-supply = <&reg_can_xcvr>;
 369
 370         status = "okay";
 371 };
 372
 373 &fec {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_enet_4>;
 376         phy-mode = "rmii";
 377         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 378         phy-supply = <&reg_3v3_etn>;
 379         status = "okay";
 380 };
 381
 382 &gpmi {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_tx6_gpmi_nand>;
 385         nand-on-flash-bbt;
 386         status = "okay";
 387 };
 388
 389 &i2c1 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_i2c1_1>;
 392         clock-frequency = <400000>;
 393         status = "okay";
 394
 395         ds1339: rtc@68 {
 396                 compatible = "dallas,ds1339";
 397                 reg = <0x68>;
 398         };
 399 };
 400
 401 &i2c3 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_i2c3_2>;
 404         clock-frequency = <400000>;
 405         status = "okay";
 406
 407         touchscreen: tsc2007@48 {
 408                 compatible = "ti,tsc2007";
 409                 reg = <0x48>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&pinctrl_tsc2007_1>;
 412                 interrupt-parent = <&gpio3>;
 413                 interrupts = <26 0>;
 414                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 415                 ti,x-plate-ohms = <660>;
 416                 linux,wakeup;
 417         };
 418
 419         polytouch: edt-ft5x06@38 {
 420                 compatible = "edt,edt-ft5x06";
 421                 reg = <0x38>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
 424                 interrupt-parent = <&gpio6>;
 425                 interrupts = <15 0>;
 426                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 427                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 428         };
 429
 430         sgtl5000: sgtl5000@0a {
 431                 compatible = "fsl,sgtl5000";
 432                 reg = <0x0a>;
 433                 VDDA-supply = <&reg_2v5>;
 434                 VDDIO-supply = <&reg_3v3>;
 435                 clocks = <&mclk>;
 436         };
 437 };
 438
 439 &iomuxc {
 440         pinctrl-names = "default";
 441         pinctrl-0 = <&pinctrl_hog>;
 442
 443         display {
 444                 tx6_pinctrl_disp0_1: disp0grp-1 {
 445                         fsl,pins = <
 446                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 447                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 448                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 449                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 450                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 451                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 452                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 453                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 454                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 455                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 456                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 457                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 458                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 459                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 460                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 461                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 462                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 463                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 464                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 465                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 466                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 467                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 468                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 469                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 470                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 471                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 472                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 473                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 474                         >;
 475                 };
 476
 477                 tx6_pinctrl_disp0_2: disp0grp-2 {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 480                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 481                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 482                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 483                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 484                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 485                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 486                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 487                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 488                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 489                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 490                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 491                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 492                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 493                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 494                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 495                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 496                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 497                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 498                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 499                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 500                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 501                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 502                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 503                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 504                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 505                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 506                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 507                         >;
 508                 };
 509         };
 510
 511         flexcan {
 512                 pinctrl_tx6qdl_flexcan_xcvr: flexcan-xcvrgrp-1 {
 513                         fsl,pins = <
 514                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
 515                         >;
 516                 };
 517         };
 518
 519         hog {
 520                 pinctrl_hog: hoggrp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
 523                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
 524                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
 525                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT
 526                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* SD1 CD */
 527                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* SD2 CD */
 528                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
 529                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
 530                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
 531                         >;
 532                 };
 533         };
 534
 535         kpp {
 536                 pinctrl_kpp: kppgrp {
 537                         fsl,pins = <
 538                                 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
 539                                 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
 540                                 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
 541                                 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
 542
 543                                 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
 544                                 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
 545                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
 546                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
 547                         >;
 548                 };
 549         };
 550
 551         nand {
 552                 pinctrl_tx6_gpmi_nand: tx6-gpmi-nand {
 553                         fsl,pins = <
 554                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 555                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 556                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 557                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 558                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 559                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 560                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 561                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 562                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 563                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 564                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 565                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 566                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 567                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 568                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 569                         >;
 570                 };
 571         };
 572
 573         touchpanel {
 574                 pinctrl_tsc2007_1: tsc2007grp-1 {
 575                         fsl,pins = <
 576                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
 577                         >;
 578                 };
 579
 580                 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
 583                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22   0x1b0b0 /* Reset */
 584                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21   0x1b0b0 /* Wake */
 585                         >;
 586                 };
 587         };
 588
 589         usbh1 {
 590                 pinctrl_tx6_usbh1_vbus: tx6-usbh1-vbusgrp {
 591                         fsl,pins = <
 592                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
 593                         >;
 594                 };
 595         };
 596
 597         usbotg {
 598                 pinctrl_tx6_usbotg: tx6-usbotggrp {
 599                         fsl,pins = <
 600                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
 601                         >;
 602                 };
 603
 604                 pinctrl_tx6_usbotg_vbus: tx6-usbotg-vbusgrp {
 605                         fsl,pins = <
 606                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
 607                         >;
 608                 };
 609         };
 610 };
 611
 612 &kpp {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_kpp>;
 615         /* sample keymap */
 616         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 617         linux,keymap = <
 618                 0x06060074 /* row 6, col 6, KEY_POWER */
 619                 0x06070052 /* row 6, col 7, KEY_KP0 */
 620                 0x0602004f /* row 6, col 2, KEY_KP1 */
 621                 0x06030050 /* row 6, col 3, KEY_KP2 */
 622                 0x07060051 /* row 7, col 6, KEY_KP3 */
 623                 0x0707004b /* row 7, col 7, KEY_KP4 */
 624                 0x0702004c /* row 7, col 2, KEY_KP5 */
 625                 0x0703004d /* row 7, col 3, KEY_KP6 */
 626                 0x02060047 /* row 2, col 6, KEY_KP7 */
 627                 0x02070048 /* row 2, col 7, KEY_KP8 */
 628                 0x02020049 /* row 2, col 2, KEY_KP9 */
 629         >;
 630 };
 631
 632 &ldb {
 633         status = "okay";
 634
 635         lvds0: lvds-channel@0 {
 636                 fsl,data-mapping = "spwg";
 637                 fsl,data-width = <18>;
 638                 status = "okay";
 639
 640                 display-timings {
 641                         native-mode = <&lvds_timing0>;
 642                         lvds_timing0: hsd100pxn1 {
 643                                 clock-frequency = <65000000>;
 644                                 hactive = <1024>;
 645                                 vactive = <768>;
 646                                 hback-porch = <220>;
 647                                 hfront-porch = <40>;
 648                                 vback-porch = <21>;
 649                                 vfront-porch = <7>;
 650                                 hsync-len = <60>;
 651                                 vsync-len = <10>;
 652                         };
 653                 };
 654         };
 655
 656         lvds1: lvds-channel@1 {
 657                 fsl,data-mapping = "spwg";
 658                 fsl,data-width = <18>;
 659                 status = "okay";
 660
 661                 display-timings {
 662                         native-mode = <&lvds_timing1>;
 663                         lvds_timing1: hsd100pxn1 {
 664                                 clock-frequency = <65000000>;
 665                                 hactive = <1024>;
 666                                 vactive = <768>;
 667                                 hback-porch = <220>;
 668                                 hfront-porch = <40>;
 669                                 vback-porch = <21>;
 670                                 vfront-porch = <7>;
 671                                 hsync-len = <60>;
 672                                 vsync-len = <10>;
 673                         };
 674                 };
 675         };
 676 };
 677
 678 &pwm1 {
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&pinctrl_pwm1_2>;
 681         status = "okay";
 682 };
 683
 684 &pwm2 {
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&pinctrl_pwm2_1>;
 687         status = "okay";
 688 };
 689
 690 &ssi1 {
 691         fsl,mode = "i2s-slave";
 692         status = "okay";
 693 };
 694
 695 &uart1 {
 696         pinctrl-names = "default";
 697         pinctrl-0 = <&pinctrl_uart1_2>;
 698         status = "okay";
 699 };
 700
 701 &uart2 {
 702         pinctrl-names = "default";
 703         pinctrl-0 = <&pinctrl_uart2_3 &pinctrl_uart2_rtscts_3>;
 704         status = "okay";
 705 };
 706
 707 &uart3 {
 708         pinctrl-names = "default";
 709         pinctrl-0 = <&pinctrl_uart3_3 &pinctrl_uart3_rtscts_3>;
 710         status = "okay";
 711 };
 712
 713 &usbh1 {
 714         vbus-supply = <&reg_usbh1_vbus>;
 715         pinctrl-names = "default";
 716         pinctrl-0 = <&pinctrl_tx6_usbh1_vbus>;
 717         dr_mode = "host";
 718         disable-over-current;
 719         status = "okay";
 720 };
 721
 722 &usbotg {
 723         vbus-supply = <&reg_usbotg_vbus>;
 724         pinctrl-names = "default";
 725         pinctrl-0 = <&pinctrl_tx6_usbotg &pinctrl_tx6_usbotg_vbus>;
 726         dr_mode = "peripheral";
 727         disable-over-current;
 728         status = "okay";
 729 };
 730
 731 &usdhc1 {
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&pinctrl_usdhc1_2>;
 734         cd-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
 735         status = "okay";
 736 };
 737
 738 &usdhc2 {
 739         pinctrl-names = "default";
 740         pinctrl-0 = <&pinctrl_usdhc2_2>;
 741         cd-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
 742         status = "okay";
 743 };