arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14
  15 / {
  16         aliases {
  17                 can0 = &can2;
  18                 can1 = &can1;
  19                 ethernet0 = &fec;
  20                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  21                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  22                 pwm0 = &pwm1;
  23                 pwm1 = &pwm2;
  24                 reg_can_xcvr = &reg_can_xcvr;
  25                 stk5led = &user_led;
  26                 usbotg = &usbotg;
  27                 sdhc0 = &usdhc1;
  28                 sdhc1 = &usdhc2;
  29         };
  30
  31         memory {
  32                 reg = <0 0>; /* will be filled by U-Boot */
  33         };
  34
  35         clocks {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 mclk: clock@0 {
  39                         compatible = "fixed-clock";
  40                         reg = <0>;
  41                         #clock-cells = <0>;
  42                         clock-frequency = <27000000>;
  43                 };
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48
  49                 power {
  50                         label = "Power Button";
  51                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  52                         linux,code = <116>; /* KEY_POWER */
  53                         gpio-key,wakeup;
  54                 };
  55         };
  56
  57         leds {
  58                 compatible = "gpio-leds";
  59
  60                 user_led: user {
  61                         label = "Heartbeat";
  62                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  63                         linux,default-trigger = "heartbeat";
  64                 };
  65         };
  66
  67         regulators {
  68                 compatible = "simple-bus";
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 reg_3v3_etn: regulator@0 {
  73                         compatible = "regulator-fixed";
  74                         reg = <0>;
  75                         regulator-name = "3V3_ETN";
  76                         regulator-min-microvolt = <3300000>;
  77                         regulator-max-microvolt = <3300000>;
  78                         pinctrl-names = "default";
  79                         pinctrl-0 = <&pinctrl_etnphy_power>;
  80                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  81                         enable-active-high;
  82                 };
  83
  84                 reg_2v5: regulator@1 {
  85                         compatible = "regulator-fixed";
  86                         reg = <1>;
  87                         regulator-name = "2V5";
  88                         regulator-min-microvolt = <2500000>;
  89                         regulator-max-microvolt = <2500000>;
  90                         regulator-always-on;
  91                 };
  92
  93                 reg_3v3: regulator@2 {
  94                         compatible = "regulator-fixed";
  95                         reg = <2>;
  96                         regulator-name = "3V3";
  97                         regulator-min-microvolt = <3300000>;
  98                         regulator-max-microvolt = <3300000>;
  99                         regulator-always-on;
 100                 };
 101
 102                 reg_can_xcvr: regulator@3 {
 103                         compatible = "regulator-fixed";
 104                         reg = <3>;
 105                         regulator-name = "CAN XCVR";
 106                         regulator-min-microvolt = <3300000>;
 107                         regulator-max-microvolt = <3300000>;
 108                         pinctrl-names = "default";
 109                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 110                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 111                         enable-active-low;
 112                 };
 113
 114                 reg_lcd0_pwr: regulator@4 {
 115                         compatible = "regulator-fixed";
 116                         reg = <4>;
 117                         regulator-name = "LCD0 POWER";
 118                         regulator-min-microvolt = <3300000>;
 119                         regulator-max-microvolt = <3300000>;
 120                         pinctrl-names = "default";
 121                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
 122                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                         regulator-boot-on;
 125                         regulator-always-on;
 126                         status = "disabled";
 127                 };
 128
 129                 reg_lcd1_pwr: regulator@5 {
 130                         compatible = "regulator-fixed";
 131                         reg = <5>;
 132                         regulator-name = "LCD1 POWER";
 133                         regulator-min-microvolt = <3300000>;
 134                         regulator-max-microvolt = <3300000>;
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
 137                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 138                         enable-active-high;
 139                         regulator-boot-on;
 140                         regulator-always-on;
 141                         status = "disabled";
 142                 };
 143
 144                 reg_usbh1_vbus: regulator@6 {
 145                         compatible = "regulator-fixed";
 146                         reg = <6>;
 147                         regulator-name = "usbh1_vbus";
 148                         regulator-min-microvolt = <5000000>;
 149                         regulator-max-microvolt = <5000000>;
 150                         pinctrl-names = "default";
 151                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 152                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 153                         enable-active-high;
 154                 };
 155
 156                 reg_usbotg_vbus: regulator@7 {
 157                         compatible = "regulator-fixed";
 158                         reg = <7>;
 159                         regulator-name = "usbotg_vbus";
 160                         regulator-min-microvolt = <5000000>;
 161                         regulator-max-microvolt = <5000000>;
 162                         pinctrl-names = "default";
 163                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 164                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 165                         enable-active-high;
 166                 };
 167         };
 168
 169         sound {
 170                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 171                              "fsl,imx-audio-sgtl5000";
 172                 model = "sgtl5000-audio";
 173                 ssi-controller = <&ssi1>;
 174                 audio-codec = <&sgtl5000>;
 175                 audio-routing =
 176                         "MIC_IN", "Mic Jack",
 177                         "Mic Jack", "Mic Bias",
 178                         "Headphone Jack", "HP_OUT";
 179                 mux-int-port = <1>;
 180                 mux-ext-port = <5>;
 181         };
 182
 183         v4l2_out {
 184                 compatible = "fsl,mxc_v4l2_output";
 185                 status = "okay";
 186         };
 187 };
 188
 189 &audmux {
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_audmux>;
 192         status = "okay";
 193 };
 194
 195 &can1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_flexcan1>;
 198         xceiver-supply = <&reg_can_xcvr>;
 199         status = "okay";
 200 };
 201
 202 &can2 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_flexcan2>;
 205         xceiver-supply = <&reg_can_xcvr>;
 206         status = "okay";
 207 };
 208
 209 &ecspi1 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_ecspi1>;
 212         fsl,spi-num-chipselects = <2>;
 213         cs-gpios = <
 214                 &gpio2 30 GPIO_ACTIVE_HIGH
 215                 &gpio3 19 GPIO_ACTIVE_HIGH
 216         >;
 217         status = "okay";
 218
 219         spidev0: spi@0 {
 220                 compatible = "spidev";
 221                 reg = <0>;
 222                 spi-max-frequency = <54000000>;
 223         };
 224
 225         spidev1: spi@1 {
 226                 compatible = "spidev";
 227                 reg = <1>;
 228                 spi-max-frequency = <54000000>;
 229         };
 230 };
 231
 232 &fec {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_enet>;
 235         phy-mode = "rmii";
 236         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 237         phy-supply = <&reg_3v3_etn>;
 238         status = "okay";
 239 };
 240
 241 &gpmi {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_gpmi_nand>;
 244         nand-on-flash-bbt;
 245         fsl,no-blockmark-swap;
 246         status = "okay";
 247 };
 248
 249 &i2c1 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_i2c1>;
 252         clock-frequency = <400000>;
 253         status = "okay";
 254
 255         ds1339: rtc@68 {
 256                 compatible = "dallas,ds1339";
 257                 reg = <0x68>;
 258         };
 259 };
 260
 261 &i2c3 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_i2c3>;
 264         clock-frequency = <400000>;
 265         status = "okay";
 266
 267         sgtl5000: sgtl5000@0a {
 268                 compatible = "fsl,sgtl5000";
 269                 reg = <0x0a>;
 270                 VDDA-supply = <&reg_2v5>;
 271                 VDDIO-supply = <&reg_3v3>;
 272                 clocks = <&mclk>;
 273         };
 274
 275         polytouch: edt-ft5x06@38 {
 276                 compatible = "edt,edt-ft5x06";
 277                 reg = <0x38>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 280                 interrupt-parent = <&gpio6>;
 281                 interrupts = <15 0>;
 282                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 283                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 284                 linux,wakeup;
 285         };
 286
 287         touchscreen: tsc2007@48 {
 288                 compatible = "ti,tsc2007";
 289                 reg = <0x48>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&pinctrl_tsc2007>;
 292                 interrupt-parent = <&gpio3>;
 293                 interrupts = <26 0>;
 294                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 295                 ti,x-plate-ohms = <660>;
 296                 linux,wakeup;
 297         };
 298 };
 299
 300 &iomuxc {
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_hog>;
 303
 304         imx6qdl-tx6 {
 305                 pinctrl_hog: hoggrp {
 306                         fsl,pins = <
 307                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 308                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 309                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 310                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 311                         >;
 312                 };
 313
 314                 pinctrl_audmux: audmuxgrp {
 315                         fsl,pins = <
 316                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 317                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 318                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 319                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 320                         >;
 321                 };
 322
 323                 pinctrl_disp0_1: disp0grp-1 {
 324                         fsl,pins = <
 325                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 326                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 327                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 328                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 329                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 330                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 331                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 332                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 333                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 334                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 335                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 336                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 337                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 338                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 339                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 340                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 341                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 342                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 343                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 344                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 345                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 346                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 347                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 348                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 349                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 350                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 351                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 352                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 353                         >;
 354                 };
 355
 356                 pinctrl_disp0_2: disp0grp-2 {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 359                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 360                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 361                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 362                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 363                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 364                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 365                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 366                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 367                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 368                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 369                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 370                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 371                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 372                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 373                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 374                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 375                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 376                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 377                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 378                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 379                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 380                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 381                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 382                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 383                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 384                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 385                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 386                         >;
 387                 };
 388
 389                 pinctrl_ecspi1: ecspi1grp {
 390                         fsl,pins = <
 391                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 392                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 393                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 394                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 395                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 396                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 397                         >;
 398                 };
 399
 400                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 401                         fsl,pins = <
 402                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 403                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 404                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 405                         >;
 406                 };
 407
 408                 pinctrl_enet: enetgrp {
 409                         fsl,pins = <
 410                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 411                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 412                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 413                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 414                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 415                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 416                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 417                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 418                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 419                         >;
 420                 };
 421
 422                 pinctrl_etnphy_power: etnphy-pwrgrp {
 423                         fsl,pins = <
 424                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 425                         >;
 426                 };
 427
 428                 pinctrl_flexcan1: flexcan1grp {
 429                         fsl,pins = <
 430                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 431                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 432                         >;
 433                 };
 434
 435                 pinctrl_flexcan2: flexcan2grp {
 436                         fsl,pins = <
 437                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 438                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 439                         >;
 440                 };
 441
 442                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 443                         fsl,pins = <
 444                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 445                         >;
 446                 };
 447
 448                 pinctrl_gpmi_nand: gpminandgrp {
 449                         fsl,pins = <
 450                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 451                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 452                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 453                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 454                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 455                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 456                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 457                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 458                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 459                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 460                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 461                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 462                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 463                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 464                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 465                         >;
 466                 };
 467
 468                 pinctrl_i2c1: i2c1grp {
 469                         fsl,pins = <
 470                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 471                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 472                         >;
 473                 };
 474
 475                 pinctrl_i2c3: i2c3grp {
 476                         fsl,pins = <
 477                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 478                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 479                         >;
 480                 };
 481
 482                 pinctrl_kpp: kppgrp {
 483                         fsl,pins = <
 484                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 485                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 486                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 487                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 488                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 489                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 490                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 491                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 492                         >;
 493                 };
 494
 495                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
 496                         fsl,pins = <
 497                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 498                         >;
 499                 };
 500
 501                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
 502                         fsl,pins = <
 503                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 504                         >;
 505                 };
 506
 507                 pinctrl_pwm1: pwm1grp {
 508                         fsl,pins = <
 509                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 510                         >;
 511                 };
 512
 513                 pinctrl_pwm2: pwm2grp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 516                         >;
 517                 };
 518
 519                 pinctrl_tsc2007: tsc2007grp {
 520                         fsl,pins = <
 521                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 522                         >;
 523                 };
 524
 525                 pinctrl_uart1: uart1grp {
 526                         fsl,pins = <
 527                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 528                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 529                         >;
 530                 };
 531
 532                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 533                         fsl,pins = <
 534                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 535                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 536                         >;
 537                 };
 538
 539                 pinctrl_uart2: uart2grp {
 540                         fsl,pins = <
 541                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 542                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 543                         >;
 544                 };
 545
 546                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 547                         fsl,pins = <
 548                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 549                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 550                         >;
 551                 };
 552
 553                 pinctrl_uart3: uart3grp {
 554                         fsl,pins = <
 555                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 556                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 557                         >;
 558                 };
 559
 560                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 561                         fsl,pins = <
 562                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 563                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 564                         >;
 565                 };
 566
 567                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 568                         fsl,pins = <
 569                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 570                         >;
 571                 };
 572
 573                 pinctrl_usbotg: usbotggrp {
 574                         fsl,pins = <
 575                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 576                         >;
 577                 };
 578
 579                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 580                         fsl,pins = <
 581                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 582                         >;
 583                 };
 584
 585                 pinctrl_usdhc1: usdhc1grp {
 586                         fsl,pins = <
 587                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 588                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 589                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 590                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 591                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 592                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 593                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 594                         >;
 595                 };
 596
 597                 pinctrl_usdhc2: usdhc2grp {
 598                         fsl,pins = <
 599                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 600                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 601                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 602                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 603                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 604                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 605                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 606                         >;
 607                 };
 608         };
 609 };
 610
 611 &kpp {
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&pinctrl_kpp>;
 614         /* sample keymap */
 615         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 616         linux,keymap = <
 617                 0x06060074 /* MATRIX_KEY(6, 6, 116) KEY_POWER */
 618                 0x06070052 /* MATRIX_KEY(6, 7, 82) KEY_KP0 */
 619                 0x0602004f /* MATRIX_KEY(6, 2, 79) KEY_KP1 */
 620                 0x06030050 /* MATRIX_KEY(6, 3, 80) KEY_KP2 */
 621                 0x07060051 /* MATRIX_KEY(7, 6, 81) KEY_KP3 */
 622                 0x0707004b /* MATRIX_KEY(7, 7, 75) KEY_KP4 */
 623                 0x0702004c /* MATRIX_KEY(7, 2, 76) KEY_KP5 */
 624                 0x0703004d /* MATRIX_KEY(7, 3, 77) KEY_KP6 */
 625                 0x02060047 /* MATRIX_KEY(2, 6, 71) KEY_KP7 */
 626                 0x02070048 /* MATRIX_KEY(2, 7, 72) KEY_KP8 */
 627                 0x02020049 /* MATRIX_KEY(2, 2, 73) KEY_KP9 */
 628         >;
 629 };
 630
 631 &pwm1 {
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&pinctrl_pwm1>;
 634         #pwm-cells = <2>;
 635         status = "disabled";
 636 };
 637
 638 &pwm2 {
 639         pinctrl-names = "default";
 640         pinctrl-0 = <&pinctrl_pwm2>;
 641         #pwm-cells = <2>;
 642         status = "okay";
 643 };
 644
 645 &ssi1 {
 646         fsl,mode = "i2s-slave";
 647         status = "okay";
 648 };
 649
 650 &uart1 {
 651         pinctrl-names = "default";
 652         pinctrl-0 = <&pinctrl_uart1>;
 653         status = "okay";
 654 };
 655
 656 &uart2 {
 657         pinctrl-names = "default";
 658         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 659         status = "okay";
 660 };
 661
 662 &uart3 {
 663         pinctrl-names = "default";
 664         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 665         status = "okay";
 666 };
 667
 668 &usbh1 {
 669         vbus-supply = <&reg_usbh1_vbus>;
 670         dr_mode = "host";
 671         disable-over-current;
 672         status = "okay";
 673 };
 674
 675 &usbotg {
 676         vbus-supply = <&reg_usbotg_vbus>;
 677         pinctrl-names = "default";
 678         pinctrl-0 = <&pinctrl_usbotg>;
 679         dr_mode = "peripheral";
 680         disable-over-current;
 681         status = "okay";
 682 };
 683
 684 &usdhc1 {
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&pinctrl_usdhc1>;
 687         bus-width = <4>;
 688         no-1-8-v;
 689         cd-gpios = <&gpio7 2 0>;
 690         fsl,wp-controller;
 691         status = "okay";
 692 };
 693
 694 &usdhc2 {
 695         pinctrl-names = "default";
 696         pinctrl-0 = <&pinctrl_usdhc2>;
 697         bus-width = <4>;
 698         no-1-8-v;
 699         cd-gpios = <&gpio7 3 0>;
 700         fsl,wp-controller;
 701         status = "okay";
 702 };