arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         aliases {
  17                 can0 = &can2;
  18                 can1 = &can1;
  19                 display = &display;
  20                 ethernet0 = &fec;
  21                 lcdif_23bit_pins_a = &tx6_pinctrl_disp0_1;
  22                 lcdif_24bit_pins_a = &tx6_pinctrl_disp0_2;
  23                 lvds0 = &lvds0;
  24                 lvds1 = &lvds1;
  25                 pwm0 = &pwm1;
  26                 pwm1 = &pwm2;
  27                 reg_can_xcvr = &reg_can_xcvr;
  28                 stk5led = &user_led;
  29                 usbotg = &usbotg;
  30                 sdhc0 = &usdhc1;
  31                 sdhc1 = &usdhc2;
  32         };
  33
  34         memory {
  35                 reg = <0 0>; /* will be filled by U-Boot */
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 mclk: codec_clock {
  42                         compatible = "fixed-clock";
  43                         reg = <0>;
  44                         #clock-cells = <0>;
  45                         clock-frequency = <27000000>;
  46                 };
  47         };
  48
  49         backlight: backlight@0 {
  50                 compatible = "pwm-backlight";
  51                 pwms = <&pwm2 0 500000>;
  52                 power-supply = <&reg_3v3>;
  53                 /*
  54                  * a poor man's way to create an inverse 1:1 relationship
  55                  * between the PWM value and the actual duty cycle
  56                  */
  57                 brightness-levels = <100
  58                                       99 98 97 96 95 94 93 92 91 90
  59                                       89 88 87 86 85 84 83 82 81 80
  60                                       79 78 77 76 75 74 73 72 71 70
  61                                       69 68 67 66 65 64 63 62 61 60
  62                                       59 58 57 56 55 54 53 52 51 50
  63                                       49 48 47 46 45 44 43 42 41 40
  64                                       39 38 37 36 35 34 33 32 31 30
  65                                       29 28 27 26 25 24 23 22 21 20
  66                                       19 18 17 16 15 14 13 12 11 10
  67                                        9  8  7  6  5  4  3  2  1  0>;
  68                 default-brightness-level = <50>;
  69         };
  70
  71         backlight@1 {
  72                 compatible = "pwm-backlight";
  73                 pwms = <&pwm1 0 500000>;
  74                 power-supply = <&reg_3v3>;
  75                 /*
  76                  * a poor man's way to create a 1:1 relationship between
  77                  * the PWM value and the actual duty cycle
  78                  */
  79                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  80                                      10 11 12 13 14 15 16 17 18 19
  81                                      20 21 22 23 24 25 26 27 28 29
  82                                      30 31 32 33 34 35 36 37 38 39
  83                                      40 41 42 43 44 45 46 47 48 49
  84                                      50 51 52 53 54 55 56 57 58 59
  85                                      60 61 62 63 64 65 66 67 68 69
  86                                      70 71 72 73 74 75 76 77 78 79
  87                                      80 81 82 83 84 85 86 87 88 89
  88                                      90 91 92 93 94 95 96 97 98 99
  89                                     100>;
  90                 default-brightness-level = <50>;
  91                 status = "disabled";
  92         };
  93
  94         display: display@di0 {
  95                 compatible = "fsl,imx-parallel-display";
  96                 crtcs = <&ipu1 0>;
  97                 interface-pix-fmt = "rgb24";
  98                 pinctrl-names = "default";
  99                 pinctrl-0 = <&tx6_pinctrl_disp0_1>;
 100                 status = "okay";
 101
 102                 display-timings {
 103                         VGA {
 104                                 clock-frequency = <25200000>;
 105                                 hactive = <640>;
 106                                 vactive = <480>;
 107                                 hback-porch = <48>;
 108                                 hsync-len = <96>;
 109                                 hfront-porch = <16>;
 110                                 vback-porch = <31>;
 111                                 vsync-len = <2>;
 112                                 vfront-porch = <12>;
 113                                 hsync-active = <0>;
 114                                 vsync-active = <0>;
 115                                 de-active = <1>;
 116                                 pixelclk-active = <0>;
 117                         };
 118
 119                         ETV570 {
 120                                 clock-frequency = <25200000>;
 121                                 hactive = <640>;
 122                                 vactive = <480>;
 123                                 hback-porch = <114>;
 124                                 hsync-len = <30>;
 125                                 hfront-porch = <16>;
 126                                 vback-porch = <32>;
 127                                 vsync-len = <3>;
 128                                 vfront-porch = <10>;
 129                                 hsync-active = <0>;
 130                                 vsync-active = <0>;
 131                                 de-active = <1>;
 132                                 pixelclk-active = <0>;
 133                         };
 134
 135                         ET0350 {
 136                                 clock-frequency = <6413760>;
 137                                 hactive = <320>;
 138                                 vactive = <240>;
 139                                 hback-porch = <34>;
 140                                 hsync-len = <34>;
 141                                 hfront-porch = <20>;
 142                                 vback-porch = <15>;
 143                                 vsync-len = <3>;
 144                                 vfront-porch = <4>;
 145                                 hsync-active = <0>;
 146                                 vsync-active = <0>;
 147                                 de-active = <1>;
 148                                 pixelclk-active = <0>;
 149                         };
 150
 151                         ET0430 {
 152                                 clock-frequency = <9009000>;
 153                                 hactive = <480>;
 154                                 vactive = <272>;
 155                                 hback-porch = <2>;
 156                                 hsync-len = <41>;
 157                                 hfront-porch = <2>;
 158                                 vback-porch = <2>;
 159                                 vsync-len = <10>;
 160                                 vfront-porch = <2>;
 161                                 hsync-active = <0>;
 162                                 vsync-active = <0>;
 163                                 de-active = <1>;
 164                                 pixelclk-active = <1>;
 165                         };
 166
 167                         ET0500 {
 168                                 clock-frequency = <33264000>;
 169                                 hactive = <800>;
 170                                 vactive = <480>;
 171                                 hback-porch = <88>;
 172                                 hsync-len = <128>;
 173                                 hfront-porch = <40>;
 174                                 vback-porch = <33>;
 175                                 vsync-len = <2>;
 176                                 vfront-porch = <10>;
 177                                 hsync-active = <0>;
 178                                 vsync-active = <0>;
 179                                 de-active = <1>;
 180                                 pixelclk-active = <0>;
 181                         };
 182
 183                         ET0700 { /* same as ET0500 */
 184                                 clock-frequency = <33264000>;
 185                                 hactive = <800>;
 186                                 vactive = <480>;
 187                                 hback-porch = <88>;
 188                                 hsync-len = <128>;
 189                                 hfront-porch = <40>;
 190                                 vback-porch = <33>;
 191                                 vsync-len = <2>;
 192                                 vfront-porch = <10>;
 193                                 hsync-active = <0>;
 194                                 vsync-active = <0>;
 195                                 de-active = <1>;
 196                                 pixelclk-active = <0>;
 197                         };
 198
 199                         ETQ570 {
 200                                 clock-frequency = <6596040>;
 201                                 hactive = <320>;
 202                                 vactive = <240>;
 203                                 hback-porch = <38>;
 204                                 hsync-len = <30>;
 205                                 hfront-porch = <30>;
 206                                 vback-porch = <16>;
 207                                 vsync-len = <3>;
 208                                 vfront-porch = <4>;
 209                                 hsync-active = <0>;
 210                                 vsync-active = <0>;
 211                                 de-active = <1>;
 212                                 pixelclk-active = <0>;
 213                         };
 214                 };
 215         };
 216
 217         gpio-keys {
 218                 compatible = "gpio-keys";
 219
 220                 power {
 221                         label = "Power Button";
 222                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 223                         linux,code = <KEY_POWER>;
 224                         gpio-key,wakeup;
 225                 };
 226         };
 227
 228         leds {
 229                 compatible = "gpio-leds";
 230
 231                 user_led: user {
 232                         label = "Heartbeat";
 233                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
 234                         linux,default-trigger = "heartbeat";
 235                 };
 236         };
 237
 238         regulators {
 239                 compatible = "simple-bus";
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242
 243                 reg_3v3_etn: regulator@0 {
 244                         compatible = "regulator-fixed";
 245                         reg = <0>;
 246                         regulator-name = "3V3_ETN";
 247                         regulator-min-microvolt = <3300000>;
 248                         regulator-max-microvolt = <3300000>;
 249                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 250                         enable-active-high;
 251                 };
 252
 253                 reg_2v5: regulator@1 {
 254                         compatible = "regulator-fixed";
 255                         reg = <1>;
 256                         regulator-name = "2V5";
 257                         regulator-min-microvolt = <2500000>;
 258                         regulator-max-microvolt = <2500000>;
 259                         regulator-always-on;
 260                 };
 261
 262                 reg_3v3: regulator@2 {
 263                         compatible = "regulator-fixed";
 264                         reg = <2>;
 265                         regulator-name = "3V3";
 266                         regulator-min-microvolt = <3300000>;
 267                         regulator-max-microvolt = <3300000>;
 268                         regulator-always-on;
 269                 };
 270
 271                 reg_can_xcvr: regulator@3 {
 272                         compatible = "regulator-fixed";
 273                         reg = <3>;
 274                         regulator-name = "CAN XCVR";
 275                         regulator-min-microvolt = <3300000>;
 276                         regulator-max-microvolt = <3300000>;
 277                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 278                         enable-active-low;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_tx6qdl_flexcan_xcvr>;
 281                 };
 282
 283                 reg_lcd_pwr0: regulator@4 {
 284                         compatible = "regulator-fixed";
 285                         reg = <4>;
 286                         regulator-name = "LCD0 POWER";
 287                         regulator-min-microvolt = <3300000>;
 288                         regulator-max-microvolt = <3300000>;
 289                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 290                         enable-active-high;
 291                 };
 292
 293                 reg_lcd_pwr1: regulator@5 {
 294                         compatible = "regulator-fixed";
 295                         reg = <5>;
 296                         regulator-name = "LCD1 POWER";
 297                         regulator-min-microvolt = <3300000>;
 298                         regulator-max-microvolt = <3300000>;
 299                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 300                         enable-active-high;
 301                 };
 302
 303                 reg_lcd_reset: regulator@6 {
 304                         compatible = "regulator-fixed";
 305                         reg = <6>;
 306                         regulator-name = "LCD RESET";
 307                         regulator-min-microvolt = <3300000>;
 308                         regulator-max-microvolt = <3300000>;
 309                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 310                         startup-delay-us = <300000>;
 311                         enable-active-high;
 312                         regulator-always-on;
 313                 };
 314
 315                 reg_usbh1_vbus: regulator@7 {
 316                         compatible = "regulator-fixed";
 317                         reg = <7>;
 318                         regulator-name = "usbh1_vbus";
 319                         regulator-min-microvolt = <5000000>;
 320                         regulator-max-microvolt = <5000000>;
 321                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 322                         enable-active-high;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_tx6_usbh1_vbus>;
 325                 };
 326
 327                 reg_usbotg_vbus: regulator@8 {
 328                         compatible = "regulator-fixed";
 329                         reg = <8>;
 330                         regulator-name = "usbotg_vbus";
 331                         regulator-min-microvolt = <5000000>;
 332                         regulator-max-microvolt = <5000000>;
 333                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 334                         enable-active-high;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&pinctrl_tx6_usbotg_vbus>;
 337                 };
 338         };
 339
 340         sound {
 341                 compatible = "fsl,imx6qdl-tx6qdl-sgtl5000",
 342                              "fsl,imx-audio-sgtl5000";
 343                 model = "sgtl5000-audio";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&pinctrl_audmux_5>;
 346                 ssi-controller = <&ssi1>;
 347                 audio-codec = <&sgtl5000>;
 348                 audio-routing =
 349                         "MIC_IN", "Mic Jack",
 350                         "Mic Jack", "Mic Bias",
 351                         "Headphone Jack", "HP_OUT";
 352                 mux-int-port = <1>;
 353                 mux-ext-port = <5>;
 354         };
 355 };
 356
 357 &audmux {
 358         status = "okay";
 359 };
 360
 361 &can1 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_flexcan1_3>;
 364         xceiver-supply = <&reg_can_xcvr>;
 365
 366         status = "okay";
 367 };
 368
 369 &can2 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_flexcan2_1>;
 372         xceiver-supply = <&reg_can_xcvr>;
 373
 374         status = "okay";
 375 };
 376
 377 &fec {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&pinctrl_enet_4>;
 380         phy-mode = "rmii";
 381         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 382         phy-supply = <&reg_3v3_etn>;
 383         status = "okay";
 384 };
 385
 386 &gpmi {
 387         pinctrl-names = "default";
 388         pinctrl-0 = <&pinctrl_tx6_gpmi_nand>;
 389         nand-on-flash-bbt;
 390         status = "okay";
 391 };
 392
 393 &i2c1 {
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_i2c1_1>;
 396         clock-frequency = <400000>;
 397         status = "okay";
 398
 399         ds1339: rtc@68 {
 400                 compatible = "dallas,ds1339";
 401                 reg = <0x68>;
 402         };
 403 };
 404
 405 &i2c3 {
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_i2c3_2>;
 408         clock-frequency = <400000>;
 409         status = "okay";
 410
 411         touchscreen: tsc2007@48 {
 412                 compatible = "ti,tsc2007";
 413                 reg = <0x48>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&pinctrl_tsc2007_1>;
 416                 interrupt-parent = <&gpio3>;
 417                 interrupts = <26 0>;
 418                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 419                 ti,x-plate-ohms = <660>;
 420                 linux,wakeup;
 421         };
 422
 423         polytouch: edt-ft5x06@38 {
 424                 compatible = "edt,edt-ft5x06";
 425                 reg = <0x38>;
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
 428                 interrupt-parent = <&gpio6>;
 429                 interrupts = <15 0>;
 430                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 431                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 432         };
 433
 434         sgtl5000: sgtl5000@0a {
 435                 compatible = "fsl,sgtl5000";
 436                 reg = <0x0a>;
 437                 VDDA-supply = <&reg_2v5>;
 438                 VDDIO-supply = <&reg_3v3>;
 439                 clocks = <&mclk>;
 440         };
 441 };
 442
 443 &iomuxc {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_hog>;
 446
 447         display {
 448                 tx6_pinctrl_disp0_1: disp0grp-1 {
 449                         fsl,pins = <
 450                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 451                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 452                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 453                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 454                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 455                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 456                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 457                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 458                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 459                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 460                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 461                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 462                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 463                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 464                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 465                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 466                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 467                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 468                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 469                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 470                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 471                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 472                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 473                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 474                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 475                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 476                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 477                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 478                         >;
 479                 };
 480
 481                 tx6_pinctrl_disp0_2: disp0grp-2 {
 482                         fsl,pins = <
 483                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 484                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 485                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 486                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 487                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 488                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 489                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 490                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 491                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 492                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 493                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 494                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 495                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 496                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 497                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 498                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 499                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 500                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 501                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 502                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 503                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 504                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 505                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 506                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 507                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 508                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 509                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 510                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 511                         >;
 512                 };
 513         };
 514
 515         flexcan {
 516                 pinctrl_tx6qdl_flexcan_xcvr: flexcan-xcvrgrp-1 {
 517                         fsl,pins = <
 518                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
 519                         >;
 520                 };
 521         };
 522
 523         hog {
 524                 pinctrl_hog: hoggrp {
 525                         fsl,pins = <
 526                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
 527                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
 528                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
 529                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT
 530                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* SD1 CD */
 531                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* SD2 CD */
 532                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
 533                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
 534                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
 535                         >;
 536                 };
 537         };
 538
 539         kpp {
 540                 pinctrl_kpp: kppgrp {
 541                         fsl,pins = <
 542                                 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
 543                                 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
 544                                 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
 545                                 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
 546
 547                                 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
 548                                 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
 549                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
 550                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
 551                         >;
 552                 };
 553         };
 554
 555         nand {
 556                 pinctrl_tx6_gpmi_nand: tx6-gpmi-nand {
 557                         fsl,pins = <
 558                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 559                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 560                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 561                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 562                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 563                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 564                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 565                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 566                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 567                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 568                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 569                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 570                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 571                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 572                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 573                         >;
 574                 };
 575         };
 576
 577         touchpanel {
 578                 pinctrl_tsc2007_1: tsc2007grp-1 {
 579                         fsl,pins = <
 580                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
 581                         >;
 582                 };
 583
 584                 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
 585                         fsl,pins = <
 586                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
 587                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22   0x1b0b0 /* Reset */
 588                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21   0x1b0b0 /* Wake */
 589                         >;
 590                 };
 591         };
 592
 593         usbh1 {
 594                 pinctrl_tx6_usbh1_vbus: tx6-usbh1-vbusgrp {
 595                         fsl,pins = <
 596                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
 597                         >;
 598                 };
 599         };
 600
 601         usbotg {
 602                 pinctrl_tx6_usbotg: tx6-usbotggrp {
 603                         fsl,pins = <
 604                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
 605                         >;
 606                 };
 607
 608                 pinctrl_tx6_usbotg_vbus: tx6-usbotg-vbusgrp {
 609                         fsl,pins = <
 610                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
 611                         >;
 612                 };
 613         };
 614 };
 615
 616 &kpp {
 617         pinctrl-names = "default";
 618         pinctrl-0 = <&pinctrl_kpp>;
 619         /* sample keymap */
 620         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 621         linux,keymap = <
 622                 0x06060074 /* row 6, col 6, KEY_POWER */
 623                 0x06070052 /* row 6, col 7, KEY_KP0 */
 624                 0x0602004f /* row 6, col 2, KEY_KP1 */
 625                 0x06030050 /* row 6, col 3, KEY_KP2 */
 626                 0x07060051 /* row 7, col 6, KEY_KP3 */
 627                 0x0707004b /* row 7, col 7, KEY_KP4 */
 628                 0x0702004c /* row 7, col 2, KEY_KP5 */
 629                 0x0703004d /* row 7, col 3, KEY_KP6 */
 630                 0x02060047 /* row 2, col 6, KEY_KP7 */
 631                 0x02070048 /* row 2, col 7, KEY_KP8 */
 632                 0x02020049 /* row 2, col 2, KEY_KP9 */
 633         >;
 634 };
 635
 636 &ldb {
 637         status = "okay";
 638
 639         lvds0: lvds-channel@0 {
 640                 fsl,data-mapping = "spwg";
 641                 fsl,data-width = <18>;
 642                 status = "okay";
 643
 644                 display-timings {
 645                         native-mode = <&lvds_timing0>;
 646                         lvds_timing0: hsd100pxn1 {
 647                                 clock-frequency = <65000000>;
 648                                 hactive = <1024>;
 649                                 vactive = <768>;
 650                                 hback-porch = <220>;
 651                                 hfront-porch = <40>;
 652                                 vback-porch = <21>;
 653                                 vfront-porch = <7>;
 654                                 hsync-len = <60>;
 655                                 vsync-len = <10>;
 656                         };
 657                 };
 658         };
 659
 660         lvds1: lvds-channel@1 {
 661                 fsl,data-mapping = "spwg";
 662                 fsl,data-width = <18>;
 663                 status = "okay";
 664
 665                 display-timings {
 666                         native-mode = <&lvds_timing1>;
 667                         lvds_timing1: hsd100pxn1 {
 668                                 clock-frequency = <65000000>;
 669                                 hactive = <1024>;
 670                                 vactive = <768>;
 671                                 hback-porch = <220>;
 672                                 hfront-porch = <40>;
 673                                 vback-porch = <21>;
 674                                 vfront-porch = <7>;
 675                                 hsync-len = <60>;
 676                                 vsync-len = <10>;
 677                         };
 678                 };
 679         };
 680 };
 681
 682 &pwm1 {
 683         pinctrl-names = "default";
 684         pinctrl-0 = <&pinctrl_pwm1_2>;
 685         status = "okay";
 686 };
 687
 688 &pwm2 {
 689         pinctrl-names = "default";
 690         pinctrl-0 = <&pinctrl_pwm2_1>;
 691         status = "okay";
 692 };
 693
 694 &ssi1 {
 695         fsl,mode = "i2s-slave";
 696         status = "okay";
 697 };
 698
 699 &uart1 {
 700         pinctrl-names = "default";
 701         pinctrl-0 = <&pinctrl_uart1_2>;
 702         status = "okay";
 703 };
 704
 705 &uart2 {
 706         pinctrl-names = "default";
 707         pinctrl-0 = <&pinctrl_uart2_3 &pinctrl_uart2_rtscts_3>;
 708         status = "okay";
 709 };
 710
 711 &uart3 {
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&pinctrl_uart3_3 &pinctrl_uart3_rtscts_3>;
 714         status = "okay";
 715 };
 716
 717 &usbh1 {
 718         vbus-supply = <&reg_usbh1_vbus>;
 719         dr_mode = "host";
 720         disable-over-current;
 721         status = "okay";
 722 };
 723
 724 &usbotg {
 725         vbus-supply = <&reg_usbotg_vbus>;
 726         pinctrl-names = "default";
 727         pinctrl-0 = <&pinctrl_tx6_usbotg>;
 728         dr_mode = "peripheral";
 729         disable-over-current;
 730         status = "okay";
 731 };
 732
 733 &usdhc1 {
 734         pinctrl-names = "default";
 735         pinctrl-0 = <&pinctrl_usdhc1_2>;
 736         cd-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
 737         status = "okay";
 738 };
 739
 740 &usdhc2 {
 741         pinctrl-names = "default";
 742         pinctrl-0 = <&pinctrl_usdhc2_2>;
 743         cd-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
 744         status = "okay";
 745 };