arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/pwm/pwm.h>
  15
  16 / {
  17         aliases {
  18                 can0 = &can2;
  19                 can1 = &can1;
  20                 ethernet0 = &fec;
  21                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  22                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  23                 pwm0 = &pwm1;
  24                 pwm1 = &pwm2;
  25                 reg_can_xcvr = &reg_can_xcvr;
  26                 stk5led = &user_led;
  27                 usbotg = &usbotg;
  28                 sdhc0 = &usdhc1;
  29                 sdhc1 = &usdhc2;
  30         };
  31
  32         memory {
  33                 reg = <0 0>; /* will be filled by U-Boot */
  34         };
  35
  36         clocks {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 mclk: clock@0 {
  40                         compatible = "fixed-clock";
  41                         reg = <0>;
  42                         #clock-cells = <0>;
  43                         clock-frequency = <27000000>;
  44                 };
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49
  50                 power {
  51                         label = "Power Button";
  52                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_POWER>;
  54                         gpio-key,wakeup;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60
  61                 user_led: user {
  62                         label = "Heartbeat";
  63                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         regulators {
  69                 compatible = "simple-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 reg_3v3_etn: regulator@0 {
  74                         compatible = "regulator-fixed";
  75                         reg = <0>;
  76                         regulator-name = "3V3_ETN";
  77                         regulator-min-microvolt = <3300000>;
  78                         regulator-max-microvolt = <3300000>;
  79                         pinctrl-names = "default";
  80                         pinctrl-0 = <&pinctrl_etnphy_power>;
  81                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  82                         enable-active-high;
  83                 };
  84
  85                 reg_2v5: regulator@1 {
  86                         compatible = "regulator-fixed";
  87                         reg = <1>;
  88                         regulator-name = "2V5";
  89                         regulator-min-microvolt = <2500000>;
  90                         regulator-max-microvolt = <2500000>;
  91                         regulator-always-on;
  92                 };
  93
  94                 reg_3v3: regulator@2 {
  95                         compatible = "regulator-fixed";
  96                         reg = <2>;
  97                         regulator-name = "3V3";
  98                         regulator-min-microvolt = <3300000>;
  99                         regulator-max-microvolt = <3300000>;
 100                         regulator-always-on;
 101                 };
 102
 103                 reg_can_xcvr: regulator@3 {
 104                         compatible = "regulator-fixed";
 105                         reg = <3>;
 106                         regulator-name = "CAN XCVR";
 107                         regulator-min-microvolt = <3300000>;
 108                         regulator-max-microvolt = <3300000>;
 109                         pinctrl-names = "default";
 110                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 111                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 112                         enable-active-low;
 113                 };
 114
 115                 reg_lcd0_pwr: regulator@4 {
 116                         compatible = "regulator-fixed";
 117                         reg = <4>;
 118                         regulator-name = "LCD0 POWER";
 119                         regulator-min-microvolt = <3300000>;
 120                         regulator-max-microvolt = <3300000>;
 121                         pinctrl-names = "default";
 122                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
 123                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 124                         enable-active-high;
 125                         status = "disabled";
 126                 };
 127
 128                 reg_lcd1_pwr: regulator@5 {
 129                         compatible = "regulator-fixed";
 130                         reg = <5>;
 131                         regulator-name = "LCD1 POWER";
 132                         regulator-min-microvolt = <3300000>;
 133                         regulator-max-microvolt = <3300000>;
 134                         pinctrl-names = "default";
 135                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
 136                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 137                         enable-active-high;
 138                         status = "disabled";
 139                 };
 140
 141                 reg_usbh1_vbus: regulator@6 {
 142                         compatible = "regulator-fixed";
 143                         reg = <6>;
 144                         regulator-name = "usbh1_vbus";
 145                         regulator-min-microvolt = <5000000>;
 146                         regulator-max-microvolt = <5000000>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 149                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 150                         enable-active-high;
 151                 };
 152
 153                 reg_usbotg_vbus: regulator@7 {
 154                         compatible = "regulator-fixed";
 155                         reg = <7>;
 156                         regulator-name = "usbotg_vbus";
 157                         regulator-min-microvolt = <5000000>;
 158                         regulator-max-microvolt = <5000000>;
 159                         pinctrl-names = "default";
 160                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 161                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 162                         enable-active-high;
 163                 };
 164         };
 165
 166         sound {
 167                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 168                              "fsl,imx-audio-sgtl5000";
 169                 model = "sgtl5000-audio";
 170                 pinctrl-names = "default";
 171                 pinctrl-0 = <&pinctrl_audmux>;
 172                 ssi-controller = <&ssi1>;
 173                 audio-codec = <&sgtl5000>;
 174                 audio-routing =
 175                         "MIC_IN", "Mic Jack",
 176                         "Mic Jack", "Mic Bias",
 177                         "Headphone Jack", "HP_OUT";
 178                 mux-int-port = <1>;
 179                 mux-ext-port = <5>;
 180         };
 181 };
 182
 183 &audmux {
 184         status = "okay";
 185 };
 186
 187 &can1 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_flexcan1>;
 190         xceiver-supply = <&reg_can_xcvr>;
 191         status = "okay";
 192 };
 193
 194 &can2 {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_flexcan2>;
 197         xceiver-supply = <&reg_can_xcvr>;
 198         status = "okay";
 199 };
 200
 201 &ecspi1 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_ecspi1>;
 204         fsl,spi-num-chipselects = <2>;
 205         cs-gpios = <
 206                 &gpio2 30 GPIO_ACTIVE_HIGH
 207                 &gpio3 19 GPIO_ACTIVE_HIGH
 208         >;
 209         status = "okay";
 210
 211         spidev0: spi@0 {
 212                 compatible = "spidev";
 213                 reg = <0>;
 214                 spi-max-frequency = <54000000>;
 215         };
 216
 217         spidev1: spi@1 {
 218                 compatible = "spidev";
 219                 reg = <1>;
 220                 spi-max-frequency = <54000000>;
 221         };
 222 };
 223
 224 &fec {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_enet>;
 227         phy-mode = "rmii";
 228         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 229         phy-supply = <&reg_3v3_etn>;
 230         status = "okay";
 231 };
 232
 233 &gpmi {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_gpmi_nand>;
 236         nand-on-flash-bbt;
 237         fsl,no-blockmark-swap;
 238         status = "okay";
 239 };
 240
 241 &i2c1 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_i2c1>;
 244         clock-frequency = <400000>;
 245         status = "okay";
 246
 247         ds1339: rtc@68 {
 248                 compatible = "dallas,ds1339";
 249                 reg = <0x68>;
 250         };
 251 };
 252
 253 &i2c3 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_i2c3>;
 256         clock-frequency = <400000>;
 257         status = "okay";
 258
 259         sgtl5000: sgtl5000@0a {
 260                 compatible = "fsl,sgtl5000";
 261                 reg = <0x0a>;
 262                 VDDA-supply = <&reg_2v5>;
 263                 VDDIO-supply = <&reg_3v3>;
 264                 clocks = <&mclk>;
 265         };
 266
 267         polytouch: edt-ft5x06@38 {
 268                 compatible = "edt,edt-ft5x06";
 269                 reg = <0x38>;
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 272                 interrupt-parent = <&gpio6>;
 273                 interrupts = <15 0>;
 274                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 275                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 276                 linux,wakeup;
 277         };
 278
 279         touchscreen: tsc2007@48 {
 280                 compatible = "ti,tsc2007";
 281                 reg = <0x48>;
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&pinctrl_tsc2007>;
 284                 interrupt-parent = <&gpio3>;
 285                 interrupts = <26 0>;
 286                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 287                 ti,x-plate-ohms = <660>;
 288                 linux,wakeup;
 289         };
 290 };
 291
 292 &iomuxc {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_hog>;
 295
 296         imx6qdl-tx6 {
 297                 pinctrl_hog: hoggrp {
 298                         fsl,pins = <
 299                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 300                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 301                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 302                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 303                         >;
 304                 };
 305
 306                 pinctrl_audmux: audmuxgrp {
 307                         fsl,pins = <
 308                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 309                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 310                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 311                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 312                         >;
 313                 };
 314
 315                 pinctrl_disp0_1: disp0grp-1 {
 316                         fsl,pins = <
 317                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 318                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 319                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 320                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 321                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 322                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 323                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 324                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 325                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 326                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 327                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 328                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 329                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 330                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 331                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 332                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 333                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 334                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 335                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 336                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 337                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 338                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 339                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 340                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 341                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 342                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 343                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 344                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 345                         >;
 346                 };
 347
 348                 pinctrl_disp0_2: disp0grp-2 {
 349                         fsl,pins = <
 350                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 351                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 352                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 353                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 354                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 355                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 356                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 357                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 358                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 359                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 360                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 361                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 362                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 363                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 364                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 365                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 366                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 367                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 368                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 369                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 370                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 371                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 372                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 373                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 374                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 375                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 376                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 377                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 378                         >;
 379                 };
 380
 381                 pinctrl_ecspi1: ecspi1grp {
 382                         fsl,pins = <
 383                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 384                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 385                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 386                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 387                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 388                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 389                         >;
 390                 };
 391
 392                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 393                         fsl,pins = <
 394                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 395                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 396                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 397                         >;
 398                 };
 399
 400                 pinctrl_enet: enetgrp {
 401                         fsl,pins = <
 402                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 403                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 404                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 405                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 406                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 407                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 408                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 409                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 410                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 411                         >;
 412                 };
 413
 414                 pinctrl_etnphy_power: etnphy-pwrgrp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 417                         >;
 418                 };
 419
 420                 pinctrl_flexcan1: flexcan1grp {
 421                         fsl,pins = <
 422                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 423                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 424                         >;
 425                 };
 426
 427                 pinctrl_flexcan2: flexcan2grp {
 428                         fsl,pins = <
 429                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 430                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 431                         >;
 432                 };
 433
 434                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 435                         fsl,pins = <
 436                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 437                         >;
 438                 };
 439
 440                 pinctrl_gpmi_nand: gpminandgrp {
 441                         fsl,pins = <
 442                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 443                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 444                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 445                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 446                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 447                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 448                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 449                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 450                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 451                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 452                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 453                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 454                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 455                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 456                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 457                         >;
 458                 };
 459
 460                 pinctrl_i2c1: i2c1grp {
 461                         fsl,pins = <
 462                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 463                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 464                         >;
 465                 };
 466
 467                 pinctrl_i2c3: i2c3grp {
 468                         fsl,pins = <
 469                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 470                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 471                         >;
 472                 };
 473
 474                 pinctrl_kpp: kppgrp {
 475                         fsl,pins = <
 476                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 477                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 478                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 479                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 480                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 481                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 482                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 483                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 484                         >;
 485                 };
 486
 487                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
 488                         fsl,pins = <
 489                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 490                         >;
 491                 };
 492
 493                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
 494                         fsl,pins = <
 495                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 496                         >;
 497                 };
 498
 499                 pinctrl_pwm1: pwm1grp {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 502                         >;
 503                 };
 504
 505                 pinctrl_pwm2: pwm2grp {
 506                         fsl,pins = <
 507                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 508                         >;
 509                 };
 510
 511                 pinctrl_tsc2007: tsc2007grp {
 512                         fsl,pins = <
 513                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 514                         >;
 515                 };
 516
 517                 pinctrl_uart1: uart1grp {
 518                         fsl,pins = <
 519                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 520                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 521                         >;
 522                 };
 523
 524                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 525                         fsl,pins = <
 526                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 527                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 528                         >;
 529                 };
 530
 531                 pinctrl_uart2: uart2grp {
 532                         fsl,pins = <
 533                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 534                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 535                         >;
 536                 };
 537
 538                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 539                         fsl,pins = <
 540                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 541                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 542                         >;
 543                 };
 544
 545                 pinctrl_uart3: uart3grp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 548                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 549                         >;
 550                 };
 551
 552                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 553                         fsl,pins = <
 554                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 555                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 556                         >;
 557                 };
 558
 559                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 560                         fsl,pins = <
 561                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 562                         >;
 563                 };
 564
 565                 pinctrl_usbotg: usbotggrp {
 566                         fsl,pins = <
 567                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 568                         >;
 569                 };
 570
 571                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 572                         fsl,pins = <
 573                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 574                         >;
 575                 };
 576
 577                 pinctrl_usdhc1: usdhc1grp {
 578                         fsl,pins = <
 579                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 580                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 581                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 582                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 583                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 584                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 585                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 586                         >;
 587                 };
 588
 589                 pinctrl_usdhc2: usdhc2grp {
 590                         fsl,pins = <
 591                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 592                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 593                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 594                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 595                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 596                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 597                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 598                         >;
 599                 };
 600         };
 601 };
 602
 603 &kpp {
 604         pinctrl-names = "default";
 605         pinctrl-0 = <&pinctrl_kpp>;
 606         /* sample keymap */
 607         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 608         linux,keymap = <
 609                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 610                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 611                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 612                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 613                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 614                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 615                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 616                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 617                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 618                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 619                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 620         >;
 621 };
 622
 623 &pwm1 {
 624         pinctrl-names = "default";
 625         pinctrl-0 = <&pinctrl_pwm1>;
 626         #pwm-cells = <3>;
 627         status = "disabled";
 628 };
 629
 630 &pwm2 {
 631         pinctrl-names = "default";
 632         pinctrl-0 = <&pinctrl_pwm2>;
 633         #pwm-cells = <3>;
 634         status = "okay";
 635 };
 636
 637 &ssi1 {
 638         fsl,mode = "i2s-slave";
 639         status = "okay";
 640 };
 641
 642 &uart1 {
 643         pinctrl-names = "default";
 644         pinctrl-0 = <&pinctrl_uart1>;
 645         status = "okay";
 646 };
 647
 648 &uart2 {
 649         pinctrl-names = "default";
 650         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 651         status = "okay";
 652 };
 653
 654 &uart3 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 657         status = "okay";
 658 };
 659
 660 &usbh1 {
 661         vbus-supply = <&reg_usbh1_vbus>;
 662         dr_mode = "host";
 663         disable-over-current;
 664         status = "okay";
 665 };
 666
 667 &usbotg {
 668         vbus-supply = <&reg_usbotg_vbus>;
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_usbotg>;
 671         dr_mode = "peripheral";
 672         disable-over-current;
 673         status = "okay";
 674 };
 675
 676 &usdhc1 {
 677         pinctrl-names = "default";
 678         pinctrl-0 = <&pinctrl_usdhc1>;
 679         bus-width = <4>;
 680         no-1-8-v;
 681         cd-gpios = <&gpio7 2 0>;
 682         fsl,wp-controller;
 683         status = "okay";
 684 };
 685
 686 &usdhc2 {
 687         pinctrl-names = "default";
 688         pinctrl-0 = <&pinctrl_usdhc2>;
 689         bus-width = <4>;
 690         no-1-8-v;
 691         cd-gpios = <&gpio7 3 0>;
 692         fsl,wp-controller;
 693         status = "okay";
 694 };