arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 ethernet0 = &fec;
  20                 can0 = &can1;
  21                 can1 = &can2;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 ipu0 = &ipu1;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 ckih1 {
  69                         compatible = "fsl,imx-ckih1", "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <24000000>;
  78                 };
  79         };
  80
  81         soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "simple-bus";
  85                 interrupt-parent = <&intc>;
  86                 ranges;
  87
  88                 dma_apbh: dma-apbh@00110000 {
  89                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  90                         reg = <0x00110000 0x2000>;
  91                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  95                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  96                         #dma-cells = <1>;
  97                         dma-channels = <4>;
  98                         clocks = <&clks 106>;
  99                 };
 100
 101                 gpmi: gpmi-nand@00112000 {
 102                         compatible = "fsl,imx6q-gpmi-nand";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 106                         reg-names = "gpmi-nand", "bch";
 107                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 108                         interrupt-names = "bch";
 109                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 110                                  <&clks 150>, <&clks 149>;
 111                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 112                                       "gpmi_bch_apb", "per1_bch";
 113                         dmas = <&dma_apbh 0>;
 114                         dma-names = "rx-tx";
 115                         status = "disabled";
 116                 };
 117
 118                 timer@00a00600 {
 119                         compatible = "arm,cortex-a9-twd-timer";
 120                         reg = <0x00a00600 0x20>;
 121                         interrupts = <1 13 0xf01>;
 122                         clocks = <&clks 15>;
 123                 };
 124
 125                 L2: l2-cache@00a02000 {
 126                         compatible = "arm,pl310-cache";
 127                         reg = <0x00a02000 0x1000>;
 128                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 129                         cache-unified;
 130                         cache-level = <2>;
 131                         arm,tag-latency = <4 2 3>;
 132                         arm,data-latency = <4 2 3>;
 133                 };
 134
 135                 pcie: pcie@0x01000000 {
 136                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 137                         reg = <0x01ffc000 0x4000>; /* DBI */
 138                         #address-cells = <3>;
 139                         #size-cells = <2>;
 140                         device_type = "pci";
 141                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 142                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 143                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 144                         num-lanes = <1>;
 145                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 146                         interrupt-names = "msi";
 147                         #interrupt-cells = <1>;
 148                         interrupt-map-mask = <0 0 0 0x7>;
 149                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 150                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 151                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 152                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 153                         clocks = <&clks 144>, <&clks 206>, <&clks 189>;
 154                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 155                         status = "disabled";
 156                 };
 157
 158                 pmu {
 159                         compatible = "arm,cortex-a9-pmu";
 160                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 161                 };
 162
 163                 aips-bus@02000000 { /* AIPS1 */
 164                         compatible = "fsl,aips-bus", "simple-bus";
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         reg = <0x02000000 0x100000>;
 168                         ranges;
 169
 170                         spba-bus@02000000 {
 171                                 compatible = "fsl,spba-bus", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0x02000000 0x40000>;
 175                                 ranges;
 176
 177                                 spdif: spdif@02004000 {
 178                                         compatible = "fsl,imx35-spdif";
 179                                         reg = <0x02004000 0x4000>;
 180                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 181                                         dmas = <&sdma 14 18 0>,
 182                                                <&sdma 15 18 0>;
 183                                         dma-names = "rx", "tx";
 184                                         clocks = <&clks 197>, <&clks 3>,
 185                                                  <&clks 197>, <&clks 107>,
 186                                                  <&clks 0>,   <&clks 118>,
 187                                                  <&clks 0>,  <&clks 139>,
 188                                                  <&clks 0>;
 189                                         clock-names = "core",  "rxtx0",
 190                                                       "rxtx1", "rxtx2",
 191                                                       "rxtx3", "rxtx4",
 192                                                       "rxtx5", "rxtx6",
 193                                                       "rxtx7";
 194                                         status = "disabled";
 195                                 };
 196
 197                                 ecspi1: ecspi@02008000 {
 198                                         #address-cells = <1>;
 199                                         #size-cells = <0>;
 200                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 201                                         reg = <0x02008000 0x4000>;
 202                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 203                                         clocks = <&clks 112>, <&clks 112>;
 204                                         clock-names = "ipg", "per";
 205                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 206                                         dma-names = "rx", "tx";
 207                                         status = "disabled";
 208                                 };
 209
 210                                 ecspi2: ecspi@0200c000 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 214                                         reg = <0x0200c000 0x4000>;
 215                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 216                                         clocks = <&clks 113>, <&clks 113>;
 217                                         clock-names = "ipg", "per";
 218                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 219                                         dma-names = "rx", "tx";
 220                                         status = "disabled";
 221                                 };
 222
 223                                 ecspi3: ecspi@02010000 {
 224                                         #address-cells = <1>;
 225                                         #size-cells = <0>;
 226                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 227                                         reg = <0x02010000 0x4000>;
 228                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 229                                         clocks = <&clks 114>, <&clks 114>;
 230                                         clock-names = "ipg", "per";
 231                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 232                                         dma-names = "rx", "tx";
 233                                         status = "disabled";
 234                                 };
 235
 236                                 ecspi4: ecspi@02014000 {
 237                                         #address-cells = <1>;
 238                                         #size-cells = <0>;
 239                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 240                                         reg = <0x02014000 0x4000>;
 241                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 242                                         clocks = <&clks 115>, <&clks 115>;
 243                                         clock-names = "ipg", "per";
 244                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 245                                         dma-names = "rx", "tx";
 246                                         status = "disabled";
 247                                 };
 248
 249                                 uart1: serial@02020000 {
 250                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 251                                         reg = <0x02020000 0x4000>;
 252                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks 160>, <&clks 161>;
 254                                         clock-names = "ipg", "per";
 255                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 256                                         dma-names = "rx", "tx";
 257                                         status = "disabled";
 258                                 };
 259
 260                                 esai: esai@02024000 {
 261                                         compatible = "fsl,imx6q-esai";
 262                                         reg = <0x02024000 0x4000>;
 263                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 264                                         clocks = <&clks 118>, <&clks 156>;
 265                                         clock-names = "core", "dma";
 266                                         fsl,esai-dma-events = <24 23>;
 267                                         fsl,flags = <1>;
 268                                         status = "disabled";
 269                                 };
 270
 271                                 ssi1: ssi@02028000 {
 272                                         compatible = "fsl,imx6q-ssi",
 273                                                         "fsl,imx51-ssi",
 274                                                         "fsl,imx21-ssi";
 275                                         reg = <0x02028000 0x4000>;
 276                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 277                                         clocks = <&clks 178>;
 278                                         dmas = <&sdma 37 1 0>,
 279                                                <&sdma 38 1 0>;
 280                                         dma-names = "rx", "tx";
 281                                         fsl,fifo-depth = <15>;
 282                                         fsl,ssi-dma-events = <38 37>;
 283                                         status = "disabled";
 284                                 };
 285
 286                                 ssi2: ssi@0202c000 {
 287                                         compatible = "fsl,imx6q-ssi",
 288                                                         "fsl,imx51-ssi",
 289                                                         "fsl,imx21-ssi";
 290                                         reg = <0x0202c000 0x4000>;
 291                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks 179>;
 293                                         dmas = <&sdma 41 1 0>,
 294                                                <&sdma 42 1 0>;
 295                                         dma-names = "rx", "tx";
 296                                         fsl,fifo-depth = <15>;
 297                                         fsl,ssi-dma-events = <42 41>;
 298                                         status = "disabled";
 299                                 };
 300
 301                                 ssi3: ssi@02030000 {
 302                                         compatible = "fsl,imx6q-ssi",
 303                                                         "fsl,imx51-ssi",
 304                                                         "fsl,imx21-ssi";
 305                                         reg = <0x02030000 0x4000>;
 306                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks 180>;
 308                                         dmas = <&sdma 45 1 0>,
 309                                                <&sdma 46 1 0>;
 310                                         dma-names = "rx", "tx";
 311                                         fsl,fifo-depth = <15>;
 312                                         fsl,ssi-dma-events = <46 45>;
 313                                         status = "disabled";
 314                                 };
 315
 316                                 asrc: asrc@02034000 {
 317                                         reg = <0x02034000 0x4000>;
 318                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 319                                 };
 320
 321                                 spba@0203c000 {
 322                                         reg = <0x0203c000 0x4000>;
 323                                 };
 324                         };
 325
 326                         vpu: vpu@02040000 {
 327                                 reg = <0x02040000 0x3c000>;
 328                                 reg-names = "vpu_regs";
 329                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 330                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 331                                 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
 332                                 clocks = <&clks 168>, <&clks 140>, <&clks 142>;
 333                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 334                                 iramsize = <0x21000>;
 335                                 iram = <&ocram>;
 336                                 resets = <&src 1>;
 337                                 pu-supply = <&reg_pu>;
 338                                 status = "disabled";
 339                         };
 340
 341                         aipstz@0207c000 { /* AIPSTZ1 */
 342                                 reg = <0x0207c000 0x4000>;
 343                         };
 344
 345                         pwm1: pwm@02080000 {
 346                                 #pwm-cells = <2>;
 347                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 348                                 reg = <0x02080000 0x4000>;
 349                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 350                                 clocks = <&clks 62>, <&clks 145>;
 351                                 clock-names = "ipg", "per";
 352                         };
 353
 354                         pwm2: pwm@02084000 {
 355                                 #pwm-cells = <2>;
 356                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02084000 0x4000>;
 358                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks 62>, <&clks 146>;
 360                                 clock-names = "ipg", "per";
 361                         };
 362
 363                         pwm3: pwm@02088000 {
 364                                 #pwm-cells = <2>;
 365                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 366                                 reg = <0x02088000 0x4000>;
 367                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks 62>, <&clks 147>;
 369                                 clock-names = "ipg", "per";
 370                         };
 371
 372                         pwm4: pwm@0208c000 {
 373                                 #pwm-cells = <2>;
 374                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 375                                 reg = <0x0208c000 0x4000>;
 376                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 377                                 clocks = <&clks 62>, <&clks 148>;
 378                                 clock-names = "ipg", "per";
 379                         };
 380
 381                         can1: flexcan@02090000 {
 382                                 compatible = "fsl,imx6q-flexcan";
 383                                 reg = <0x02090000 0x4000>;
 384                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 385                                 clocks = <&clks 108>, <&clks 109>;
 386                                 clock-names = "ipg", "per";
 387                                 status = "disabled";
 388                         };
 389
 390                         can2: flexcan@02094000 {
 391                                 compatible = "fsl,imx6q-flexcan";
 392                                 reg = <0x02094000 0x4000>;
 393                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 394                                 clocks = <&clks 110>, <&clks 111>;
 395                                 clock-names = "ipg", "per";
 396                                 status = "disabled";
 397                         };
 398
 399                         gpt: gpt@02098000 {
 400                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 401                                 reg = <0x02098000 0x4000>;
 402                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 403                                 clocks = <&clks 119>, <&clks 120>;
 404                                 clock-names = "ipg", "per";
 405                         };
 406
 407                         gpio1: gpio@0209c000 {
 408                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x0209c000 0x4000>;
 410                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 412                                 gpio-controller;
 413                                 #gpio-cells = <2>;
 414                                 interrupt-controller;
 415                                 #interrupt-cells = <2>;
 416                         };
 417
 418                         gpio2: gpio@020a0000 {
 419                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 420                                 reg = <0x020a0000 0x4000>;
 421                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 423                                 gpio-controller;
 424                                 #gpio-cells = <2>;
 425                                 interrupt-controller;
 426                                 #interrupt-cells = <2>;
 427                         };
 428
 429                         gpio3: gpio@020a4000 {
 430                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 431                                 reg = <0x020a4000 0x4000>;
 432                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 433                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 434                                 gpio-controller;
 435                                 #gpio-cells = <2>;
 436                                 interrupt-controller;
 437                                 #interrupt-cells = <2>;
 438                         };
 439
 440                         gpio4: gpio@020a8000 {
 441                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 442                                 reg = <0x020a8000 0x4000>;
 443                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 444                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 445                                 gpio-controller;
 446                                 #gpio-cells = <2>;
 447                                 interrupt-controller;
 448                                 #interrupt-cells = <2>;
 449                         };
 450
 451                         gpio5: gpio@020ac000 {
 452                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 453                                 reg = <0x020ac000 0x4000>;
 454                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                         };
 461
 462                         gpio6: gpio@020b0000 {
 463                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 464                                 reg = <0x020b0000 0x4000>;
 465                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 466                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 467                                 gpio-controller;
 468                                 #gpio-cells = <2>;
 469                                 interrupt-controller;
 470                                 #interrupt-cells = <2>;
 471                         };
 472
 473                         gpio7: gpio@020b4000 {
 474                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 475                                 reg = <0x020b4000 0x4000>;
 476                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 477                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 478                                 gpio-controller;
 479                                 #gpio-cells = <2>;
 480                                 interrupt-controller;
 481                                 #interrupt-cells = <2>;
 482                         };
 483
 484                         kpp: kpp@020b8000 {
 485                                 compatible = "fsl,imx6qdl-kpp", "fsl,imx21-kpp";
 486                                 reg = <0x020b8000 0x4000>;
 487                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 488                                 clocks = <&clks 0>;
 489                         };
 490
 491                         wdog1: wdog@020bc000 {
 492                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 493                                 reg = <0x020bc000 0x4000>;
 494                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks 0>;
 496                         };
 497
 498                         wdog2: wdog@020c0000 {
 499                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 500                                 reg = <0x020c0000 0x4000>;
 501                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks 0>;
 503                                 status = "disabled";
 504                         };
 505
 506                         clks: ccm@020c4000 {
 507                                 compatible = "fsl,imx6q-ccm";
 508                                 reg = <0x020c4000 0x4000>;
 509                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 511                                 #clock-cells = <1>;
 512                         };
 513
 514                         anatop: anatop@020c8000 {
 515                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 516                                 reg = <0x020c8000 0x1000>;
 517                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 519                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 520
 521                                 regulator-1p1@110 {
 522                                         compatible = "fsl,anatop-regulator";
 523                                         regulator-name = "vdd1p1";
 524                                         regulator-min-microvolt = <800000>;
 525                                         regulator-max-microvolt = <1375000>;
 526                                         regulator-always-on;
 527                                         anatop-reg-offset = <0x110>;
 528                                         anatop-vol-bit-shift = <8>;
 529                                         anatop-vol-bit-width = <5>;
 530                                         anatop-min-bit-val = <4>;
 531                                         anatop-min-voltage = <800000>;
 532                                         anatop-max-voltage = <1375000>;
 533                                 };
 534
 535                                 regulator-3p0@120 {
 536                                         compatible = "fsl,anatop-regulator";
 537                                         regulator-name = "vdd3p0";
 538                                         regulator-min-microvolt = <2800000>;
 539                                         regulator-max-microvolt = <3150000>;
 540                                         regulator-always-on;
 541                                         anatop-reg-offset = <0x120>;
 542                                         anatop-vol-bit-shift = <8>;
 543                                         anatop-vol-bit-width = <5>;
 544                                         anatop-min-bit-val = <0>;
 545                                         anatop-min-voltage = <2625000>;
 546                                         anatop-max-voltage = <3400000>;
 547                                 };
 548
 549                                 regulator-2p5@130 {
 550                                         compatible = "fsl,anatop-regulator";
 551                                         regulator-name = "vdd2p5";
 552                                         regulator-min-microvolt = <2000000>;
 553                                         regulator-max-microvolt = <2750000>;
 554                                         regulator-always-on;
 555                                         anatop-reg-offset = <0x130>;
 556                                         anatop-vol-bit-shift = <8>;
 557                                         anatop-vol-bit-width = <5>;
 558                                         anatop-min-bit-val = <0>;
 559                                         anatop-min-voltage = <2000000>;
 560                                         anatop-max-voltage = <2750000>;
 561                                 };
 562
 563                                 reg_arm: regulator-vddcore@140 {
 564                                         compatible = "fsl,anatop-regulator";
 565                                         regulator-name = "vddarm";
 566                                         regulator-min-microvolt = <725000>;
 567                                         regulator-max-microvolt = <1450000>;
 568                                         regulator-always-on;
 569                                         anatop-reg-offset = <0x140>;
 570                                         anatop-vol-bit-shift = <0>;
 571                                         anatop-vol-bit-width = <5>;
 572                                         anatop-delay-reg-offset = <0x170>;
 573                                         anatop-delay-bit-shift = <24>;
 574                                         anatop-delay-bit-width = <2>;
 575                                         anatop-min-bit-val = <1>;
 576                                         anatop-min-voltage = <725000>;
 577                                         anatop-max-voltage = <1450000>;
 578                                 };
 579
 580                                 reg_pu: regulator-vddpu@140 {
 581                                         compatible = "fsl,anatop-regulator";
 582                                         regulator-name = "vddpu";
 583                                         regulator-min-microvolt = <725000>;
 584                                         regulator-max-microvolt = <1450000>;
 585                                         regulator-always-on;
 586                                         anatop-reg-offset = <0x140>;
 587                                         anatop-vol-bit-shift = <9>;
 588                                         anatop-vol-bit-width = <5>;
 589                                         anatop-delay-reg-offset = <0x170>;
 590                                         anatop-delay-bit-shift = <26>;
 591                                         anatop-delay-bit-width = <2>;
 592                                         anatop-min-bit-val = <1>;
 593                                         anatop-min-voltage = <725000>;
 594                                         anatop-max-voltage = <1450000>;
 595                                 };
 596
 597                                 reg_soc: regulator-vddsoc@140 {
 598                                         compatible = "fsl,anatop-regulator";
 599                                         regulator-name = "vddsoc";
 600                                         regulator-min-microvolt = <725000>;
 601                                         regulator-max-microvolt = <1450000>;
 602                                         regulator-always-on;
 603                                         anatop-reg-offset = <0x140>;
 604                                         anatop-vol-bit-shift = <18>;
 605                                         anatop-vol-bit-width = <5>;
 606                                         anatop-delay-reg-offset = <0x170>;
 607                                         anatop-delay-bit-shift = <28>;
 608                                         anatop-delay-bit-width = <2>;
 609                                         anatop-min-bit-val = <1>;
 610                                         anatop-min-voltage = <725000>;
 611                                         anatop-max-voltage = <1450000>;
 612                                 };
 613                         };
 614
 615                         tempmon: tempmon {
 616                                 compatible = "fsl,imx6q-tempmon";
 617                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 618                                 fsl,tempmon = <&anatop>;
 619                                 fsl,tempmon-data = <&ocotp>;
 620                                 clocks = <&clks 172>;
 621                         };
 622
 623                         usbphy1: usbphy@020c9000 {
 624                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 625                                 reg = <0x020c9000 0x1000>;
 626                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clks 182>;
 628                                 fsl,anatop = <&anatop>;
 629                         };
 630
 631                         usbphy2: usbphy@020ca000 {
 632                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 633                                 reg = <0x020ca000 0x1000>;
 634                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clks 183>;
 636                                 fsl,anatop = <&anatop>;
 637                         };
 638
 639                         snvs@020cc000 {
 640                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 641                                 #address-cells = <1>;
 642                                 #size-cells = <1>;
 643                                 ranges = <0 0x020cc000 0x4000>;
 644
 645                                 snvs-rtc-lp@34 {
 646                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 647                                         reg = <0x34 0x58>;
 648                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 649                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 650                                 };
 651                         };
 652
 653                         epit1: epit@020d0000 { /* EPIT1 */
 654                                 reg = <0x020d0000 0x4000>;
 655                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 656                         };
 657
 658                         epit2: epit@020d4000 { /* EPIT2 */
 659                                 reg = <0x020d4000 0x4000>;
 660                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 661                         };
 662
 663                         src: src@020d8000 {
 664                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 665                                 reg = <0x020d8000 0x4000>;
 666                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 667                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 668                                 #reset-cells = <1>;
 669                         };
 670
 671                         gpc: gpc@020dc000 {
 672                                 compatible = "fsl,imx6q-gpc";
 673                                 reg = <0x020dc000 0x4000>;
 674                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 675                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 676                         };
 677
 678                         gpr: iomuxc-gpr@020e0000 {
 679                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 680                                 reg = <0x020e0000 0x38>;
 681                         };
 682
 683                         iomuxc: iomuxc@020e0000 {
 684                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 685                                 reg = <0x020e0000 0x4000>;
 686                         };
 687
 688                         ldb: ldb@020e0008 {
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 692                                 reg = <0x020e0000 0x4000>;
 693                                 clocks = <&clks 135>, <&clks 136>,
 694                                          <&clks 39>, <&clks 40>,
 695                                          <&clks 41>, <&clks 42>,
 696                                          <&clks 184>, <&clks 185>,
 697                                          <&clks 205>, <&clks 206>,
 698                                          <&clks 207>, <&clks 208>;
 699                                 clock-names = "ldb_di0", "ldb_di1",
 700                                               "ipu1_di0_sel", "ipu1_di1_sel",
 701                                               "ipu2_di0_sel", "ipu2_di1_sel",
 702                                               "di0_div_3_5", "di1_div_3_5",
 703                                               "di0_div_7", "di1_div_7",
 704                                               "di0_div_sel", "di1_div_sel";
 705                                 gpr = <&gpr>;
 706                                 status = "disabled";
 707
 708                                 lvds-channel@0 {
 709                                         #address-cells = <1>;
 710                                         #size-cells = <0>;
 711                                         reg = <0>;
 712                                         status = "disabled";
 713
 714                                         port@0 {
 715                                                 reg = <0>;
 716
 717                                                 lvds0_mux_0: endpoint {
 718                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 719                                                 };
 720                                         };
 721
 722                                         port@1 {
 723                                                 reg = <1>;
 724
 725                                                 lvds0_mux_1: endpoint {
 726                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 727                                                 };
 728                                         };
 729                                 };
 730
 731                                 lvds-channel@1 {
 732                                         #address-cells = <1>;
 733                                         #size-cells = <0>;
 734                                         reg = <1>;
 735                                         status = "disabled";
 736
 737                                         port@0 {
 738                                                 reg = <0>;
 739
 740                                                 lvds1_mux_0: endpoint {
 741                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 742                                                 };
 743                                         };
 744
 745                                         port@1 {
 746                                                 reg = <1>;
 747
 748                                                 lvds1_mux_1: endpoint {
 749                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 750                                                 };
 751                                         };
 752                                 };
 753                         };
 754
 755                         hdmi: hdmi@0120000 {
 756                                 #address-cells = <1>;
 757                                 #size-cells = <0>;
 758                                 reg = <0x00120000 0x9000>;
 759                                 interrupts = <0 115 0x04>;
 760                                 gpr = <&gpr>;
 761                                 clocks = <&clks 123>, <&clks 124>;
 762                                 clock-names = "iahb", "isfr";
 763                                 status = "disabled";
 764
 765                                 port@0 {
 766                                         reg = <0>;
 767
 768                                         hdmi_mux_0: endpoint {
 769                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 770                                         };
 771                                 };
 772
 773                                 port@1 {
 774                                         reg = <1>;
 775
 776                                         hdmi_mux_1: endpoint {
 777                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 778                                         };
 779                                 };
 780                         };
 781
 782                         dcic1: dcic@020e4000 {
 783                                 reg = <0x020e4000 0x4000>;
 784                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 785                         };
 786
 787                         dcic2: dcic@020e8000 {
 788                                 reg = <0x020e8000 0x4000>;
 789                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 790                         };
 791
 792                         sdma: sdma@020ec000 {
 793                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 794                                 reg = <0x020ec000 0x4000>;
 795                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 796                                 clocks = <&clks 155>, <&clks 155>;
 797                                 clock-names = "ipg", "ahb";
 798                                 #dma-cells = <3>;
 799                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 800                         };
 801                 };
 802
 803                 aips-bus@02100000 { /* AIPS2 */
 804                         compatible = "fsl,aips-bus", "simple-bus";
 805                         #address-cells = <1>;
 806                         #size-cells = <1>;
 807                         reg = <0x02100000 0x100000>;
 808                         ranges;
 809
 810                         caam@02100000 {
 811                                 reg = <0x02100000 0x40000>;
 812                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 813                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 814                         };
 815
 816                         aipstz@0217c000 { /* AIPSTZ2 */
 817                                 reg = <0x0217c000 0x4000>;
 818                         };
 819
 820                         usbotg: usb@02184000 {
 821                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 822                                 reg = <0x02184000 0x200>;
 823                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 824                                 clocks = <&clks 162>;
 825                                 fsl,usbphy = <&usbphy1>;
 826                                 fsl,usbmisc = <&usbmisc 0>;
 827                                 status = "disabled";
 828                         };
 829
 830                         usbh1: usb@02184200 {
 831                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 832                                 reg = <0x02184200 0x200>;
 833                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 834                                 clocks = <&clks 162>;
 835                                 fsl,usbphy = <&usbphy2>;
 836                                 fsl,usbmisc = <&usbmisc 1>;
 837                                 status = "disabled";
 838                         };
 839
 840                         usbh2: usb@02184400 {
 841                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 842                                 reg = <0x02184400 0x200>;
 843                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clks 162>;
 845                                 fsl,usbmisc = <&usbmisc 2>;
 846                                 status = "disabled";
 847                         };
 848
 849                         usbh3: usb@02184600 {
 850                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 851                                 reg = <0x02184600 0x200>;
 852                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clks 162>;
 854                                 fsl,usbmisc = <&usbmisc 3>;
 855                                 status = "disabled";
 856                         };
 857
 858                         usbmisc: usbmisc@02184800 {
 859                                 #index-cells = <1>;
 860                                 compatible = "fsl,imx6q-usbmisc";
 861                                 reg = <0x02184800 0x200>;
 862                                 clocks = <&clks 162>;
 863                         };
 864
 865                         fec: ethernet@02188000 {
 866                                 compatible = "fsl,imx6q-fec";
 867                                 reg = <0x02188000 0x4000>;
 868                                 interrupts-extended =
 869                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 870                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 871                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 872                                 clock-names = "ipg", "ahb", "ptp";
 873                                 status = "disabled";
 874                         };
 875
 876                         mlb@0218c000 {
 877                                 reg = <0x0218c000 0x4000>;
 878                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 879                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 880                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 881                         };
 882
 883                         usdhc1: usdhc@02190000 {
 884                                 compatible = "fsl,imx6q-usdhc";
 885                                 reg = <0x02190000 0x4000>;
 886                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 887                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 888                                 clock-names = "ipg", "ahb", "per";
 889                                 bus-width = <4>;
 890                                 status = "disabled";
 891                         };
 892
 893                         usdhc2: usdhc@02194000 {
 894                                 compatible = "fsl,imx6q-usdhc";
 895                                 reg = <0x02194000 0x4000>;
 896                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 897                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 898                                 clock-names = "ipg", "ahb", "per";
 899                                 bus-width = <4>;
 900                                 status = "disabled";
 901                         };
 902
 903                         usdhc3: usdhc@02198000 {
 904                                 compatible = "fsl,imx6q-usdhc";
 905                                 reg = <0x02198000 0x4000>;
 906                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 908                                 clock-names = "ipg", "ahb", "per";
 909                                 bus-width = <4>;
 910                                 status = "disabled";
 911                         };
 912
 913                         usdhc4: usdhc@0219c000 {
 914                                 compatible = "fsl,imx6q-usdhc";
 915                                 reg = <0x0219c000 0x4000>;
 916                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 918                                 clock-names = "ipg", "ahb", "per";
 919                                 bus-width = <4>;
 920                                 status = "disabled";
 921                         };
 922
 923                         i2c1: i2c@021a0000 {
 924                                 #address-cells = <1>;
 925                                 #size-cells = <0>;
 926                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 927                                 reg = <0x021a0000 0x4000>;
 928                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 929                                 clocks = <&clks 125>;
 930                                 status = "disabled";
 931                         };
 932
 933                         i2c2: i2c@021a4000 {
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 937                                 reg = <0x021a4000 0x4000>;
 938                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&clks 126>;
 940                                 status = "disabled";
 941                         };
 942
 943                         i2c3: i2c@021a8000 {
 944                                 #address-cells = <1>;
 945                                 #size-cells = <0>;
 946                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 947                                 reg = <0x021a8000 0x4000>;
 948                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 949                                 clocks = <&clks 127>;
 950                                 status = "disabled";
 951                         };
 952
 953                         romcp@021ac000 {
 954                                 reg = <0x021ac000 0x4000>;
 955                         };
 956
 957                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 958                                 compatible = "fsl,imx6q-mmdc";
 959                                 reg = <0x021b0000 0x4000>;
 960                         };
 961
 962                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 963                                 reg = <0x021b4000 0x4000>;
 964                         };
 965
 966                         weim: weim@021b8000 {
 967                                 compatible = "fsl,imx6q-weim";
 968                                 reg = <0x021b8000 0x4000>;
 969                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 970                                 clocks = <&clks 196>;
 971                         };
 972
 973                         ocotp: ocotp@021bc000 {
 974                                 compatible = "fsl,imx6q-ocotp", "syscon";
 975                                 reg = <0x021bc000 0x4000>;
 976                         };
 977
 978                         tzasc@021d0000 { /* TZASC1 */
 979                                 reg = <0x021d0000 0x4000>;
 980                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 981                         };
 982
 983                         tzasc@021d4000 { /* TZASC2 */
 984                                 reg = <0x021d4000 0x4000>;
 985                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 986                         };
 987
 988                         audmux: audmux@021d8000 {
 989                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 990                                 reg = <0x021d8000 0x4000>;
 991                                 status = "disabled";
 992                         };
 993
 994                         mipi_csi: mipi@021dc000 {
 995                                 reg = <0x021dc000 0x4000>;
 996                         };
 997
 998                         mipi_dsi: mipi@021e0000 {
 999                                 #address-cells = <1>;
1000                                 #size-cells = <0>;
1001                                 reg = <0x021e0000 0x4000>;
1002                                 status = "disabled";
1003
1004                                 port@0 {
1005                                         reg = <0>;
1006
1007                                         mipi_mux_0: endpoint {
1008                                                 remote-endpoint = <&ipu1_di0_mipi>;
1009                                         };
1010                                 };
1011
1012                                 port@1 {
1013                                         reg = <1>;
1014
1015                                         mipi_mux_1: endpoint {
1016                                                 remote-endpoint = <&ipu1_di1_mipi>;
1017                                         };
1018                                 };
1019                         };
1020
1021                         vdoa@021e4000 {
1022                                 reg = <0x021e4000 0x4000>;
1023                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1024                         };
1025
1026                         uart2: serial@021e8000 {
1027                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1028                                 reg = <0x021e8000 0x4000>;
1029                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1030                                 clocks = <&clks 160>, <&clks 161>;
1031                                 clock-names = "ipg", "per";
1032                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1033                                 dma-names = "rx", "tx";
1034                                 status = "disabled";
1035                         };
1036
1037                         uart3: serial@021ec000 {
1038                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1039                                 reg = <0x021ec000 0x4000>;
1040                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1041                                 clocks = <&clks 160>, <&clks 161>;
1042                                 clock-names = "ipg", "per";
1043                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1044                                 dma-names = "rx", "tx";
1045                                 status = "disabled";
1046                         };
1047
1048                         uart4: serial@021f0000 {
1049                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1050                                 reg = <0x021f0000 0x4000>;
1051                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks 160>, <&clks 161>;
1053                                 clock-names = "ipg", "per";
1054                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1055                                 dma-names = "rx", "tx";
1056                                 status = "disabled";
1057                         };
1058
1059                         uart5: serial@021f4000 {
1060                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1061                                 reg = <0x021f4000 0x4000>;
1062                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1063                                 clocks = <&clks 160>, <&clks 161>;
1064                                 clock-names = "ipg", "per";
1065                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1066                                 dma-names = "rx", "tx";
1067                                 status = "disabled";
1068                         };
1069                 };
1070
1071                 ipu1: ipu@02400000 {
1072                         #address-cells = <1>;
1073                         #size-cells = <0>;
1074                         compatible = "fsl,imx6q-ipu";
1075                         reg = <0x02400000 0x400000>;
1076                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1077                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1078                         clocks = <&clks 130>, <&clks 131>, <&clks 132>,
1079                                  <&clks 39>, <&clks 40>,
1080                                  <&clks 135>, <&clks 136>;
1081                         clock-names = "bus", "di0", "di1",
1082                                       "di0_sel", "di1_sel",
1083                                       "ldb_di0", "ldb_di1";
1084                         resets = <&src 2>;
1085                         bypass_reset = <0>;
1086
1087                         ipu1_di0: port@2 {
1088                                 #address-cells = <1>;
1089                                 #size-cells = <0>;
1090                                 reg = <2>;
1091
1092                                 ipu1_di0_disp0: endpoint@0 {
1093                                 };
1094
1095                                 ipu1_di0_hdmi: endpoint@1 {
1096                                         remote-endpoint = <&hdmi_mux_0>;
1097                                 };
1098
1099                                 ipu1_di0_mipi: endpoint@2 {
1100                                         remote-endpoint = <&mipi_mux_0>;
1101                                 };
1102
1103                                 ipu1_di0_lvds0: endpoint@3 {
1104                                         remote-endpoint = <&lvds0_mux_0>;
1105                                 };
1106
1107                                 ipu1_di0_lvds1: endpoint@4 {
1108                                         remote-endpoint = <&lvds1_mux_0>;
1109                                 };
1110                         };
1111
1112                         ipu1_di1: port@3 {
1113                                 #address-cells = <1>;
1114                                 #size-cells = <0>;
1115                                 reg = <3>;
1116
1117                                 ipu1_di0_disp1: endpoint@0 {
1118                                 };
1119
1120                                 ipu1_di1_hdmi: endpoint@1 {
1121                                         remote-endpoint = <&hdmi_mux_1>;
1122                                 };
1123
1124                                 ipu1_di1_mipi: endpoint@2 {
1125                                         remote-endpoint = <&mipi_mux_1>;
1126                                 };
1127
1128                                 ipu1_di1_lvds0: endpoint@3 {
1129                                         remote-endpoint = <&lvds0_mux_1>;
1130                                 };
1131
1132                                 ipu1_di1_lvds1: endpoint@4 {
1133                                         remote-endpoint = <&lvds1_mux_1>;
1134                                 };
1135                         };
1136                 };
1137         };
1138 };