arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         intc: interrupt-controller@00a01000 {
  32                 compatible = "arm,cortex-a9-gic";
  33                 #interrupt-cells = <3>;
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 interrupt-controller;
  37                 reg = <0x00a01000 0x1000>,
  38                       <0x00a00100 0x100>;
  39         };
  40
  41         clocks {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 ckil {
  46                         compatible = "fsl,imx-ckil", "fixed-clock";
  47                         clock-frequency = <32768>;
  48                 };
  49
  50                 ckih1 {
  51                         compatible = "fsl,imx-ckih1", "fixed-clock";
  52                         clock-frequency = <0>;
  53                 };
  54
  55                 osc {
  56                         compatible = "fsl,imx-osc", "fixed-clock";
  57                         clock-frequency = <24000000>;
  58                 };
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "simple-bus";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 dma-apbh@00110000 {
  69                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  70                         reg = <0x00110000 0x2000>;
  71                         clocks = <&clks 106>;
  72                 };
  73
  74                 gpmi: gpmi-nand@00112000 {
  75                         compatible = "fsl,imx6q-gpmi-nand";
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  79                         reg-names = "gpmi-nand", "bch";
  80                         interrupts = <0 13 0x04>, <0 15 0x04>;
  81                         interrupt-names = "gpmi-dma", "bch";
  82                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  83                                  <&clks 150>, <&clks 149>;
  84                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  85                                       "gpmi_bch_apb", "per1_bch";
  86                         fsl,gpmi-dma-channel = <0>;
  87                         status = "disabled";
  88                 };
  89
  90                 timer@00a00600 {
  91                         compatible = "arm,cortex-a9-twd-timer";
  92                         reg = <0x00a00600 0x20>;
  93                         interrupts = <1 13 0xf01>;
  94                         clocks = <&clks 15>;
  95                 };
  96
  97                 L2: l2-cache@00a02000 {
  98                         compatible = "arm,pl310-cache";
  99                         reg = <0x00a02000 0x1000>;
 100                         interrupts = <0 92 0x04>;
 101                         cache-unified;
 102                         cache-level = <2>;
 103                 };
 104
 105                 pmu {
 106                         compatible = "arm,cortex-a9-pmu";
 107                         interrupts = <0 94 0x04>;
 108                 };
 109
 110                 aips-bus@02000000 { /* AIPS1 */
 111                         compatible = "fsl,aips-bus", "simple-bus";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         reg = <0x02000000 0x100000>;
 115                         ranges;
 116
 117                         spba-bus@02000000 {
 118                                 compatible = "fsl,spba-bus", "simple-bus";
 119                                 #address-cells = <1>;
 120                                 #size-cells = <1>;
 121                                 reg = <0x02000000 0x40000>;
 122                                 ranges;
 123
 124                                 spdif: spdif@02004000 {
 125                                         reg = <0x02004000 0x4000>;
 126                                         interrupts = <0 52 0x04>;
 127                                 };
 128
 129                                 ecspi1: ecspi@02008000 {
 130                                         #address-cells = <1>;
 131                                         #size-cells = <0>;
 132                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 133                                         reg = <0x02008000 0x4000>;
 134                                         interrupts = <0 31 0x04>;
 135                                         clocks = <&clks 112>, <&clks 112>;
 136                                         clock-names = "ipg", "per";
 137                                         status = "disabled";
 138                                 };
 139
 140                                 ecspi2: ecspi@0200c000 {
 141                                         #address-cells = <1>;
 142                                         #size-cells = <0>;
 143                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 144                                         reg = <0x0200c000 0x4000>;
 145                                         interrupts = <0 32 0x04>;
 146                                         clocks = <&clks 113>, <&clks 113>;
 147                                         clock-names = "ipg", "per";
 148                                         status = "disabled";
 149                                 };
 150
 151                                 ecspi3: ecspi@02010000 {
 152                                         #address-cells = <1>;
 153                                         #size-cells = <0>;
 154                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 155                                         reg = <0x02010000 0x4000>;
 156                                         interrupts = <0 33 0x04>;
 157                                         clocks = <&clks 114>, <&clks 114>;
 158                                         clock-names = "ipg", "per";
 159                                         status = "disabled";
 160                                 };
 161
 162                                 ecspi4: ecspi@02014000 {
 163                                         #address-cells = <1>;
 164                                         #size-cells = <0>;
 165                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 166                                         reg = <0x02014000 0x4000>;
 167                                         interrupts = <0 34 0x04>;
 168                                         clocks = <&clks 115>, <&clks 115>;
 169                                         clock-names = "ipg", "per";
 170                                         status = "disabled";
 171                                 };
 172
 173                                 uart1: serial@02020000 {
 174                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 175                                         reg = <0x02020000 0x4000>;
 176                                         interrupts = <0 26 0x04>;
 177                                         clocks = <&clks 160>, <&clks 161>;
 178                                         clock-names = "ipg", "per";
 179                                         status = "disabled";
 180                                 };
 181
 182                                 esai: esai@02024000 {
 183                                         reg = <0x02024000 0x4000>;
 184                                         interrupts = <0 51 0x04>;
 185                                 };
 186
 187                                 ssi1: ssi@02028000 {
 188                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 189                                         reg = <0x02028000 0x4000>;
 190                                         interrupts = <0 46 0x04>;
 191                                         clocks = <&clks 178>;
 192                                         fsl,fifo-depth = <15>;
 193                                         fsl,ssi-dma-events = <38 37>;
 194                                         status = "disabled";
 195                                 };
 196
 197                                 ssi2: ssi@0202c000 {
 198                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 199                                         reg = <0x0202c000 0x4000>;
 200                                         interrupts = <0 47 0x04>;
 201                                         clocks = <&clks 179>;
 202                                         fsl,fifo-depth = <15>;
 203                                         fsl,ssi-dma-events = <42 41>;
 204                                         status = "disabled";
 205                                 };
 206
 207                                 ssi3: ssi@02030000 {
 208                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 209                                         reg = <0x02030000 0x4000>;
 210                                         interrupts = <0 48 0x04>;
 211                                         clocks = <&clks 180>;
 212                                         fsl,fifo-depth = <15>;
 213                                         fsl,ssi-dma-events = <46 45>;
 214                                         status = "disabled";
 215                                 };
 216
 217                                 asrc: asrc@02034000 {
 218                                         reg = <0x02034000 0x4000>;
 219                                         interrupts = <0 50 0x04>;
 220                                 };
 221
 222                                 spba@0203c000 {
 223                                         reg = <0x0203c000 0x4000>;
 224                                 };
 225                         };
 226
 227                         vpu: vpu@02040000 {
 228                                 reg = <0x02040000 0x3c000>;
 229                                 interrupts = <0 3 0x04 0 12 0x04>;
 230                         };
 231
 232                         aipstz@0207c000 { /* AIPSTZ1 */
 233                                 reg = <0x0207c000 0x4000>;
 234                         };
 235
 236                         pwm1: pwm@02080000 {
 237                                 #pwm-cells = <2>;
 238                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 239                                 reg = <0x02080000 0x4000>;
 240                                 interrupts = <0 83 0x04>;
 241                                 clocks = <&clks 62>, <&clks 145>;
 242                                 clock-names = "ipg", "per";
 243                         };
 244
 245                         pwm2: pwm@02084000 {
 246                                 #pwm-cells = <2>;
 247                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 248                                 reg = <0x02084000 0x4000>;
 249                                 interrupts = <0 84 0x04>;
 250                                 clocks = <&clks 62>, <&clks 146>;
 251                                 clock-names = "ipg", "per";
 252                         };
 253
 254                         pwm3: pwm@02088000 {
 255                                 #pwm-cells = <2>;
 256                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 257                                 reg = <0x02088000 0x4000>;
 258                                 interrupts = <0 85 0x04>;
 259                                 clocks = <&clks 62>, <&clks 147>;
 260                                 clock-names = "ipg", "per";
 261                         };
 262
 263                         pwm4: pwm@0208c000 {
 264                                 #pwm-cells = <2>;
 265                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 266                                 reg = <0x0208c000 0x4000>;
 267                                 interrupts = <0 86 0x04>;
 268                                 clocks = <&clks 62>, <&clks 148>;
 269                                 clock-names = "ipg", "per";
 270                         };
 271
 272                         can1: flexcan@02090000 {
 273                                 reg = <0x02090000 0x4000>;
 274                                 interrupts = <0 110 0x04>;
 275                         };
 276
 277                         can2: flexcan@02094000 {
 278                                 reg = <0x02094000 0x4000>;
 279                                 interrupts = <0 111 0x04>;
 280                         };
 281
 282                         gpt: gpt@02098000 {
 283                                 compatible = "fsl,imx6q-gpt";
 284                                 reg = <0x02098000 0x4000>;
 285                                 interrupts = <0 55 0x04>;
 286                                 clocks = <&clks 119>, <&clks 120>;
 287                                 clock-names = "ipg", "per";
 288                         };
 289
 290                         gpio1: gpio@0209c000 {
 291                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 292                                 reg = <0x0209c000 0x4000>;
 293                                 interrupts = <0 66 0x04 0 67 0x04>;
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 interrupt-controller;
 297                                 #interrupt-cells = <2>;
 298                         };
 299
 300                         gpio2: gpio@020a0000 {
 301                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 302                                 reg = <0x020a0000 0x4000>;
 303                                 interrupts = <0 68 0x04 0 69 0x04>;
 304                                 gpio-controller;
 305                                 #gpio-cells = <2>;
 306                                 interrupt-controller;
 307                                 #interrupt-cells = <2>;
 308                         };
 309
 310                         gpio3: gpio@020a4000 {
 311                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 312                                 reg = <0x020a4000 0x4000>;
 313                                 interrupts = <0 70 0x04 0 71 0x04>;
 314                                 gpio-controller;
 315                                 #gpio-cells = <2>;
 316                                 interrupt-controller;
 317                                 #interrupt-cells = <2>;
 318                         };
 319
 320                         gpio4: gpio@020a8000 {
 321                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 322                                 reg = <0x020a8000 0x4000>;
 323                                 interrupts = <0 72 0x04 0 73 0x04>;
 324                                 gpio-controller;
 325                                 #gpio-cells = <2>;
 326                                 interrupt-controller;
 327                                 #interrupt-cells = <2>;
 328                         };
 329
 330                         gpio5: gpio@020ac000 {
 331                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 332                                 reg = <0x020ac000 0x4000>;
 333                                 interrupts = <0 74 0x04 0 75 0x04>;
 334                                 gpio-controller;
 335                                 #gpio-cells = <2>;
 336                                 interrupt-controller;
 337                                 #interrupt-cells = <2>;
 338                         };
 339
 340                         gpio6: gpio@020b0000 {
 341                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 342                                 reg = <0x020b0000 0x4000>;
 343                                 interrupts = <0 76 0x04 0 77 0x04>;
 344                                 gpio-controller;
 345                                 #gpio-cells = <2>;
 346                                 interrupt-controller;
 347                                 #interrupt-cells = <2>;
 348                         };
 349
 350                         gpio7: gpio@020b4000 {
 351                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 352                                 reg = <0x020b4000 0x4000>;
 353                                 interrupts = <0 78 0x04 0 79 0x04>;
 354                                 gpio-controller;
 355                                 #gpio-cells = <2>;
 356                                 interrupt-controller;
 357                                 #interrupt-cells = <2>;
 358                         };
 359
 360                         kpp: kpp@020b8000 {
 361                                 reg = <0x020b8000 0x4000>;
 362                                 interrupts = <0 82 0x04>;
 363                         };
 364
 365                         wdog1: wdog@020bc000 {
 366                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 367                                 reg = <0x020bc000 0x4000>;
 368                                 interrupts = <0 80 0x04>;
 369                                 clocks = <&clks 0>;
 370                         };
 371
 372                         wdog2: wdog@020c0000 {
 373                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 374                                 reg = <0x020c0000 0x4000>;
 375                                 interrupts = <0 81 0x04>;
 376                                 clocks = <&clks 0>;
 377                                 status = "disabled";
 378                         };
 379
 380                         clks: ccm@020c4000 {
 381                                 compatible = "fsl,imx6q-ccm";
 382                                 reg = <0x020c4000 0x4000>;
 383                                 interrupts = <0 87 0x04 0 88 0x04>;
 384                                 #clock-cells = <1>;
 385                         };
 386
 387                         anatop: anatop@020c8000 {
 388                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 389                                 reg = <0x020c8000 0x1000>;
 390                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 391
 392                                 regulator-1p1@110 {
 393                                         compatible = "fsl,anatop-regulator";
 394                                         regulator-name = "vdd1p1";
 395                                         regulator-min-microvolt = <800000>;
 396                                         regulator-max-microvolt = <1375000>;
 397                                         regulator-always-on;
 398                                         anatop-reg-offset = <0x110>;
 399                                         anatop-vol-bit-shift = <8>;
 400                                         anatop-vol-bit-width = <5>;
 401                                         anatop-min-bit-val = <4>;
 402                                         anatop-min-voltage = <800000>;
 403                                         anatop-max-voltage = <1375000>;
 404                                 };
 405
 406                                 regulator-3p0@120 {
 407                                         compatible = "fsl,anatop-regulator";
 408                                         regulator-name = "vdd3p0";
 409                                         regulator-min-microvolt = <2800000>;
 410                                         regulator-max-microvolt = <3150000>;
 411                                         regulator-always-on;
 412                                         anatop-reg-offset = <0x120>;
 413                                         anatop-vol-bit-shift = <8>;
 414                                         anatop-vol-bit-width = <5>;
 415                                         anatop-min-bit-val = <0>;
 416                                         anatop-min-voltage = <2625000>;
 417                                         anatop-max-voltage = <3400000>;
 418                                 };
 419
 420                                 regulator-2p5@130 {
 421                                         compatible = "fsl,anatop-regulator";
 422                                         regulator-name = "vdd2p5";
 423                                         regulator-min-microvolt = <2000000>;
 424                                         regulator-max-microvolt = <2750000>;
 425                                         regulator-always-on;
 426                                         anatop-reg-offset = <0x130>;
 427                                         anatop-vol-bit-shift = <8>;
 428                                         anatop-vol-bit-width = <5>;
 429                                         anatop-min-bit-val = <0>;
 430                                         anatop-min-voltage = <2000000>;
 431                                         anatop-max-voltage = <2750000>;
 432                                 };
 433
 434                                 reg_arm: regulator-vddcore@140 {
 435                                         compatible = "fsl,anatop-regulator";
 436                                         regulator-name = "cpu";
 437                                         regulator-min-microvolt = <725000>;
 438                                         regulator-max-microvolt = <1450000>;
 439                                         regulator-always-on;
 440                                         anatop-reg-offset = <0x140>;
 441                                         anatop-vol-bit-shift = <0>;
 442                                         anatop-vol-bit-width = <5>;
 443                                         anatop-delay-reg-offset = <0x170>;
 444                                         anatop-delay-bit-shift = <24>;
 445                                         anatop-delay-bit-width = <2>;
 446                                         anatop-min-bit-val = <1>;
 447                                         anatop-min-voltage = <725000>;
 448                                         anatop-max-voltage = <1450000>;
 449                                 };
 450
 451                                 reg_pu: regulator-vddpu@140 {
 452                                         compatible = "fsl,anatop-regulator";
 453                                         regulator-name = "vddpu";
 454                                         regulator-min-microvolt = <725000>;
 455                                         regulator-max-microvolt = <1450000>;
 456                                         regulator-always-on;
 457                                         anatop-reg-offset = <0x140>;
 458                                         anatop-vol-bit-shift = <9>;
 459                                         anatop-vol-bit-width = <5>;
 460                                         anatop-delay-reg-offset = <0x170>;
 461                                         anatop-delay-bit-shift = <26>;
 462                                         anatop-delay-bit-width = <2>;
 463                                         anatop-min-bit-val = <1>;
 464                                         anatop-min-voltage = <725000>;
 465                                         anatop-max-voltage = <1450000>;
 466                                 };
 467
 468                                 reg_soc: regulator-vddsoc@140 {
 469                                         compatible = "fsl,anatop-regulator";
 470                                         regulator-name = "vddsoc";
 471                                         regulator-min-microvolt = <725000>;
 472                                         regulator-max-microvolt = <1450000>;
 473                                         regulator-always-on;
 474                                         anatop-reg-offset = <0x140>;
 475                                         anatop-vol-bit-shift = <18>;
 476                                         anatop-vol-bit-width = <5>;
 477                                         anatop-delay-reg-offset = <0x170>;
 478                                         anatop-delay-bit-shift = <28>;
 479                                         anatop-delay-bit-width = <2>;
 480                                         anatop-min-bit-val = <1>;
 481                                         anatop-min-voltage = <725000>;
 482                                         anatop-max-voltage = <1450000>;
 483                                 };
 484                         };
 485
 486                         usbphy1: usbphy@020c9000 {
 487                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 488                                 reg = <0x020c9000 0x1000>;
 489                                 interrupts = <0 44 0x04>;
 490                                 clocks = <&clks 182>;
 491                         };
 492
 493                         usbphy2: usbphy@020ca000 {
 494                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 495                                 reg = <0x020ca000 0x1000>;
 496                                 interrupts = <0 45 0x04>;
 497                                 clocks = <&clks 183>;
 498                         };
 499
 500                         snvs@020cc000 {
 501                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 502                                 #address-cells = <1>;
 503                                 #size-cells = <1>;
 504                                 ranges = <0 0x020cc000 0x4000>;
 505
 506                                 snvs-rtc-lp@34 {
 507                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 508                                         reg = <0x34 0x58>;
 509                                         interrupts = <0 19 0x04 0 20 0x04>;
 510                                 };
 511                         };
 512
 513                         epit1: epit@020d0000 { /* EPIT1 */
 514                                 reg = <0x020d0000 0x4000>;
 515                                 interrupts = <0 56 0x04>;
 516                         };
 517
 518                         epit2: epit@020d4000 { /* EPIT2 */
 519                                 reg = <0x020d4000 0x4000>;
 520                                 interrupts = <0 57 0x04>;
 521                         };
 522
 523                         src: src@020d8000 {
 524                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 525                                 reg = <0x020d8000 0x4000>;
 526                                 interrupts = <0 91 0x04 0 96 0x04>;
 527                                 #reset-cells = <1>;
 528                         };
 529
 530                         gpc: gpc@020dc000 {
 531                                 compatible = "fsl,imx6q-gpc";
 532                                 reg = <0x020dc000 0x4000>;
 533                                 interrupts = <0 89 0x04 0 90 0x04>;
 534                         };
 535
 536                         gpr: iomuxc-gpr@020e0000 {
 537                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 538                                 reg = <0x020e0000 0x38>;
 539                         };
 540
 541                         ldb: ldb@020e0008 {
 542                                 #address-cells = <1>;
 543                                 #size-cells = <0>;
 544                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 545                                 gpr = <&gpr>;
 546                                 status = "disabled";
 547
 548                                 lvds-channel@0 {
 549                                         reg = <0>;
 550                                         crtcs = <&ipu1 0>;
 551                                         status = "disabled";
 552                                 };
 553
 554                                 lvds-channel@1 {
 555                                         reg = <1>;
 556                                         crtcs = <&ipu1 1>;
 557                                         status = "disabled";
 558                                 };
 559                         };
 560
 561                         dcic1: dcic@020e4000 {
 562                                 reg = <0x020e4000 0x4000>;
 563                                 interrupts = <0 124 0x04>;
 564                         };
 565
 566                         dcic2: dcic@020e8000 {
 567                                 reg = <0x020e8000 0x4000>;
 568                                 interrupts = <0 125 0x04>;
 569                         };
 570
 571                         sdma: sdma@020ec000 {
 572                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 573                                 reg = <0x020ec000 0x4000>;
 574                                 interrupts = <0 2 0x04>;
 575                                 clocks = <&clks 155>, <&clks 155>;
 576                                 clock-names = "ipg", "ahb";
 577                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 578                         };
 579                 };
 580
 581                 aips-bus@02100000 { /* AIPS2 */
 582                         compatible = "fsl,aips-bus", "simple-bus";
 583                         #address-cells = <1>;
 584                         #size-cells = <1>;
 585                         reg = <0x02100000 0x100000>;
 586                         ranges;
 587
 588                         caam@02100000 {
 589                                 reg = <0x02100000 0x40000>;
 590                                 interrupts = <0 105 0x04 0 106 0x04>;
 591                         };
 592
 593                         aipstz@0217c000 { /* AIPSTZ2 */
 594                                 reg = <0x0217c000 0x4000>;
 595                         };
 596
 597                         usbotg: usb@02184000 {
 598                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 599                                 reg = <0x02184000 0x200>;
 600                                 interrupts = <0 43 0x04>;
 601                                 clocks = <&clks 162>;
 602                                 fsl,usbphy = <&usbphy1>;
 603                                 fsl,usbmisc = <&usbmisc 0>;
 604                                 status = "disabled";
 605                         };
 606
 607                         usbh1: usb@02184200 {
 608                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 609                                 reg = <0x02184200 0x200>;
 610                                 interrupts = <0 40 0x04>;
 611                                 clocks = <&clks 162>;
 612                                 fsl,usbphy = <&usbphy2>;
 613                                 fsl,usbmisc = <&usbmisc 1>;
 614                                 status = "disabled";
 615                         };
 616
 617                         usbh2: usb@02184400 {
 618                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 619                                 reg = <0x02184400 0x200>;
 620                                 interrupts = <0 41 0x04>;
 621                                 clocks = <&clks 162>;
 622                                 fsl,usbmisc = <&usbmisc 2>;
 623                                 status = "disabled";
 624                         };
 625
 626                         usbh3: usb@02184600 {
 627                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 628                                 reg = <0x02184600 0x200>;
 629                                 interrupts = <0 42 0x04>;
 630                                 clocks = <&clks 162>;
 631                                 fsl,usbmisc = <&usbmisc 3>;
 632                                 status = "disabled";
 633                         };
 634
 635                         usbmisc: usbmisc: usbmisc@02184800 {
 636                                 #index-cells = <1>;
 637                                 compatible = "fsl,imx6q-usbmisc";
 638                                 reg = <0x02184800 0x200>;
 639                                 clocks = <&clks 162>;
 640                         };
 641
 642                         fec: ethernet@02188000 {
 643                                 compatible = "fsl,imx6q-fec";
 644                                 reg = <0x02188000 0x4000>;
 645                                 interrupts = <0 118 0x04 0 119 0x04>;
 646                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 647                                 clock-names = "ipg", "ahb", "ptp";
 648                                 status = "disabled";
 649                         };
 650
 651                         mlb@0218c000 {
 652                                 reg = <0x0218c000 0x4000>;
 653                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 654                         };
 655
 656                         usdhc1: usdhc@02190000 {
 657                                 compatible = "fsl,imx6q-usdhc";
 658                                 reg = <0x02190000 0x4000>;
 659                                 interrupts = <0 22 0x04>;
 660                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 661                                 clock-names = "ipg", "ahb", "per";
 662                                 bus-width = <4>;
 663                                 status = "disabled";
 664                         };
 665
 666                         usdhc2: usdhc@02194000 {
 667                                 compatible = "fsl,imx6q-usdhc";
 668                                 reg = <0x02194000 0x4000>;
 669                                 interrupts = <0 23 0x04>;
 670                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 671                                 clock-names = "ipg", "ahb", "per";
 672                                 bus-width = <4>;
 673                                 status = "disabled";
 674                         };
 675
 676                         usdhc3: usdhc@02198000 {
 677                                 compatible = "fsl,imx6q-usdhc";
 678                                 reg = <0x02198000 0x4000>;
 679                                 interrupts = <0 24 0x04>;
 680                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 681                                 clock-names = "ipg", "ahb", "per";
 682                                 bus-width = <4>;
 683                                 status = "disabled";
 684                         };
 685
 686                         usdhc4: usdhc@0219c000 {
 687                                 compatible = "fsl,imx6q-usdhc";
 688                                 reg = <0x0219c000 0x4000>;
 689                                 interrupts = <0 25 0x04>;
 690                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 691                                 clock-names = "ipg", "ahb", "per";
 692                                 bus-width = <4>;
 693                                 status = "disabled";
 694                         };
 695
 696                         i2c1: i2c@021a0000 {
 697                                 #address-cells = <1>;
 698                                 #size-cells = <0>;
 699                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 700                                 reg = <0x021a0000 0x4000>;
 701                                 interrupts = <0 36 0x04>;
 702                                 clocks = <&clks 125>;
 703                                 status = "disabled";
 704                         };
 705
 706                         i2c2: i2c@021a4000 {
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 710                                 reg = <0x021a4000 0x4000>;
 711                                 interrupts = <0 37 0x04>;
 712                                 clocks = <&clks 126>;
 713                                 status = "disabled";
 714                         };
 715
 716                         i2c3: i2c@021a8000 {
 717                                 #address-cells = <1>;
 718                                 #size-cells = <0>;
 719                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 720                                 reg = <0x021a8000 0x4000>;
 721                                 interrupts = <0 38 0x04>;
 722                                 clocks = <&clks 127>;
 723                                 status = "disabled";
 724                         };
 725
 726                         romcp@021ac000 {
 727                                 reg = <0x021ac000 0x4000>;
 728                         };
 729
 730                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 731                                 compatible = "fsl,imx6q-mmdc";
 732                                 reg = <0x021b0000 0x4000>;
 733                         };
 734
 735                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 736                                 reg = <0x021b4000 0x4000>;
 737                         };
 738
 739                         weim@021b8000 {
 740                                 reg = <0x021b8000 0x4000>;
 741                                 interrupts = <0 14 0x04>;
 742                         };
 743
 744                         ocotp@021bc000 {
 745                                 compatible = "fsl,imx6q-ocotp";
 746                                 reg = <0x021bc000 0x4000>;
 747                         };
 748
 749                         ocotp@021c0000 {
 750                                 reg = <0x021c0000 0x4000>;
 751                                 interrupts = <0 21 0x04>;
 752                         };
 753
 754                         tzasc@021d0000 { /* TZASC1 */
 755                                 reg = <0x021d0000 0x4000>;
 756                                 interrupts = <0 108 0x04>;
 757                         };
 758
 759                         tzasc@021d4000 { /* TZASC2 */
 760                                 reg = <0x021d4000 0x4000>;
 761                                 interrupts = <0 109 0x04>;
 762                         };
 763
 764                         audmux: audmux@021d8000 {
 765                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 766                                 reg = <0x021d8000 0x4000>;
 767                                 status = "disabled";
 768                         };
 769
 770                         mipi@021dc000 { /* MIPI-CSI */
 771                                 reg = <0x021dc000 0x4000>;
 772                         };
 773
 774                         mipi@021e0000 { /* MIPI-DSI */
 775                                 reg = <0x021e0000 0x4000>;
 776                         };
 777
 778                         vdoa@021e4000 {
 779                                 reg = <0x021e4000 0x4000>;
 780                                 interrupts = <0 18 0x04>;
 781                         };
 782
 783                         uart2: serial@021e8000 {
 784                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 785                                 reg = <0x021e8000 0x4000>;
 786                                 interrupts = <0 27 0x04>;
 787                                 clocks = <&clks 160>, <&clks 161>;
 788                                 clock-names = "ipg", "per";
 789                                 status = "disabled";
 790                         };
 791
 792                         uart3: serial@021ec000 {
 793                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 794                                 reg = <0x021ec000 0x4000>;
 795                                 interrupts = <0 28 0x04>;
 796                                 clocks = <&clks 160>, <&clks 161>;
 797                                 clock-names = "ipg", "per";
 798                                 status = "disabled";
 799                         };
 800
 801                         uart4: serial@021f0000 {
 802                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 803                                 reg = <0x021f0000 0x4000>;
 804                                 interrupts = <0 29 0x04>;
 805                                 clocks = <&clks 160>, <&clks 161>;
 806                                 clock-names = "ipg", "per";
 807                                 status = "disabled";
 808                         };
 809
 810                         uart5: serial@021f4000 {
 811                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 812                                 reg = <0x021f4000 0x4000>;
 813                                 interrupts = <0 30 0x04>;
 814                                 clocks = <&clks 160>, <&clks 161>;
 815                                 clock-names = "ipg", "per";
 816                                 status = "disabled";
 817                         };
 818                 };
 819
 820                 ipu1: ipu@02400000 {
 821                         #crtc-cells = <1>;
 822                         compatible = "fsl,imx6q-ipu";
 823                         reg = <0x02400000 0x400000>;
 824                         interrupts = <0 6 0x4 0 5 0x4>;
 825                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 826                         clock-names = "bus", "di0", "di1";
 827                         resets = <&src 2>;
 828                 };
 829         };
 830 };