arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 gpio5 = &gpio6;
  23                 gpio6 = &gpio7;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36         };
  37
  38         intc: interrupt-controller@00a01000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 interrupt-controller;
  44                 reg = <0x00a01000 0x1000>,
  45                       <0x00a00100 0x100>;
  46         };
  47
  48         clocks {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56
  57                 ckih1 {
  58                         compatible = "fsl,imx-ckih1", "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 osc {
  63                         compatible = "fsl,imx-osc", "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&intc>;
  73                 ranges;
  74
  75                 dma_apbh: dma-apbh@00110000 {
  76                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  77                         reg = <0x00110000 0x2000>;
  78                         interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
  79                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  80                         #dma-cells = <1>;
  81                         dma-channels = <4>;
  82                         clocks = <&clks 106>;
  83                 };
  84
  85                 gpmi: gpmi-nand@00112000 {
  86                         compatible = "fsl,imx6q-gpmi-nand";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  90                         reg-names = "gpmi-nand", "bch";
  91                         interrupts = <0 15 0x04>;
  92                         interrupt-names = "bch";
  93                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  94                                  <&clks 150>, <&clks 149>;
  95                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  96                                       "gpmi_bch_apb", "per1_bch";
  97                         dmas = <&dma_apbh 0>;
  98                         dma-names = "rx-tx";
  99                         status = "disabled";
 100                 };
 101
 102                 timer@00a00600 {
 103                         compatible = "arm,cortex-a9-twd-timer";
 104                         reg = <0x00a00600 0x20>;
 105                         interrupts = <1 13 0xf01>;
 106                         clocks = <&clks 15>;
 107                 };
 108
 109                 L2: l2-cache@00a02000 {
 110                         compatible = "arm,pl310-cache";
 111                         reg = <0x00a02000 0x1000>;
 112                         interrupts = <0 92 0x04>;
 113                         cache-unified;
 114                         cache-level = <2>;
 115                         arm,tag-latency = <4 2 3>;
 116                         arm,data-latency = <4 2 3>;
 117                 };
 118
 119                 pcie: pcie@0x01000000 {
 120                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 121                         reg = <0x01ffc000 0x4000>; /* DBI */
 122                         #address-cells = <3>;
 123                         #size-cells = <2>;
 124                         device_type = "pci";
 125                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 126                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 127                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 128                         num-lanes = <1>;
 129                         interrupts = <0 123 0x04>;
 130                         clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
 131                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 132                         status = "disabled";
 133                 };
 134
 135                 pmu {
 136                         compatible = "arm,cortex-a9-pmu";
 137                         interrupts = <0 94 0x04>;
 138                 };
 139
 140                 aips-bus@02000000 { /* AIPS1 */
 141                         compatible = "fsl,aips-bus", "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         reg = <0x02000000 0x100000>;
 145                         ranges;
 146
 147                         spba-bus@02000000 {
 148                                 compatible = "fsl,spba-bus", "simple-bus";
 149                                 #address-cells = <1>;
 150                                 #size-cells = <1>;
 151                                 reg = <0x02000000 0x40000>;
 152                                 ranges;
 153
 154                                 spdif: spdif@02004000 {
 155                                         compatible = "fsl,imx35-spdif";
 156                                         reg = <0x02004000 0x4000>;
 157                                         interrupts = <0 52 0x04>;
 158                                         dmas = <&sdma 14 18 0>,
 159                                                <&sdma 15 18 0>;
 160                                         dma-names = "rx", "tx";
 161                                         clocks = <&clks 197>, <&clks 3>,
 162                                                  <&clks 197>, <&clks 107>,
 163                                                  <&clks 0>,   <&clks 118>,
 164                                                  <&clks 62>,  <&clks 139>,
 165                                                  <&clks 0>;
 166                                         clock-names = "core",  "rxtx0",
 167                                                       "rxtx1", "rxtx2",
 168                                                       "rxtx3", "rxtx4",
 169                                                       "rxtx5", "rxtx6",
 170                                                       "rxtx7";
 171                                         status = "disabled";
 172                                 };
 173
 174                                 ecspi1: ecspi@02008000 {
 175                                         #address-cells = <1>;
 176                                         #size-cells = <0>;
 177                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 178                                         reg = <0x02008000 0x4000>;
 179                                         interrupts = <0 31 0x04>;
 180                                         clocks = <&clks 112>, <&clks 112>;
 181                                         clock-names = "ipg", "per";
 182                                         status = "disabled";
 183                                 };
 184
 185                                 ecspi2: ecspi@0200c000 {
 186                                         #address-cells = <1>;
 187                                         #size-cells = <0>;
 188                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 189                                         reg = <0x0200c000 0x4000>;
 190                                         interrupts = <0 32 0x04>;
 191                                         clocks = <&clks 113>, <&clks 113>;
 192                                         clock-names = "ipg", "per";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi3: ecspi@02010000 {
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 200                                         reg = <0x02010000 0x4000>;
 201                                         interrupts = <0 33 0x04>;
 202                                         clocks = <&clks 114>, <&clks 114>;
 203                                         clock-names = "ipg", "per";
 204                                         status = "disabled";
 205                                 };
 206
 207                                 ecspi4: ecspi@02014000 {
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 211                                         reg = <0x02014000 0x4000>;
 212                                         interrupts = <0 34 0x04>;
 213                                         clocks = <&clks 115>, <&clks 115>;
 214                                         clock-names = "ipg", "per";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 uart1: serial@02020000 {
 219                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 220                                         reg = <0x02020000 0x4000>;
 221                                         interrupts = <0 26 0x04>;
 222                                         clocks = <&clks 160>, <&clks 161>;
 223                                         clock-names = "ipg", "per";
 224                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 225                                         dma-names = "rx", "tx";
 226                                         status = "disabled";
 227                                 };
 228
 229                                 esai: esai@02024000 {
 230                                         reg = <0x02024000 0x4000>;
 231                                         interrupts = <0 51 0x04>;
 232                                 };
 233
 234                                 ssi1: ssi@02028000 {
 235                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 236                                         reg = <0x02028000 0x4000>;
 237                                         interrupts = <0 46 0x04>;
 238                                         clocks = <&clks 178>;
 239                                         dmas = <&sdma 37 1 0>,
 240                                                <&sdma 38 1 0>;
 241                                         dma-names = "rx", "tx";
 242                                         fsl,fifo-depth = <15>;
 243                                         fsl,ssi-dma-events = <38 37>;
 244                                         status = "disabled";
 245                                 };
 246
 247                                 ssi2: ssi@0202c000 {
 248                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 249                                         reg = <0x0202c000 0x4000>;
 250                                         interrupts = <0 47 0x04>;
 251                                         clocks = <&clks 179>;
 252                                         dmas = <&sdma 41 1 0>,
 253                                                <&sdma 42 1 0>;
 254                                         dma-names = "rx", "tx";
 255                                         fsl,fifo-depth = <15>;
 256                                         fsl,ssi-dma-events = <42 41>;
 257                                         status = "disabled";
 258                                 };
 259
 260                                 ssi3: ssi@02030000 {
 261                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 262                                         reg = <0x02030000 0x4000>;
 263                                         interrupts = <0 48 0x04>;
 264                                         clocks = <&clks 180>;
 265                                         dmas = <&sdma 45 1 0>,
 266                                                <&sdma 46 1 0>;
 267                                         dma-names = "rx", "tx";
 268                                         fsl,fifo-depth = <15>;
 269                                         fsl,ssi-dma-events = <46 45>;
 270                                         status = "disabled";
 271                                 };
 272
 273                                 asrc: asrc@02034000 {
 274                                         reg = <0x02034000 0x4000>;
 275                                         interrupts = <0 50 0x04>;
 276                                 };
 277
 278                                 spba@0203c000 {
 279                                         reg = <0x0203c000 0x4000>;
 280                                 };
 281                         };
 282
 283                         vpu: vpu@02040000 {
 284                                 reg = <0x02040000 0x3c000>;
 285                                 interrupts = <0 3 0x04 0 12 0x04>;
 286                         };
 287
 288                         aipstz@0207c000 { /* AIPSTZ1 */
 289                                 reg = <0x0207c000 0x4000>;
 290                         };
 291
 292                         pwm1: pwm@02080000 {
 293                                 #pwm-cells = <2>;
 294                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 295                                 reg = <0x02080000 0x4000>;
 296                                 interrupts = <0 83 0x04>;
 297                                 clocks = <&clks 62>, <&clks 145>;
 298                                 clock-names = "ipg", "per";
 299                         };
 300
 301                         pwm2: pwm@02084000 {
 302                                 #pwm-cells = <2>;
 303                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 304                                 reg = <0x02084000 0x4000>;
 305                                 interrupts = <0 84 0x04>;
 306                                 clocks = <&clks 62>, <&clks 146>;
 307                                 clock-names = "ipg", "per";
 308                         };
 309
 310                         pwm3: pwm@02088000 {
 311                                 #pwm-cells = <2>;
 312                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 313                                 reg = <0x02088000 0x4000>;
 314                                 interrupts = <0 85 0x04>;
 315                                 clocks = <&clks 62>, <&clks 147>;
 316                                 clock-names = "ipg", "per";
 317                         };
 318
 319                         pwm4: pwm@0208c000 {
 320                                 #pwm-cells = <2>;
 321                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 322                                 reg = <0x0208c000 0x4000>;
 323                                 interrupts = <0 86 0x04>;
 324                                 clocks = <&clks 62>, <&clks 148>;
 325                                 clock-names = "ipg", "per";
 326                         };
 327
 328                         can1: flexcan@02090000 {
 329                                 compatible = "fsl,imx6q-flexcan";
 330                                 reg = <0x02090000 0x4000>;
 331                                 interrupts = <0 110 0x04>;
 332                                 clocks = <&clks 108>, <&clks 109>;
 333                                 clock-names = "ipg", "per";
 334                                 status = "disabled";
 335                         };
 336
 337                         can2: flexcan@02094000 {
 338                                 compatible = "fsl,imx6q-flexcan";
 339                                 reg = <0x02094000 0x4000>;
 340                                 interrupts = <0 111 0x04>;
 341                                 clocks = <&clks 110>, <&clks 111>;
 342                                 clock-names = "ipg", "per";
 343                                 status = "disabled";
 344                         };
 345
 346                         gpt: gpt@02098000 {
 347                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 348                                 reg = <0x02098000 0x4000>;
 349                                 interrupts = <0 55 0x04>;
 350                                 clocks = <&clks 119>, <&clks 120>;
 351                                 clock-names = "ipg", "per";
 352                         };
 353
 354                         gpio1: gpio@0209c000 {
 355                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 356                                 reg = <0x0209c000 0x4000>;
 357                                 interrupts = <0 66 0x04 0 67 0x04>;
 358                                 gpio-controller;
 359                                 #gpio-cells = <2>;
 360                                 interrupt-controller;
 361                                 #interrupt-cells = <2>;
 362                         };
 363
 364                         gpio2: gpio@020a0000 {
 365                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 366                                 reg = <0x020a0000 0x4000>;
 367                                 interrupts = <0 68 0x04 0 69 0x04>;
 368                                 gpio-controller;
 369                                 #gpio-cells = <2>;
 370                                 interrupt-controller;
 371                                 #interrupt-cells = <2>;
 372                         };
 373
 374                         gpio3: gpio@020a4000 {
 375                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x020a4000 0x4000>;
 377                                 interrupts = <0 70 0x04 0 71 0x04>;
 378                                 gpio-controller;
 379                                 #gpio-cells = <2>;
 380                                 interrupt-controller;
 381                                 #interrupt-cells = <2>;
 382                         };
 383
 384                         gpio4: gpio@020a8000 {
 385                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 386                                 reg = <0x020a8000 0x4000>;
 387                                 interrupts = <0 72 0x04 0 73 0x04>;
 388                                 gpio-controller;
 389                                 #gpio-cells = <2>;
 390                                 interrupt-controller;
 391                                 #interrupt-cells = <2>;
 392                         };
 393
 394                         gpio5: gpio@020ac000 {
 395                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x020ac000 0x4000>;
 397                                 interrupts = <0 74 0x04 0 75 0x04>;
 398                                 gpio-controller;
 399                                 #gpio-cells = <2>;
 400                                 interrupt-controller;
 401                                 #interrupt-cells = <2>;
 402                         };
 403
 404                         gpio6: gpio@020b0000 {
 405                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 406                                 reg = <0x020b0000 0x4000>;
 407                                 interrupts = <0 76 0x04 0 77 0x04>;
 408                                 gpio-controller;
 409                                 #gpio-cells = <2>;
 410                                 interrupt-controller;
 411                                 #interrupt-cells = <2>;
 412                         };
 413
 414                         gpio7: gpio@020b4000 {
 415                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 416                                 reg = <0x020b4000 0x4000>;
 417                                 interrupts = <0 78 0x04 0 79 0x04>;
 418                                 gpio-controller;
 419                                 #gpio-cells = <2>;
 420                                 interrupt-controller;
 421                                 #interrupt-cells = <2>;
 422                         };
 423
 424                         kpp: kpp@020b8000 {
 425                                 reg = <0x020b8000 0x4000>;
 426                                 interrupts = <0 82 0x04>;
 427                         };
 428
 429                         wdog1: wdog@020bc000 {
 430                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 431                                 reg = <0x020bc000 0x4000>;
 432                                 interrupts = <0 80 0x04>;
 433                                 clocks = <&clks 0>;
 434                         };
 435
 436                         wdog2: wdog@020c0000 {
 437                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 438                                 reg = <0x020c0000 0x4000>;
 439                                 interrupts = <0 81 0x04>;
 440                                 clocks = <&clks 0>;
 441                                 status = "disabled";
 442                         };
 443
 444                         clks: ccm@020c4000 {
 445                                 compatible = "fsl,imx6q-ccm";
 446                                 reg = <0x020c4000 0x4000>;
 447                                 interrupts = <0 87 0x04 0 88 0x04>;
 448                                 #clock-cells = <1>;
 449                         };
 450
 451                         anatop: anatop@020c8000 {
 452                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 453                                 reg = <0x020c8000 0x1000>;
 454                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 455
 456                                 regulator-1p1@110 {
 457                                         compatible = "fsl,anatop-regulator";
 458                                         regulator-name = "vdd1p1";
 459                                         regulator-min-microvolt = <800000>;
 460                                         regulator-max-microvolt = <1375000>;
 461                                         regulator-always-on;
 462                                         anatop-reg-offset = <0x110>;
 463                                         anatop-vol-bit-shift = <8>;
 464                                         anatop-vol-bit-width = <5>;
 465                                         anatop-min-bit-val = <4>;
 466                                         anatop-min-voltage = <800000>;
 467                                         anatop-max-voltage = <1375000>;
 468                                 };
 469
 470                                 regulator-3p0@120 {
 471                                         compatible = "fsl,anatop-regulator";
 472                                         regulator-name = "vdd3p0";
 473                                         regulator-min-microvolt = <2800000>;
 474                                         regulator-max-microvolt = <3150000>;
 475                                         regulator-always-on;
 476                                         anatop-reg-offset = <0x120>;
 477                                         anatop-vol-bit-shift = <8>;
 478                                         anatop-vol-bit-width = <5>;
 479                                         anatop-min-bit-val = <0>;
 480                                         anatop-min-voltage = <2625000>;
 481                                         anatop-max-voltage = <3400000>;
 482                                 };
 483
 484                                 regulator-2p5@130 {
 485                                         compatible = "fsl,anatop-regulator";
 486                                         regulator-name = "vdd2p5";
 487                                         regulator-min-microvolt = <2000000>;
 488                                         regulator-max-microvolt = <2750000>;
 489                                         regulator-always-on;
 490                                         anatop-reg-offset = <0x130>;
 491                                         anatop-vol-bit-shift = <8>;
 492                                         anatop-vol-bit-width = <5>;
 493                                         anatop-min-bit-val = <0>;
 494                                         anatop-min-voltage = <2000000>;
 495                                         anatop-max-voltage = <2750000>;
 496                                 };
 497
 498                                 reg_arm: regulator-vddcore@140 {
 499                                         compatible = "fsl,anatop-regulator";
 500                                         regulator-name = "cpu";
 501                                         regulator-min-microvolt = <725000>;
 502                                         regulator-max-microvolt = <1450000>;
 503                                         regulator-always-on;
 504                                         anatop-reg-offset = <0x140>;
 505                                         anatop-vol-bit-shift = <0>;
 506                                         anatop-vol-bit-width = <5>;
 507                                         anatop-delay-reg-offset = <0x170>;
 508                                         anatop-delay-bit-shift = <24>;
 509                                         anatop-delay-bit-width = <2>;
 510                                         anatop-min-bit-val = <1>;
 511                                         anatop-min-voltage = <725000>;
 512                                         anatop-max-voltage = <1450000>;
 513                                 };
 514
 515                                 reg_pu: regulator-vddpu@140 {
 516                                         compatible = "fsl,anatop-regulator";
 517                                         regulator-name = "vddpu";
 518                                         regulator-min-microvolt = <725000>;
 519                                         regulator-max-microvolt = <1450000>;
 520                                         regulator-always-on;
 521                                         anatop-reg-offset = <0x140>;
 522                                         anatop-vol-bit-shift = <9>;
 523                                         anatop-vol-bit-width = <5>;
 524                                         anatop-delay-reg-offset = <0x170>;
 525                                         anatop-delay-bit-shift = <26>;
 526                                         anatop-delay-bit-width = <2>;
 527                                         anatop-min-bit-val = <1>;
 528                                         anatop-min-voltage = <725000>;
 529                                         anatop-max-voltage = <1450000>;
 530                                 };
 531
 532                                 reg_soc: regulator-vddsoc@140 {
 533                                         compatible = "fsl,anatop-regulator";
 534                                         regulator-name = "vddsoc";
 535                                         regulator-min-microvolt = <725000>;
 536                                         regulator-max-microvolt = <1450000>;
 537                                         regulator-always-on;
 538                                         anatop-reg-offset = <0x140>;
 539                                         anatop-vol-bit-shift = <18>;
 540                                         anatop-vol-bit-width = <5>;
 541                                         anatop-delay-reg-offset = <0x170>;
 542                                         anatop-delay-bit-shift = <28>;
 543                                         anatop-delay-bit-width = <2>;
 544                                         anatop-min-bit-val = <1>;
 545                                         anatop-min-voltage = <725000>;
 546                                         anatop-max-voltage = <1450000>;
 547                                 };
 548                         };
 549
 550                         tempmon: tempmon {
 551                                 compatible = "fsl,imx6q-tempmon";
 552                                 interrupts = <0 49 0x04>;
 553                                 fsl,tempmon = <&anatop>;
 554                                 fsl,tempmon-data = <&ocotp>;
 555                         };
 556
 557                         usbphy1: usbphy@020c9000 {
 558                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 559                                 reg = <0x020c9000 0x1000>;
 560                                 interrupts = <0 44 0x04>;
 561                                 clocks = <&clks 182>;
 562                         };
 563
 564                         usbphy2: usbphy@020ca000 {
 565                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 566                                 reg = <0x020ca000 0x1000>;
 567                                 interrupts = <0 45 0x04>;
 568                                 clocks = <&clks 183>;
 569                         };
 570
 571                         snvs@020cc000 {
 572                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 573                                 #address-cells = <1>;
 574                                 #size-cells = <1>;
 575                                 ranges = <0 0x020cc000 0x4000>;
 576
 577                                 snvs-rtc-lp@34 {
 578                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 579                                         reg = <0x34 0x58>;
 580                                         interrupts = <0 19 0x04 0 20 0x04>;
 581                                 };
 582                         };
 583
 584                         epit1: epit@020d0000 { /* EPIT1 */
 585                                 reg = <0x020d0000 0x4000>;
 586                                 interrupts = <0 56 0x04>;
 587                         };
 588
 589                         epit2: epit@020d4000 { /* EPIT2 */
 590                                 reg = <0x020d4000 0x4000>;
 591                                 interrupts = <0 57 0x04>;
 592                         };
 593
 594                         src: src@020d8000 {
 595                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 596                                 reg = <0x020d8000 0x4000>;
 597                                 interrupts = <0 91 0x04 0 96 0x04>;
 598                                 #reset-cells = <1>;
 599                         };
 600
 601                         gpc: gpc@020dc000 {
 602                                 compatible = "fsl,imx6q-gpc";
 603                                 reg = <0x020dc000 0x4000>;
 604                                 interrupts = <0 89 0x04 0 90 0x04>;
 605                         };
 606
 607                         gpr: iomuxc-gpr@020e0000 {
 608                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 609                                 reg = <0x020e0000 0x38>;
 610                         };
 611
 612                         iomuxc: iomuxc@020e0000 {
 613                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 614                                 reg = <0x020e0000 0x4000>;
 615
 616                                 audmux {
 617                                         pinctrl_audmux_1: audmux-1 {
 618                                                 fsl,pins = <
 619                                                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
 620                                                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
 621                                                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
 622                                                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
 623                                                 >;
 624                                         };
 625
 626                                         pinctrl_audmux_2: audmux-2 {
 627                                                 fsl,pins = <
 628                                                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
 629                                                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
 630                                                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
 631                                                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
 632                                                 >;
 633                                         };
 634
 635                                         pinctrl_audmux_3: audmux-3 {
 636                                                 fsl,pins = <
 637                                                         MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
 638                                                         MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
 639                                                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
 640                                                 >;
 641                                         };
 642
 643                                         pinctrl_audmux_4: audmux-4 {
 644                                                 fsl,pins = <
 645                                                         MX6QDL_PAD_EIM_D24__AUD5_RXFS     0x80000000
 646                                                         MX6QDL_PAD_EIM_D25__AUD5_RXC      0x80000000
 647                                                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
 648                                                 >;
 649                                         };
 650
 651                                         pinctrl_audmux_5: audmux-5 {
 652                                                 fsl,pins = <
 653                                                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD  0x80000000
 654                                                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD  0x80000000
 655                                                         MX6QDL_PAD_KEY_COL0__AUD5_TXC  0x80000000
 656                                                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x80000000
 657                                                 >;
 658                                         };
 659                                 };
 660
 661                                 ecspi1 {
 662                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 663                                                 fsl,pins = <
 664                                                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 665                                                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 666                                                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 667                                                 >;
 668                                         };
 669
 670                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 671                                                 fsl,pins = <
 672                                                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
 673                                                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
 674                                                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
 675                                                 >;
 676                                         };
 677                                 };
 678
 679                                 ecspi3 {
 680                                         pinctrl_ecspi3_1: ecspi3grp-1 {
 681                                                 fsl,pins = <
 682                                                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
 683                                                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
 684                                                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
 685                                                 >;
 686                                         };
 687                                 };
 688
 689                                 enet {
 690                                         pinctrl_enet_1: enetgrp-1 {
 691                                                 fsl,pins = <
 692                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 693                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 694                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 695                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 696                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 697                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 698                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 699                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 700                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 701                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 702                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 703                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 704                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 705                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 706                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 707                                                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 708                                                 >;
 709                                         };
 710
 711                                         pinctrl_enet_2: enetgrp-2 {
 712                                                 fsl,pins = <
 713                                                         MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
 714                                                         MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
 715                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 716                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 717                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 718                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 719                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 720                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 721                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 722                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 723                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 724                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 725                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 726                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 727                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 728                                                 >;
 729                                         };
 730
 731                                         pinctrl_enet_3: enetgrp-3 {
 732                                                 fsl,pins = <
 733                                                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 734                                                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 735                                                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 736                                                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 737                                                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 738                                                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 739                                                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 740                                                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 741                                                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 742                                                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 743                                                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 744                                                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 745                                                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 746                                                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 747                                                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 748                                                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 749                                                 >;
 750                                         };
 751                                 };
 752
 753                                 esai {
 754                                         pinctrl_esai_1: esaigrp-1 {
 755                                                 fsl,pins = <
 756                                                         MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
 757                                                         MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
 758                                                         MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
 759                                                         MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
 760                                                         MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
 761                                                         MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
 762                                                         MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
 763                                                         MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
 764                                                         MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
 765                                                 >;
 766                                         };
 767
 768                                         pinctrl_esai_2: esaigrp-2 {
 769                                                 fsl,pins = <
 770                                                         MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 771                                                         MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 772                                                         MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 773                                                         MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 774                                                         MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 775                                                         MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 776                                                         MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 777                                                         MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 778                                                         MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 779                                                         MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 780                                                 >;
 781                                         };
 782                                 };
 783
 784                                 flexcan1 {
 785                                         pinctrl_flexcan1_1: flexcan1grp-1 {
 786                                                 fsl,pins = <
 787                                                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
 788                                                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
 789                                                 >;
 790                                         };
 791
 792                                         pinctrl_flexcan1_2: flexcan1grp-2 {
 793                                                 fsl,pins = <
 794                                                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
 795                                                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
 796                                                 >;
 797                                         };
 798                                 };
 799
 800                                 flexcan2 {
 801                                         pinctrl_flexcan2_1: flexcan2grp-1 {
 802                                                 fsl,pins = <
 803                                                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
 804                                                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
 805                                                 >;
 806                                         };
 807                                 };
 808
 809                                 gpmi-nand {
 810                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 811                                                 fsl,pins = <
 812                                                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 813                                                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 814                                                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 815                                                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 816                                                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 817                                                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 818                                                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 819                                                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 820                                                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 821                                                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 822                                                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 823                                                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 824                                                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 825                                                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 826                                                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 827                                                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 828                                                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 829                                                 >;
 830                                         };
 831
 832                                         /* No Strobe */
 833                                         pinctrl_gpmi_nand_2: gpmi-nand-2 {
 834                                                 fsl,pins = <
 835                                                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 836                                                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 837                                                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 838                                                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 839                                                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 840                                                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 841                                                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 842                                                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 843                                                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 844                                                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 845                                                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 846                                                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 847                                                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 848                                                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 849                                                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 850                                                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 851                                                 >;
 852                                         };
 853                                 };
 854
 855                                 hdmi_hdcp {
 856                                         pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
 857                                                 fsl,pins = <
 858                                                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 859                                                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 860                                                 >;
 861                                         };
 862
 863                                         pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
 864                                                 fsl,pins = <
 865                                                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 866                                                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 867                                                 >;
 868                                         };
 869
 870                                         pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
 871                                                 fsl,pins = <
 872                                                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
 873                                                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 874                                                 >;
 875                                         };
 876                                 };
 877
 878                                 hdmi_cec {
 879                                         pinctrl_hdmi_cec_1: hdmicecgrp-1 {
 880                                                 fsl,pins = <
 881                                                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
 882                                                 >;
 883                                         };
 884
 885                                         pinctrl_hdmi_cec_2: hdmicecgrp-2 {
 886                                                 fsl,pins = <
 887                                                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 888                                                 >;
 889                                         };
 890                                 };
 891
 892                                 i2c1 {
 893                                         pinctrl_i2c1_1: i2c1grp-1 {
 894                                                 fsl,pins = <
 895                                                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 896                                                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 897                                                 >;
 898                                         };
 899
 900                                         pinctrl_i2c1_2: i2c1grp-2 {
 901                                                 fsl,pins = <
 902                                                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 903                                                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 904                                                 >;
 905                                         };
 906                                 };
 907
 908                                 i2c2 {
 909                                         pinctrl_i2c2_1: i2c2grp-1 {
 910                                                 fsl,pins = <
 911                                                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 912                                                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 913                                                 >;
 914                                         };
 915
 916                                         pinctrl_i2c2_2: i2c2grp-2 {
 917                                                 fsl,pins = <
 918                                                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 919                                                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 920                                                 >;
 921                                         };
 922
 923                                         pinctrl_i2c2_3: i2c2grp-3 {
 924                                                 fsl,pins = <
 925                                                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 926                                                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 927                                                 >;
 928                                         };
 929                                 };
 930
 931                                 i2c3 {
 932                                         pinctrl_i2c3_1: i2c3grp-1 {
 933                                                 fsl,pins = <
 934                                                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 935                                                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 936                                                 >;
 937                                         };
 938
 939                                         pinctrl_i2c3_2: i2c3grp-2 {
 940                                                 fsl,pins = <
 941                                                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 942                                                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 943                                                 >;
 944                                         };
 945
 946                                         pinctrl_i2c3_3: i2c3grp-3 {
 947                                                 fsl,pins = <
 948                                                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 949                                                         MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
 950                                                 >;
 951                                         };
 952
 953                                         pinctrl_i2c3_4: i2c3grp-4 {
 954                                                 fsl,pins = <
 955                                                         MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 956                                                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 957                                                 >;
 958                                         };
 959                                 };
 960
 961                                 ipu1 {
 962                                         pinctrl_ipu1_1: ipu1grp-1 {
 963                                                 fsl,pins = <
 964                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 965                                                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 966                                                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 967                                                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 968                                                         MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 969                                                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 970                                                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 971                                                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 972                                                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 973                                                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 974                                                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 975                                                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 976                                                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 977                                                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 978                                                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 979                                                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 980                                                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 981                                                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 982                                                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 983                                                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 984                                                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 985                                                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 986                                                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 987                                                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 988                                                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 989                                                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 990                                                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 991                                                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 992                                                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 993                                                 >;
 994                                         };
 995
 996                                         pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
 997                                                 fsl,pins = <
 998                                                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
 999                                                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
1000                                                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
1001                                                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
1002                                                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
1003                                                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
1004                                                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
1005                                                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
1006                                                         MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
1007                                                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
1008                                                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
1009                                                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
1010                                                 >;
1011                                         };
1012
1013                                         pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
1014                                                 fsl,pins = <
1015                                                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
1016                                                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
1017                                                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
1018                                                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
1019                                                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
1020                                                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
1021                                                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
1022                                                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
1023                                                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
1024                                                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
1025                                                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
1026                                                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
1027                                                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
1028                                                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
1029                                                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
1030                                                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
1031                                                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1032                                                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
1033                                                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
1034                                                 >;
1035                                         };
1036                                 };
1037
1038                                 mlb {
1039                                         pinctrl_mlb_1: mlbgrp-1 {
1040                                                 fsl,pins = <
1041                                                         MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
1042                                                         MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
1043                                                         MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1044                                                 >;
1045                                         };
1046
1047                                         pinctrl_mlb_2: mlbgrp-2 {
1048                                                 fsl,pins = <
1049                                                         MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
1050                                                         MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
1051                                                         MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
1052                                                 >;
1053                                         };
1054                                 };
1055
1056                                 pwm0 {
1057                                         pinctrl_pwm0_1: pwm0grp-1 {
1058                                                 fsl,pins = <
1059                                                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1060                                                 >;
1061                                         };
1062                                 };
1063
1064                                 pwm3 {
1065                                         pinctrl_pwm3_1: pwm3grp-1 {
1066                                                 fsl,pins = <
1067                                                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1068                                                 >;
1069                                         };
1070                                 };
1071
1072                                 spdif {
1073                                         pinctrl_spdif_1: spdifgrp-1 {
1074                                                 fsl,pins = <
1075                                                         MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1076                                                 >;
1077                                         };
1078
1079                                         pinctrl_spdif_2: spdifgrp-2 {
1080                                                 fsl,pins = <
1081                                                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
1082                                                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1083                                                 >;
1084                                         };
1085
1086                                         pinctrl_spdif_3: spdifgrp-3 {
1087                                                 fsl,pins = <
1088                                                         MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1089                                                 >;
1090                                         };
1091                                 };
1092
1093                                 uart1 {
1094                                         pinctrl_uart1_1: uart1grp-1 {
1095                                                 fsl,pins = <
1096                                                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1097                                                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1098                                                 >;
1099                                         };
1100
1101                                         pinctrl_uart1_2: uart1grp-2 {
1102                                                 fsl,pins = <
1103                                                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
1104                                                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
1105                                                 >;
1106                                         };
1107                                 };
1108
1109                                 uart2 {
1110                                         pinctrl_uart2_1: uart2grp-1 {
1111                                                 fsl,pins = <
1112                                                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1113                                                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1114                                                 >;
1115                                         };
1116
1117                                         pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1118                                                 fsl,pins = <
1119                                                         MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
1120                                                         MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
1121                                                         MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1122                                                         MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1123                                                 >;
1124                                         };
1125
1126                                         pinctrl_uart2_3: uart2grp-3 {
1127                                                 fsl,pins = <
1128                                                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
1129                                                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
1130                                                 >;
1131                                         };
1132                                 };
1133
1134                                 uart3 {
1135                                         pinctrl_uart3_1: uart3grp-1 {
1136                                                 fsl,pins = <
1137                                                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1138                                                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1139                                                         MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
1140                                                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
1141                                                 >;
1142                                         };
1143
1144                                         pinctrl_uart3_2: uart3grp-2 {
1145                                                 fsl,pins = <
1146                                                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1147                                                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1148                                                         MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
1149                                                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
1150                                                 >;
1151                                         };
1152
1153                                         pinctrl_uart3_3: uart3grp-3 {
1154                                                 fsl,pins = <
1155                                                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1156                                                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1157                                                 >;
1158                                         };
1159
1160                                         pinctrl_uart3_rtscts_3: uart3rtscts-3 {
1161                                                 fsl,pins = <
1162                                                         MX6QDL_PAD_SD3_DAT3__UART3_CTS_B  0x1b0b1
1163                                                         MX6QDL_PAD_SD3_RST__UART3_RTS_B   0x1b0b1
1164                                                 >;
1165                                         };
1166                                 };
1167
1168                                 uart4 {
1169                                         pinctrl_uart4_1: uart4grp-1 {
1170                                                 fsl,pins = <
1171                                                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1172                                                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1173                                                 >;
1174                                         };
1175                                 };
1176
1177                                 uart5 {
1178                                         pinctrl_uart5_1: uart5grp-1 {
1179                                                 fsl,pins = <
1180                                                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1181                                                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1182                                                 >;
1183                                         };
1184                                 };
1185
1186                                 usbotg {
1187                                         pinctrl_usbotg_1: usbotggrp-1 {
1188                                                 fsl,pins = <
1189                                                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1190                                                 >;
1191                                         };
1192
1193                                         pinctrl_usbotg_2: usbotggrp-2 {
1194                                                 fsl,pins = <
1195                                                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1196                                                 >;
1197                                         };
1198                                 };
1199
1200                                 usbh2 {
1201                                         pinctrl_usbh2_1: usbh2grp-1 {
1202                                                 fsl,pins = <
1203                                                         MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
1204                                                         MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1205                                                 >;
1206                                         };
1207
1208                                         pinctrl_usbh2_2: usbh2grp-2 {
1209                                                 fsl,pins = <
1210                                                         MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1211                                                 >;
1212                                         };
1213                                 };
1214
1215                                 usbh3 {
1216                                         pinctrl_usbh3_1: usbh3grp-1 {
1217                                                 fsl,pins = <
1218                                                         MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1219                                                         MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
1220                                                 >;
1221                                         };
1222
1223                                         pinctrl_usbh3_2: usbh3grp-2 {
1224                                                 fsl,pins = <
1225                                                         MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1226                                                 >;
1227                                         };
1228                                 };
1229
1230                                 usdhc1 {
1231                                         pinctrl_usdhc1_1: usdhc1grp-1 {
1232                                                 fsl,pins = <
1233                                                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
1234                                                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
1235                                                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1236                                                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1237                                                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1238                                                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1239                                                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1240                                                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1241                                                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1242                                                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1243                                                 >;
1244                                         };
1245
1246                                         pinctrl_usdhc1_2: usdhc1grp-2 {
1247                                                 fsl,pins = <
1248                                                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
1249                                                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
1250                                                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1251                                                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1252                                                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1253                                                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1254                                                 >;
1255                                         };
1256                                 };
1257
1258                                 usdhc2 {
1259                                         pinctrl_usdhc2_1: usdhc2grp-1 {
1260                                                 fsl,pins = <
1261                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1262                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1263                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1264                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1265                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1266                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1267                                                         MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1268                                                         MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1269                                                         MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1270                                                         MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1271                                                 >;
1272                                         };
1273
1274                                         pinctrl_usdhc2_2: usdhc2grp-2 {
1275                                                 fsl,pins = <
1276                                                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1277                                                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1278                                                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1279                                                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1280                                                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1281                                                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1282                                                 >;
1283                                         };
1284                                 };
1285
1286                                 usdhc3 {
1287                                         pinctrl_usdhc3_1: usdhc3grp-1 {
1288                                                 fsl,pins = <
1289                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1290                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1291                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1292                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1293                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1294                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1295                                                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1296                                                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1297                                                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1298                                                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1299                                                 >;
1300                                         };
1301
1302                                         pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1303                                                 fsl,pins = <
1304                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
1305                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
1306                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1307                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1308                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1309                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1310                                                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1311                                                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1312                                                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1313                                                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1314                                                 >;
1315                                         };
1316
1317                                         pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
1318                                                 fsl,pins = <
1319                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1320                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1321                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1322                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1323                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1324                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1325                                                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1326                                                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1327                                                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1328                                                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1329                                                 >;
1330                                         };
1331
1332                                         pinctrl_usdhc3_2: usdhc3grp-2 {
1333                                                 fsl,pins = <
1334                                                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1335                                                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1336                                                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1337                                                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1338                                                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1339                                                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1340                                                 >;
1341                                         };
1342                                 };
1343
1344                                 usdhc4 {
1345                                         pinctrl_usdhc4_1: usdhc4grp-1 {
1346                                                 fsl,pins = <
1347                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1348                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1349                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1350                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1351                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1352                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1353                                                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1354                                                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1355                                                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1356                                                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1357                                                 >;
1358                                         };
1359
1360                                         pinctrl_usdhc4_2: usdhc4grp-2 {
1361                                                 fsl,pins = <
1362                                                         MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1363                                                         MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1364                                                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1365                                                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1366                                                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1367                                                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1368                                                 >;
1369                                         };
1370                                 };
1371
1372                                 weim {
1373                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
1374                                                 fsl,pins = <
1375                                                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
1376                                                 >;
1377                                         };
1378
1379                                         pinctrl_weim_nor_1: weim_norgrp-1 {
1380                                                 fsl,pins = <
1381                                                         MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
1382                                                         MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
1383                                                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1384                                                         /* data */
1385                                                         MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1386                                                         MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1387                                                         MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1388                                                         MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1389                                                         MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1390                                                         MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1391                                                         MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1392                                                         MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1393                                                         MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1394                                                         MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1395                                                         MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1396                                                         MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1397                                                         MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1398                                                         MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1399                                                         MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1400                                                         MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1401                                                         /* address */
1402                                                         MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1403                                                         MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1404                                                         MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1405                                                         MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1406                                                         MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1407                                                         MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1408                                                         MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1409                                                         MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1410                                                         MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
1411                                                         MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
1412                                                         MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
1413                                                         MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
1414                                                         MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
1415                                                         MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
1416                                                         MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
1417                                                         MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
1418                                                         MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
1419                                                         MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
1420                                                         MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
1421                                                         MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
1422                                                         MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
1423                                                         MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
1424                                                         MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
1425                                                         MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
1426                                                 >;
1427                                         };
1428                                 };
1429                         };
1430
1431                         ldb: ldb@020e0008 {
1432                                 #address-cells = <1>;
1433                                 #size-cells = <0>;
1434                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1435                                 gpr = <&gpr>;
1436                                 status = "disabled";
1437
1438                                 lvds-channel@0 {
1439                                         reg = <0>;
1440                                         status = "disabled";
1441                                 };
1442
1443                                 lvds-channel@1 {
1444                                         reg = <1>;
1445                                         status = "disabled";
1446                                 };
1447                         };
1448
1449                         dcic1: dcic@020e4000 {
1450                                 reg = <0x020e4000 0x4000>;
1451                                 interrupts = <0 124 0x04>;
1452                         };
1453
1454                         dcic2: dcic@020e8000 {
1455                                 reg = <0x020e8000 0x4000>;
1456                                 interrupts = <0 125 0x04>;
1457                         };
1458
1459                         sdma: sdma@020ec000 {
1460                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1461                                 reg = <0x020ec000 0x4000>;
1462                                 interrupts = <0 2 0x04>;
1463                                 clocks = <&clks 155>, <&clks 155>;
1464                                 clock-names = "ipg", "ahb";
1465                                 #dma-cells = <3>;
1466                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1467                         };
1468                 };
1469
1470                 aips-bus@02100000 { /* AIPS2 */
1471                         compatible = "fsl,aips-bus", "simple-bus";
1472                         #address-cells = <1>;
1473                         #size-cells = <1>;
1474                         reg = <0x02100000 0x100000>;
1475                         ranges;
1476
1477                         caam@02100000 {
1478                                 reg = <0x02100000 0x40000>;
1479                                 interrupts = <0 105 0x04 0 106 0x04>;
1480                         };
1481
1482                         aipstz@0217c000 { /* AIPSTZ2 */
1483                                 reg = <0x0217c000 0x4000>;
1484                         };
1485
1486                         usbotg: usb@02184000 {
1487                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1488                                 reg = <0x02184000 0x200>;
1489                                 interrupts = <0 43 0x04>;
1490                                 clocks = <&clks 162>;
1491                                 fsl,usbphy = <&usbphy1>;
1492                                 fsl,usbmisc = <&usbmisc 0>;
1493                                 status = "disabled";
1494                         };
1495
1496                         usbh1: usb@02184200 {
1497                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1498                                 reg = <0x02184200 0x200>;
1499                                 interrupts = <0 40 0x04>;
1500                                 clocks = <&clks 162>;
1501                                 fsl,usbphy = <&usbphy2>;
1502                                 fsl,usbmisc = <&usbmisc 1>;
1503                                 status = "disabled";
1504                         };
1505
1506                         usbh2: usb@02184400 {
1507                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1508                                 reg = <0x02184400 0x200>;
1509                                 interrupts = <0 41 0x04>;
1510                                 clocks = <&clks 162>;
1511                                 fsl,usbmisc = <&usbmisc 2>;
1512                                 status = "disabled";
1513                         };
1514
1515                         usbh3: usb@02184600 {
1516                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1517                                 reg = <0x02184600 0x200>;
1518                                 interrupts = <0 42 0x04>;
1519                                 clocks = <&clks 162>;
1520                                 fsl,usbmisc = <&usbmisc 3>;
1521                                 status = "disabled";
1522                         };
1523
1524                         usbmisc: usbmisc@02184800 {
1525                                 #index-cells = <1>;
1526                                 compatible = "fsl,imx6q-usbmisc";
1527                                 reg = <0x02184800 0x200>;
1528                                 clocks = <&clks 162>;
1529                         };
1530
1531                         fec: ethernet@02188000 {
1532                                 compatible = "fsl,imx6q-fec";
1533                                 reg = <0x02188000 0x4000>;
1534                                 interrupts = <0 118 0x04 0 119 0x04>;
1535                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1536                                 clock-names = "ipg", "ahb", "ptp";
1537                                 status = "disabled";
1538                         };
1539
1540                         mlb@0218c000 {
1541                                 reg = <0x0218c000 0x4000>;
1542                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1543                         };
1544
1545                         usdhc1: usdhc@02190000 {
1546                                 compatible = "fsl,imx6q-usdhc";
1547                                 reg = <0x02190000 0x4000>;
1548                                 interrupts = <0 22 0x04>;
1549                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1550                                 clock-names = "ipg", "ahb", "per";
1551                                 bus-width = <4>;
1552                                 status = "disabled";
1553                         };
1554
1555                         usdhc2: usdhc@02194000 {
1556                                 compatible = "fsl,imx6q-usdhc";
1557                                 reg = <0x02194000 0x4000>;
1558                                 interrupts = <0 23 0x04>;
1559                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1560                                 clock-names = "ipg", "ahb", "per";
1561                                 bus-width = <4>;
1562                                 status = "disabled";
1563                         };
1564
1565                         usdhc3: usdhc@02198000 {
1566                                 compatible = "fsl,imx6q-usdhc";
1567                                 reg = <0x02198000 0x4000>;
1568                                 interrupts = <0 24 0x04>;
1569                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1570                                 clock-names = "ipg", "ahb", "per";
1571                                 bus-width = <4>;
1572                                 status = "disabled";
1573                         };
1574
1575                         usdhc4: usdhc@0219c000 {
1576                                 compatible = "fsl,imx6q-usdhc";
1577                                 reg = <0x0219c000 0x4000>;
1578                                 interrupts = <0 25 0x04>;
1579                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1580                                 clock-names = "ipg", "ahb", "per";
1581                                 bus-width = <4>;
1582                                 status = "disabled";
1583                         };
1584
1585                         i2c1: i2c@021a0000 {
1586                                 #address-cells = <1>;
1587                                 #size-cells = <0>;
1588                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1589                                 reg = <0x021a0000 0x4000>;
1590                                 interrupts = <0 36 0x04>;
1591                                 clocks = <&clks 125>;
1592                                 status = "disabled";
1593                         };
1594
1595                         i2c2: i2c@021a4000 {
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1599                                 reg = <0x021a4000 0x4000>;
1600                                 interrupts = <0 37 0x04>;
1601                                 clocks = <&clks 126>;
1602                                 status = "disabled";
1603                         };
1604
1605                         i2c3: i2c@021a8000 {
1606                                 #address-cells = <1>;
1607                                 #size-cells = <0>;
1608                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1609                                 reg = <0x021a8000 0x4000>;
1610                                 interrupts = <0 38 0x04>;
1611                                 clocks = <&clks 127>;
1612                                 status = "disabled";
1613                         };
1614
1615                         romcp@021ac000 {
1616                                 reg = <0x021ac000 0x4000>;
1617                         };
1618
1619                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1620                                 compatible = "fsl,imx6q-mmdc";
1621                                 reg = <0x021b0000 0x4000>;
1622                         };
1623
1624                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1625                                 reg = <0x021b4000 0x4000>;
1626                         };
1627
1628                         weim: weim@021b8000 {
1629                                 compatible = "fsl,imx6q-weim";
1630                                 reg = <0x021b8000 0x4000>;
1631                                 interrupts = <0 14 0x04>;
1632                                 clocks = <&clks 196>;
1633                         };
1634
1635                         ocotp: ocotp@021bc000 {
1636                                 compatible = "fsl,imx6q-ocotp", "syscon";
1637                                 reg = <0x021bc000 0x4000>;
1638                         };
1639
1640                         tzasc@021d0000 { /* TZASC1 */
1641                                 reg = <0x021d0000 0x4000>;
1642                                 interrupts = <0 108 0x04>;
1643                         };
1644
1645                         tzasc@021d4000 { /* TZASC2 */
1646                                 reg = <0x021d4000 0x4000>;
1647                                 interrupts = <0 109 0x04>;
1648                         };
1649
1650                         audmux: audmux@021d8000 {
1651                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1652                                 reg = <0x021d8000 0x4000>;
1653                                 status = "disabled";
1654                         };
1655
1656                         mipi@021dc000 { /* MIPI-CSI */
1657                                 reg = <0x021dc000 0x4000>;
1658                         };
1659
1660                         mipi@021e0000 { /* MIPI-DSI */
1661                                 reg = <0x021e0000 0x4000>;
1662                         };
1663
1664                         vdoa@021e4000 {
1665                                 reg = <0x021e4000 0x4000>;
1666                                 interrupts = <0 18 0x04>;
1667                         };
1668
1669                         uart2: serial@021e8000 {
1670                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1671                                 reg = <0x021e8000 0x4000>;
1672                                 interrupts = <0 27 0x04>;
1673                                 clocks = <&clks 160>, <&clks 161>;
1674                                 clock-names = "ipg", "per";
1675                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1676                                 dma-names = "rx", "tx";
1677                                 status = "disabled";
1678                         };
1679
1680                         uart3: serial@021ec000 {
1681                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1682                                 reg = <0x021ec000 0x4000>;
1683                                 interrupts = <0 28 0x04>;
1684                                 clocks = <&clks 160>, <&clks 161>;
1685                                 clock-names = "ipg", "per";
1686                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1687                                 dma-names = "rx", "tx";
1688                                 status = "disabled";
1689                         };
1690
1691                         uart4: serial@021f0000 {
1692                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1693                                 reg = <0x021f0000 0x4000>;
1694                                 interrupts = <0 29 0x04>;
1695                                 clocks = <&clks 160>, <&clks 161>;
1696                                 clock-names = "ipg", "per";
1697                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1698                                 dma-names = "rx", "tx";
1699                                 status = "disabled";
1700                         };
1701
1702                         uart5: serial@021f4000 {
1703                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1704                                 reg = <0x021f4000 0x4000>;
1705                                 interrupts = <0 30 0x04>;
1706                                 clocks = <&clks 160>, <&clks 161>;
1707                                 clock-names = "ipg", "per";
1708                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1709                                 dma-names = "rx", "tx";
1710                                 status = "disabled";
1711                         };
1712                 };
1713
1714                 ipu1: ipu@02400000 {
1715                         #crtc-cells = <1>;
1716                         compatible = "fsl,imx6q-ipu";
1717                         reg = <0x02400000 0x400000>;
1718                         interrupts = <0 6 0x4 0 5 0x4>;
1719                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1720                         clock-names = "bus", "di0", "di1";
1721                         resets = <&src 2>;
1722                 };
1723         };
1724 };