arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 gpio5 = &gpio6;
  26                 gpio6 = &gpio7;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 ipu0 = &ipu1;
  31                 mmc0 = &usdhc1;
  32                 mmc1 = &usdhc2;
  33                 mmc2 = &usdhc3;
  34                 mmc3 = &usdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &ecspi3;
  43                 spi3 = &ecspi4;
  44                 usbphy0 = &usbphy1;
  45                 usbphy1 = &usbphy2;
  46         };
  47
  48         intc: interrupt-controller@00a01000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         clock-frequency = <0>;
  70                 };
  71
  72                 osc {
  73                         compatible = "fsl,imx-osc", "fixed-clock";
  74                         clock-frequency = <24000000>;
  75                 };
  76         };
  77
  78         soc {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "simple-bus";
  82                 interrupt-parent = <&intc>;
  83                 ranges;
  84
  85                 caam_sm: caam-sm@00100000 {
  86                         compatible = "fsl,imx6q-caam-sm";
  87                         reg = <0x00100000 0x3fff>;
  88                 };
  89
  90                 dma_apbh: dma-apbh@00110000 {
  91                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  92                         reg = <0x00110000 0x2000>;
  93                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  96                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  97                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  98                         #dma-cells = <1>;
  99                         dma-channels = <4>;
 100                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 101                 };
 102
 103                 irq_sec_vio: caam_secvio {
 104                         compatible = "fsl,imx6q-caam-secvio";
 105                         interrupts = <0 20 0x04>;
 106                         secvio_src = <0x8000001d>;
 107                 };
 108
 109                 gpmi: gpmi-nand@00112000 {
 110                         compatible = "fsl,imx6q-gpmi-nand";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 114                         reg-names = "gpmi-nand", "bch";
 115                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 116                         interrupt-names = "bch";
 117                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 118                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 119                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 120                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 121                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 122                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 123                                       "gpmi_bch_apb", "per1_bch";
 124                         dmas = <&dma_apbh 0>;
 125                         dma-names = "rx-tx";
 126                         status = "disabled";
 127                 };
 128
 129                 timer@00a00600 {
 130                         compatible = "arm,cortex-a9-twd-timer";
 131                         reg = <0x00a00600 0x20>;
 132                         interrupts = <1 13 0xf01>;
 133                         clocks = <&clks IMX6QDL_CLK_TWD>;
 134                 };
 135
 136                 L2: l2-cache@00a02000 {
 137                         compatible = "arm,pl310-cache";
 138                         reg = <0x00a02000 0x1000>;
 139                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 140                         cache-unified;
 141                         cache-level = <2>;
 142                         arm,tag-latency = <4 2 3>;
 143                         arm,data-latency = <4 2 3>;
 144                 };
 145
 146                 pcie: pcie@0x01000000 {
 147                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 148                         reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
 149                         reg-names = "dbi", "config";
 150                         #address-cells = <3>;
 151                         #size-cells = <2>;
 152                         device_type = "pci";
 153                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 154                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 155                         num-lanes = <1>;
 156                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 157                         interrupt-names = "msi";
 158                         #interrupt-cells = <1>;
 159                         interrupt-map-mask = <0 0 0 0x7>;
 160                         interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
 161                                         <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
 162                                         <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
 163                                         <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
 165                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 166                                  <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
 167                         clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
 168                         status = "disabled";
 169                 };
 170
 171                 pmu {
 172                         compatible = "arm,cortex-a9-pmu";
 173                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 174                 };
 175
 176                 hdmi_core: hdmi_core@00120000 {
 177                         compatible = "fsl,imx6q-hdmi-core";
 178                         reg = <0x00120000 0x9000>;
 179                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 180                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 181                                         <&clks IMX6QDL_CLK_HSI_TX>;
 182                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 183                         status = "disabled";
 184                 };
 185
 186                 hdmi_video: hdmi_video@020e0000 {
 187                         compatible = "fsl,imx6q-hdmi-video";
 188                         reg = <0x020e0000 0x1000>;
 189                         reg-names = "hdmi_gpr";
 190                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 192                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 193                                         <&clks IMX6QDL_CLK_HSI_TX>;
 194                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 195                         status = "disabled";
 196                 };
 197
 198                 hdmi_audio: hdmi_audio@00120000 {
 199                         compatible = "fsl,imx6q-hdmi-audio";
 200                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 201                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 202                                         <&clks IMX6QDL_CLK_HSI_TX>;
 203                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 204                         dmas = <&sdma 2 24 0>;
 205                         dma-names = "tx";
 206                         status = "disabled";
 207                 };
 208
 209                 hdmi_cec: hdmi_cec@00120000 {
 210                         compatible = "fsl,imx6q-hdmi-cec";
 211                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 212                         status = "disabled";
 213                 };
 214
 215                 aips-bus@02000000 { /* AIPS1 */
 216                         compatible = "fsl,aips-bus", "simple-bus";
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219                         reg = <0x02000000 0x100000>;
 220                         ranges;
 221
 222                         spba-bus@02000000 {
 223                                 compatible = "fsl,spba-bus", "simple-bus";
 224                                 #address-cells = <1>;
 225                                 #size-cells = <1>;
 226                                 reg = <0x02000000 0x40000>;
 227                                 ranges;
 228
 229                                 spdif: spdif@02004000 {
 230                                         compatible = "fsl,imx35-spdif";
 231                                         reg = <0x02004000 0x4000>;
 232                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 233                                         dmas = <&sdma 14 18 0>,
 234                                                <&sdma 15 18 0>;
 235                                         dma-names = "rx", "tx";
 236                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 237                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 238                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 239                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
 240                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 241                                         clock-names = "core",  "rxtx0",
 242                                                       "rxtx1", "rxtx2",
 243                                                       "rxtx3", "rxtx4",
 244                                                       "rxtx5", "rxtx6",
 245                                                       "rxtx7", "dma";
 246                                         status = "disabled";
 247                                 };
 248
 249                                 ecspi1: ecspi@02008000 {
 250                                         #address-cells = <1>;
 251                                         #size-cells = <0>;
 252                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 253                                         reg = <0x02008000 0x4000>;
 254                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 255                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 256                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 257                                         clock-names = "ipg", "per";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 ecspi2: ecspi@0200c000 {
 262                                         #address-cells = <1>;
 263                                         #size-cells = <0>;
 264                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 265                                         reg = <0x0200c000 0x4000>;
 266                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 267                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 268                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 269                                         clock-names = "ipg", "per";
 270                                         status = "disabled";
 271                                 };
 272
 273                                 ecspi3: ecspi@02010000 {
 274                                         #address-cells = <1>;
 275                                         #size-cells = <0>;
 276                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 277                                         reg = <0x02010000 0x4000>;
 278                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 280                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 281                                         clock-names = "ipg", "per";
 282                                         status = "disabled";
 283                                 };
 284
 285                                 ecspi4: ecspi@02014000 {
 286                                         #address-cells = <1>;
 287                                         #size-cells = <0>;
 288                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 289                                         reg = <0x02014000 0x4000>;
 290                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 291                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 292                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 293                                         clock-names = "ipg", "per";
 294                                         status = "disabled";
 295                                 };
 296
 297                                 uart1: serial@02020000 {
 298                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 299                                         reg = <0x02020000 0x4000>;
 300                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 301                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 302                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 303                                         clock-names = "ipg", "per";
 304                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 305                                         dma-names = "rx", "tx";
 306                                         status = "disabled";
 307                                 };
 308
 309                                 esai: esai@02024000 {
 310                                         compatible = "fsl,imx35-esai";
 311                                         reg = <0x02024000 0x4000>;
 312                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 313                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 314                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 315                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 316                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 317                                                  <&clks IMX6QDL_CLK_SPBA>;
 318                                         clock-names = "core", "mem", "extal", "fsys", "dma";
 319                                         dmas = <&sdma 23 21 0>,
 320                                                <&sdma 24 21 0>;
 321                                         dma-names = "rx", "tx";
 322                                         status = "disabled";
 323                                 };
 324
 325                                 ssi1: ssi@02028000 {
 326                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 327                                         reg = <0x02028000 0x4000>;
 328                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 329                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 330                                                  <&clks IMX6QDL_CLK_SSI1>;
 331                                         clock-names = "ipg", "baud";
 332                                         dmas = <&sdma 37 1 0>,
 333                                                <&sdma 38 1 0>;
 334                                         dma-names = "rx", "tx";
 335                                         fsl,fifo-depth = <15>;
 336                                         fsl,ssi-dma-events = <38 37>;
 337                                         status = "disabled";
 338                                 };
 339
 340                                 ssi2: ssi@0202c000 {
 341                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 342                                         reg = <0x0202c000 0x4000>;
 343                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 344                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 345                                                  <&clks IMX6QDL_CLK_SSI2>;
 346                                         clock-names = "ipg", "baud";
 347                                         dmas = <&sdma 41 1 0>,
 348                                                <&sdma 42 1 0>;
 349                                         dma-names = "rx", "tx";
 350                                         fsl,fifo-depth = <15>;
 351                                         fsl,ssi-dma-events = <42 41>;
 352                                         status = "disabled";
 353                                 };
 354
 355                                 ssi3: ssi@02030000 {
 356                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 357                                         reg = <0x02030000 0x4000>;
 358                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 359                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 360                                                  <&clks IMX6QDL_CLK_SSI3>;
 361                                         clock-names = "ipg", "baud";
 362                                         dmas = <&sdma 45 1 0>,
 363                                                <&sdma 46 1 0>;
 364                                         dma-names = "rx", "tx";
 365                                         fsl,fifo-depth = <15>;
 366                                         fsl,ssi-dma-events = <46 45>;
 367                                         status = "disabled";
 368                                 };
 369
 370                                 asrc: asrc@02034000 {
 371                                         compatible = "fsl,imx53-asrc";
 372                                         reg = <0x02034000 0x4000>;
 373                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 374                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 375                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 376                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 377                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 378                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 379                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 380                                                 <&clks IMX6QDL_CLK_SPBA>;
 381                                         clock-names = "mem", "ipg", "asrck_0",
 382                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 383                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 384                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 385                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 386                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 387                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 388                                         dma-names = "rxa", "rxb", "rxc",
 389                                                 "txa", "txb", "txc";
 390                                         fsl,asrc-rate  = <48000>;
 391                                         fsl,asrc-width = <16>;
 392                                         status = "okay";
 393                                 };
 394
 395                                 spba@0203c000 {
 396                                         reg = <0x0203c000 0x4000>;
 397                                 };
 398                         };
 399
 400                         vpu: vpu@02040000 {
 401                                 compatible = "fsl,imx6-vpu";
 402                                 reg = <0x02040000 0x3c000>;
 403                                 reg-names = "vpu_regs";
 404                                 interrupts = <0 3 IRQ_TYPE_EDGE_RISING>,
 405                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 406                                 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
 407                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 408                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
 409                                          <&clks IMX6QDL_CLK_OCRAM>;
 410                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 411                                 iramsize = <0x21000>;
 412                                 iram = <&ocram>;
 413                                 resets = <&src 1>;
 414                                 power-domains = <&gpc 1>;
 415                         };
 416
 417                         aipstz@0207c000 { /* AIPSTZ1 */
 418                                 reg = <0x0207c000 0x4000>;
 419                         };
 420
 421                         pwm1: pwm@02080000 {
 422                                 #pwm-cells = <2>;
 423                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 424                                 reg = <0x02080000 0x4000>;
 425                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 427                                          <&clks IMX6QDL_CLK_PWM1>;
 428                                 clock-names = "ipg", "per";
 429                         };
 430
 431                         pwm2: pwm@02084000 {
 432                                 #pwm-cells = <2>;
 433                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 434                                 reg = <0x02084000 0x4000>;
 435                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 436                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 437                                          <&clks IMX6QDL_CLK_PWM2>;
 438                                 clock-names = "ipg", "per";
 439                         };
 440
 441                         pwm3: pwm@02088000 {
 442                                 #pwm-cells = <2>;
 443                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 444                                 reg = <0x02088000 0x4000>;
 445                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 446                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 447                                          <&clks IMX6QDL_CLK_PWM3>;
 448                                 clock-names = "ipg", "per";
 449                         };
 450
 451                         pwm4: pwm@0208c000 {
 452                                 #pwm-cells = <2>;
 453                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 454                                 reg = <0x0208c000 0x4000>;
 455                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 457                                          <&clks IMX6QDL_CLK_PWM4>;
 458                                 clock-names = "ipg", "per";
 459                         };
 460
 461                         flexcan1: can@02090000 {
 462                                 compatible = "fsl,imx6q-flexcan";
 463                                 reg = <0x02090000 0x4000>;
 464                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 465                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 466                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 467                                 clock-names = "ipg", "per";
 468                                 stop-mode = <&gpr 0x34 28 0x10 17>;
 469                                 status = "disabled";
 470                         };
 471
 472                         flexcan2: can@02094000 {
 473                                 compatible = "fsl,imx6q-flexcan";
 474                                 reg = <0x02094000 0x4000>;
 475                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 476                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 477                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 478                                 clock-names = "ipg", "per";
 479                                 stop-mode = <&gpr 0x34 29 0x10 18>;
 480                                 status = "disabled";
 481                         };
 482
 483                         gpt: gpt@02098000 {
 484                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 485                                 reg = <0x02098000 0x4000>;
 486                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 487                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 488                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 489                                 clock-names = "ipg", "per";
 490                         };
 491
 492                         gpio1: gpio@0209c000 {
 493                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 494                                 reg = <0x0209c000 0x4000>;
 495                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 496                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 497                                 gpio-controller;
 498                                 #gpio-cells = <2>;
 499                                 interrupt-controller;
 500                                 #interrupt-cells = <2>;
 501                         };
 502
 503                         gpio2: gpio@020a0000 {
 504                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 505                                 reg = <0x020a0000 0x4000>;
 506                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 508                                 gpio-controller;
 509                                 #gpio-cells = <2>;
 510                                 interrupt-controller;
 511                                 #interrupt-cells = <2>;
 512                         };
 513
 514                         gpio3: gpio@020a4000 {
 515                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 516                                 reg = <0x020a4000 0x4000>;
 517                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 519                                 gpio-controller;
 520                                 #gpio-cells = <2>;
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <2>;
 523                         };
 524
 525                         gpio4: gpio@020a8000 {
 526                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 527                                 reg = <0x020a8000 0x4000>;
 528                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 529                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 530                                 gpio-controller;
 531                                 #gpio-cells = <2>;
 532                                 interrupt-controller;
 533                                 #interrupt-cells = <2>;
 534                         };
 535
 536                         gpio5: gpio@020ac000 {
 537                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 538                                 reg = <0x020ac000 0x4000>;
 539                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 541                                 gpio-controller;
 542                                 #gpio-cells = <2>;
 543                                 interrupt-controller;
 544                                 #interrupt-cells = <2>;
 545                         };
 546
 547                         gpio6: gpio@020b0000 {
 548                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 549                                 reg = <0x020b0000 0x4000>;
 550                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 551                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 552                                 gpio-controller;
 553                                 #gpio-cells = <2>;
 554                                 interrupt-controller;
 555                                 #interrupt-cells = <2>;
 556                         };
 557
 558                         gpio7: gpio@020b4000 {
 559                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 560                                 reg = <0x020b4000 0x4000>;
 561                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 562                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 563                                 gpio-controller;
 564                                 #gpio-cells = <2>;
 565                                 interrupt-controller;
 566                                 #interrupt-cells = <2>;
 567                         };
 568
 569                         kpp: kpp@020b8000 {
 570                                 reg = <0x020b8000 0x4000>;
 571                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 572                         };
 573
 574                         wdog1: wdog@020bc000 {
 575                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 576                                 reg = <0x020bc000 0x4000>;
 577                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 578                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 579                         };
 580
 581                         wdog2: wdog@020c0000 {
 582                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 583                                 reg = <0x020c0000 0x4000>;
 584                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 586                                 status = "disabled";
 587                         };
 588
 589                         clks: ccm@020c4000 {
 590                                 compatible = "fsl,imx6q-ccm";
 591                                 reg = <0x020c4000 0x4000>;
 592                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 593                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 594                                 #clock-cells = <1>;
 595                         };
 596
 597                         anatop: anatop@020c8000 {
 598                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 599                                 reg = <0x020c8000 0x1000>;
 600                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 601                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 602                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 603
 604                                 regulator-1p1@110 {
 605                                         compatible = "fsl,anatop-regulator";
 606                                         regulator-name = "vdd1p1";
 607                                         regulator-min-microvolt = <800000>;
 608                                         regulator-max-microvolt = <1375000>;
 609                                         regulator-always-on;
 610                                         anatop-reg-offset = <0x110>;
 611                                         anatop-vol-bit-shift = <8>;
 612                                         anatop-vol-bit-width = <5>;
 613                                         anatop-min-bit-val = <4>;
 614                                         anatop-min-voltage = <800000>;
 615                                         anatop-max-voltage = <1375000>;
 616                                 };
 617
 618                                 regulator-3p0@120 {
 619                                         compatible = "fsl,anatop-regulator";
 620                                         regulator-name = "vdd3p0";
 621                                         regulator-min-microvolt = <2800000>;
 622                                         regulator-max-microvolt = <3150000>;
 623                                         regulator-always-on;
 624                                         anatop-reg-offset = <0x120>;
 625                                         anatop-vol-bit-shift = <8>;
 626                                         anatop-vol-bit-width = <5>;
 627                                         anatop-min-bit-val = <0>;
 628                                         anatop-min-voltage = <2625000>;
 629                                         anatop-max-voltage = <3400000>;
 630                                 };
 631
 632                                 regulator-2p5@130 {
 633                                         compatible = "fsl,anatop-regulator";
 634                                         regulator-name = "vdd2p5";
 635                                         regulator-min-microvolt = <2000000>;
 636                                         regulator-max-microvolt = <2750000>;
 637                                         regulator-always-on;
 638                                         anatop-reg-offset = <0x130>;
 639                                         anatop-vol-bit-shift = <8>;
 640                                         anatop-vol-bit-width = <5>;
 641                                         anatop-min-bit-val = <0>;
 642                                         anatop-min-voltage = <2000000>;
 643                                         anatop-max-voltage = <2750000>;
 644                                 };
 645
 646                                 reg_arm: regulator-vddcore@140 {
 647                                         compatible = "fsl,anatop-regulator";
 648                                         regulator-name = "vddarm";
 649                                         regulator-min-microvolt = <725000>;
 650                                         regulator-max-microvolt = <1450000>;
 651                                         regulator-always-on;
 652                                         anatop-reg-offset = <0x140>;
 653                                         anatop-vol-bit-shift = <0>;
 654                                         anatop-vol-bit-width = <5>;
 655                                         anatop-delay-reg-offset = <0x170>;
 656                                         anatop-delay-bit-shift = <24>;
 657                                         anatop-delay-bit-width = <2>;
 658                                         anatop-min-bit-val = <1>;
 659                                         anatop-min-voltage = <725000>;
 660                                         anatop-max-voltage = <1450000>;
 661                                         regulator-allow-bypass;
 662                                 };
 663
 664                                 reg_pu: regulator-vddpu@140 {
 665                                         compatible = "fsl,anatop-regulator";
 666                                         regulator-name = "vddpu";
 667                                         regulator-min-microvolt = <725000>;
 668                                         regulator-max-microvolt = <1450000>;
 669                                         regulator-enable-ramp-delay = <150>;
 670                                         regulator-boot-on;
 671                                         anatop-reg-offset = <0x140>;
 672                                         anatop-vol-bit-shift = <9>;
 673                                         anatop-vol-bit-width = <5>;
 674                                         anatop-delay-reg-offset = <0x170>;
 675                                         anatop-delay-bit-shift = <26>;
 676                                         anatop-delay-bit-width = <2>;
 677                                         anatop-min-bit-val = <1>;
 678                                         anatop-min-voltage = <725000>;
 679                                         anatop-max-voltage = <1450000>;
 680                                         regulator-allow-bypass;
 681                                 };
 682
 683                                 reg_soc: regulator-vddsoc@140 {
 684                                         compatible = "fsl,anatop-regulator";
 685                                         regulator-name = "vddsoc";
 686                                         regulator-min-microvolt = <725000>;
 687                                         regulator-max-microvolt = <1450000>;
 688                                         regulator-always-on;
 689                                         anatop-reg-offset = <0x140>;
 690                                         anatop-vol-bit-shift = <18>;
 691                                         anatop-vol-bit-width = <5>;
 692                                         anatop-delay-reg-offset = <0x170>;
 693                                         anatop-delay-bit-shift = <28>;
 694                                         anatop-delay-bit-width = <2>;
 695                                         anatop-min-bit-val = <1>;
 696                                         anatop-min-voltage = <725000>;
 697                                         anatop-max-voltage = <1450000>;
 698                                         regulator-allow-bypass;
 699                                 };
 700                         };
 701
 702                         tempmon: tempmon {
 703                                 compatible = "fsl,imx6q-tempmon";
 704                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 705                                 fsl,tempmon = <&anatop>;
 706                                 fsl,tempmon-data = <&ocotp>;
 707                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 708                         };
 709
 710                         usbphy1: usbphy@020c9000 {
 711                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 712                                 reg = <0x020c9000 0x1000>;
 713                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 715                                 fsl,anatop = <&anatop>;
 716                         };
 717
 718                         usbphy2: usbphy@020ca000 {
 719                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 720                                 reg = <0x020ca000 0x1000>;
 721                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 722                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 723                                 fsl,anatop = <&anatop>;
 724                         };
 725
 726                         usbphy_nop1: usbphy_nop1 {
 727                                 compatible = "usb-nop-xceiv";
 728                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 729                                 clock-names = "main_clk";
 730                         };
 731
 732                         usbphy_nop2: usbphy_nop2 {
 733                                 compatible = "usb-nop-xceiv";
 734                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 735                                 clock-names = "main_clk";
 736                         };
 737
 738                         caam_snvs: caam-snvs@020cc000 {
 739                                 compatible = "fsl,imx6q-caam-snvs";
 740                                 reg = <0x020cc000 0x4000>;
 741                         };
 742
 743                         snvs@020cc000 {
 744                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 745                                 #address-cells = <1>;
 746                                 #size-cells = <1>;
 747                                 ranges = <0 0x020cc000 0x4000>;
 748
 749                                 snvs-rtc-lp@34 {
 750                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 751                                         reg = <0x34 0x58>;
 752                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 753                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 754                                 };
 755                         };
 756
 757                         epit1: epit@020d0000 { /* EPIT1 */
 758                                 reg = <0x020d0000 0x4000>;
 759                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 760                         };
 761
 762                         epit2: epit@020d4000 { /* EPIT2 */
 763                                 reg = <0x020d4000 0x4000>;
 764                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 765                         };
 766
 767                         src: src@020d8000 {
 768                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 769                                 reg = <0x020d8000 0x4000>;
 770                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 771                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 772                                 #reset-cells = <1>;
 773                         };
 774
 775                         gpc: gpc@020dc000 {
 776                                 compatible = "fsl,imx6q-gpc";
 777                                 reg = <0x020dc000 0x4000>;
 778                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 779                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 780                                 pu-supply = <&reg_pu>;
 781                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 782                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 783                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 784                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 785                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 786                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 787                                 #power-domain-cells = <1>;
 788                         };
 789
 790                         gpr: iomuxc-gpr@020e0000 {
 791                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 792                                 reg = <0x020e0000 0x38>;
 793                         };
 794
 795                         iomuxc: iomuxc@020e0000 {
 796                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 797                                 reg = <0x020e0000 0x4000>;
 798                         };
 799
 800                         ldb: ldb@020e0008 {
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 gpr = <&gpr>;
 804                                 status = "disabled";
 805
 806                                 lvds-channel@0 {
 807                                         reg = <0>;
 808                                         status = "disabled";
 809                                 };
 810
 811                                 lvds-channel@1 {
 812                                         reg = <1>;
 813                                         status = "disabled";
 814                                 };
 815                         };
 816
 817                         dcic1: dcic@020e4000 {
 818                                 compatible = "fsl,imx6q-dcic";
 819                                 reg = <0x020e4000 0x4000>;
 820                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
 822                                 clock-names = "dcic", "disp-axi";
 823                                 gpr = <&gpr>;
 824                                 status = "disabled";
 825                         };
 826
 827                         dcic2: dcic@020e8000 {
 828                                 compatible = "fsl,imx6q-dcic";
 829                                 reg = <0x020e8000 0x4000>;
 830                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
 832                                 clock-names = "dcic", "disp-axi";
 833                                 gpr = <&gpr>;
 834                                 status = "disabled";
 835                         };
 836
 837                         sdma: sdma@020ec000 {
 838                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 839                                 reg = <0x020ec000 0x4000>;
 840                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 842                                          <&clks IMX6QDL_CLK_SDMA>;
 843                                 clock-names = "ipg", "ahb";
 844                                 #dma-cells = <3>;
 845                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 846                         };
 847                 };
 848
 849                 aips-bus@02100000 { /* AIPS2 */
 850                         compatible = "fsl,aips-bus", "simple-bus";
 851                         #address-cells = <1>;
 852                         #size-cells = <1>;
 853                         reg = <0x02100000 0x100000>;
 854                         ranges;
 855
 856                         crypto: caam@2100000 {
 857                                 compatible = "fsl,sec-v4.0";
 858                                 #address-cells = <1>;
 859                                 #size-cells = <1>;
 860                                 reg = <0x2100000 0x40000>;
 861                                 ranges = <0 0x2100000 0x40000>;
 862                                 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
 863                                 clocks = <&clks IMX6QDL_CAAM_MEM>, <&clks IMX6QDL_CAAM_ACLK>, <&clks IMX6QDL_CAAM_IPG> ,<&clks IMX6QDL_CLK_EIM_SLOW>;
 864                                 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
 865
 866                                 sec_jr0: jr0@1000 {
 867                                         compatible = "fsl,sec-v4.0-job-ring";
 868                                         reg = <0x1000 0x1000>;
 869                                         interrupt-parent = <&intc>;
 870                                         interrupts = <0 105 0x4>;
 871                                 };
 872
 873                                 sec_jr1: jr1@2000 {
 874                                         compatible = "fsl,sec-v4.0-job-ring";
 875                                         reg = <0x2000 0x1000>;
 876                                         interrupt-parent = <&intc>;
 877                                         interrupts = <0 106 0x4>;
 878                                 };
 879                         };
 880
 881                         aipstz@0217c000 { /* AIPSTZ2 */
 882                                 reg = <0x0217c000 0x4000>;
 883                         };
 884
 885                         usbotg: usb@02184000 {
 886                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 887                                 reg = <0x02184000 0x200>;
 888                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 890                                 fsl,usbphy = <&usbphy1>;
 891                                 fsl,usbmisc = <&usbmisc 0>;
 892                                 fsl,anatop = <&anatop>;
 893                                 status = "disabled";
 894                         };
 895
 896                         usbh1: usb@02184200 {
 897                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 898                                 reg = <0x02184200 0x200>;
 899                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 900                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 901                                 fsl,usbphy = <&usbphy2>;
 902                                 fsl,usbmisc = <&usbmisc 1>;
 903                                 status = "disabled";
 904                         };
 905
 906                         usbh2: usb@02184400 {
 907                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 908                                 reg = <0x02184400 0x200>;
 909                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 910                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 911                                 fsl,usbmisc = <&usbmisc 2>;
 912                                 phy_type = "hsic";
 913                                 fsl,usbphy = <&usbphy_nop1>;
 914                                 fsl,anatop = <&anatop>;
 915                                 status = "disabled";
 916                         };
 917
 918                         usbh3: usb@02184600 {
 919                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 920                                 reg = <0x02184600 0x200>;
 921                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 922                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 923                                 fsl,usbmisc = <&usbmisc 3>;
 924                                 phy_type = "hsic";
 925                                 fsl,usbphy = <&usbphy_nop2>;
 926                                 fsl,anatop = <&anatop>;
 927                                 status = "disabled";
 928                         };
 929
 930                         usbmisc: usbmisc@02184800 {
 931                                 #index-cells = <1>;
 932                                 compatible = "fsl,imx6q-usbmisc";
 933                                 reg = <0x02184800 0x200>;
 934                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 935                         };
 936
 937                         fec: ethernet@02188000 {
 938                                 compatible = "fsl,imx6q-fec";
 939                                 reg = <0x02188000 0x4000>;
 940                                 interrupts-extended =
 941                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 942                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 943                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 944                                          <&clks IMX6QDL_CLK_ENET>,
 945                                          <&clks IMX6QDL_CLK_ENET_REF>;
 946                                 clock-names = "ipg", "ahb", "ptp";
 947                                 status = "disabled";
 948                         };
 949
 950                         mlb: mlb@0218c000 {
 951                                 compatible = "fsl,imx6q-mlb150";
 952                                 reg = <0x0218c000 0x4000>;
 953                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 954                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 955                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 956                                 clocks = <&clks IMX6QDL_CLK_MLB>,
 957                                          <&clks IMX6QDL_CLK_PLL8_MLB>;
 958                                 clock-names = "mlb", "pll8_mlb";
 959                                 iram = <&ocram>;
 960                                 status = "disabled";
 961                         };
 962
 963                         usdhc1: usdhc@02190000 {
 964                                 compatible = "fsl,imx6q-usdhc";
 965                                 reg = <0x02190000 0x4000>;
 966                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 968                                          <&clks IMX6QDL_CLK_USDHC1>,
 969                                          <&clks IMX6QDL_CLK_USDHC1>;
 970                                 clock-names = "ipg", "ahb", "per";
 971                                 bus-width = <4>;
 972                                 status = "disabled";
 973                         };
 974
 975                         usdhc2: usdhc@02194000 {
 976                                 compatible = "fsl,imx6q-usdhc";
 977                                 reg = <0x02194000 0x4000>;
 978                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 979                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 980                                          <&clks IMX6QDL_CLK_USDHC2>,
 981                                          <&clks IMX6QDL_CLK_USDHC2>;
 982                                 clock-names = "ipg", "ahb", "per";
 983                                 bus-width = <4>;
 984                                 status = "disabled";
 985                         };
 986
 987                         usdhc3: usdhc@02198000 {
 988                                 compatible = "fsl,imx6q-usdhc";
 989                                 reg = <0x02198000 0x4000>;
 990                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 991                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 992                                          <&clks IMX6QDL_CLK_USDHC3>,
 993                                          <&clks IMX6QDL_CLK_USDHC3>;
 994                                 clock-names = "ipg", "ahb", "per";
 995                                 bus-width = <4>;
 996                                 status = "disabled";
 997                         };
 998
 999                         usdhc4: usdhc@0219c000 {
1000                                 compatible = "fsl,imx6q-usdhc";
1001                                 reg = <0x0219c000 0x4000>;
1002                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1003                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1004                                          <&clks IMX6QDL_CLK_USDHC4>,
1005                                          <&clks IMX6QDL_CLK_USDHC4>;
1006                                 clock-names = "ipg", "ahb", "per";
1007                                 bus-width = <4>;
1008                                 status = "disabled";
1009                         };
1010
1011                         i2c1: i2c@021a0000 {
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1015                                 reg = <0x021a0000 0x4000>;
1016                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1018                                 status = "disabled";
1019                         };
1020
1021                         i2c2: i2c@021a4000 {
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1025                                 reg = <0x021a4000 0x4000>;
1026                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1028                                 status = "disabled";
1029                         };
1030
1031                         i2c3: i2c@021a8000 {
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1035                                 reg = <0x021a8000 0x4000>;
1036                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1037                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1038                                 status = "disabled";
1039                         };
1040
1041                         romcp@021ac000 {
1042                                 reg = <0x021ac000 0x4000>;
1043                         };
1044
1045                         mmdc0-1@021b0000 { /* MMDC0-1 */
1046                                 compatible = "fsl,imx6q-mmdc-combine";
1047                                 reg = <0x021b0000 0x8000>;
1048                         };
1049
1050                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1051                                 compatible = "fsl,imx6q-mmdc";
1052                                 reg = <0x021b0000 0x4000>;
1053                         };
1054
1055                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1056                                 reg = <0x021b4000 0x4000>;
1057                         };
1058
1059                         weim: weim@021b8000 {
1060                                 compatible = "fsl,imx6q-weim";
1061                                 reg = <0x021b8000 0x4000>;
1062                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1063                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1064                         };
1065
1066                         ocotp: ocotp-ctrl@021bc000 {
1067                                 compatible = "syscon";
1068                                 reg = <0x021bc000 0x4000>;
1069                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1070                         };
1071
1072                         ocotp-fuse@021bc000 {
1073                                 compatible = "fsl,imx6q-ocotp";
1074                                 reg = <0x021bc000 0x4000>;
1075                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1076                         };
1077
1078                         tzasc@021d0000 { /* TZASC1 */
1079                                 reg = <0x021d0000 0x4000>;
1080                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1081                         };
1082
1083                         tzasc@021d4000 { /* TZASC2 */
1084                                 reg = <0x021d4000 0x4000>;
1085                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1086                         };
1087
1088                         audmux: audmux@021d8000 {
1089                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1090                                 reg = <0x021d8000 0x4000>;
1091                                 status = "disabled";
1092                         };
1093
1094                         mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */
1095                                 compatible = "fsl,imx6q-mipi-csi2";
1096                                 reg = <0x021dc000 0x4000>;
1097                                 interrupts = <0 100 0x04>, <0 101 0x04>;
1098                                 clocks = <&clks 138>, <&clks 53>, <&clks 204>;
1099                                 /* Note: clks 138 is hsi_tx, however, the dphy_c
1100                                  * hsi_tx and pll_refclk use the same clk gate.
1101                                  * In current clk driver, open/close clk gate do
1102                                  * use hsi_tx for a temporary debug purpose.
1103                                  */
1104                                 clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
1105                                 status = "disabled";
1106                         };
1107
1108                         mipi@021e0000 { /* MIPI-DSI */
1109                                 reg = <0x021e0000 0x4000>;
1110                         };
1111
1112                         vdoa@021e4000 {
1113                                 compatible = "fsl,imx6q-vdoa";
1114                                 reg = <0x021e4000 0x4000>;
1115                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1116                                 clocks = <&clks IMX6QDL_CLK_VDOA>;
1117                                 iram = <&ocram>;
1118                         };
1119
1120                         uart2: serial@021e8000 {
1121                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1122                                 reg = <0x021e8000 0x4000>;
1123                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1124                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1125                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1126                                 clock-names = "ipg", "per";
1127                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1128                                 dma-names = "rx", "tx";
1129                                 status = "disabled";
1130                         };
1131
1132                         uart3: serial@021ec000 {
1133                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1134                                 reg = <0x021ec000 0x4000>;
1135                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1136                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1137                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1138                                 clock-names = "ipg", "per";
1139                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1140                                 dma-names = "rx", "tx";
1141                                 status = "disabled";
1142                         };
1143
1144                         uart4: serial@021f0000 {
1145                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1146                                 reg = <0x021f0000 0x4000>;
1147                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1148                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1149                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1150                                 clock-names = "ipg", "per";
1151                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1152                                 dma-names = "rx", "tx";
1153                                 status = "disabled";
1154                         };
1155
1156                         uart5: serial@021f4000 {
1157                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1158                                 reg = <0x021f4000 0x4000>;
1159                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1160                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1161                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1162                                 clock-names = "ipg", "per";
1163                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1164                                 dma-names = "rx", "tx";
1165                                 status = "disabled";
1166                         };
1167                 };
1168
1169                 ipu1: ipu@02400000 {
1170                         compatible = "fsl,imx6q-ipu";
1171                         reg = <0x02400000 0x400000>;
1172                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1173                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1174                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1175                                  <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
1176                                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
1177                                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
1178                         clock-names = "bus",
1179                                       "di0", "di1",
1180                                       "di0_sel", "di1_sel",
1181                                       "ldb_di0", "ldb_di1";
1182                         resets = <&src 2>;
1183                         bypass_reset = <0>;
1184                 };
1185         };
1186 };