arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 gpio5 = &gpio6;
  26                 gpio6 = &gpio7;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 ipu0 = &ipu1;
  31                 mmc0 = &usdhc1;
  32                 mmc1 = &usdhc2;
  33                 mmc2 = &usdhc3;
  34                 mmc3 = &usdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &ecspi3;
  43                 spi3 = &ecspi4;
  44                 usbphy0 = &usbphy1;
  45                 usbphy1 = &usbphy2;
  46         };
  47
  48         intc: interrupt-controller@00a01000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         clock-frequency = <0>;
  70                 };
  71
  72                 osc {
  73                         compatible = "fsl,imx-osc", "fixed-clock";
  74                         clock-frequency = <24000000>;
  75                 };
  76         };
  77
  78         soc {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "simple-bus";
  82                 interrupt-parent = <&intc>;
  83                 ranges;
  84
  85                 caam_sm: caam-sm@00100000 {
  86                         compatible = "fsl,imx6q-caam-sm";
  87                         reg = <0x00100000 0x3fff>;
  88                 };
  89
  90                 dma_apbh: dma-apbh@00110000 {
  91                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  92                         reg = <0x00110000 0x2000>;
  93                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  96                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  97                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  98                         #dma-cells = <1>;
  99                         dma-channels = <4>;
 100                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 101                 };
 102
 103                 irq_sec_vio: caam_secvio {
 104                         compatible = "fsl,imx6q-caam-secvio";
 105                         interrupts = <0 20 0x04>;
 106                         secvio_src = <0x8000001d>;
 107                 };
 108
 109                 gpmi: gpmi-nand@00112000 {
 110                         compatible = "fsl,imx6q-gpmi-nand";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 114                         reg-names = "gpmi-nand", "bch";
 115                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 116                         interrupt-names = "bch";
 117                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 118                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 119                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 120                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 121                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 122                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 123                                       "gpmi_bch_apb", "per1_bch";
 124                         dmas = <&dma_apbh 0>;
 125                         dma-names = "rx-tx";
 126                         status = "disabled";
 127                 };
 128
 129                 timer@00a00600 {
 130                         compatible = "arm,cortex-a9-twd-timer";
 131                         reg = <0x00a00600 0x20>;
 132                         interrupts = <1 13 0xf01>;
 133                         clocks = <&clks IMX6QDL_CLK_TWD>;
 134                 };
 135
 136                 L2: l2-cache@00a02000 {
 137                         compatible = "arm,pl310-cache";
 138                         reg = <0x00a02000 0x1000>;
 139                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 140                         cache-unified;
 141                         cache-level = <2>;
 142                         arm,tag-latency = <4 2 3>;
 143                         arm,data-latency = <4 2 3>;
 144                 };
 145
 146                 pcie: pcie@0x01000000 {
 147                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 148                         reg = <0x01ffc000 0x4000>; /* DBI */
 149                         #address-cells = <3>;
 150                         #size-cells = <2>;
 151                         device_type = "pci";
 152                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 153                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 154                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 155                         num-lanes = <1>;
 156                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_CLK_SATA_REF_100M>,
 158                                  <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
 159                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 160                         status = "disabled";
 161                 };
 162
 163                 pmu {
 164                         compatible = "arm,cortex-a9-pmu";
 165                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 166                 };
 167
 168                 hdmi_core: hdmi_core@00120000 {
 169                         compatible = "fsl,imx6q-hdmi-core";
 170                         reg = <0x00120000 0x9000>;
 171                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 172                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 173                                         <&clks IMX6QDL_CLK_HSI_TX>;
 174                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 175                         status = "disabled";
 176                 };
 177
 178                 hdmi_video: hdmi_video@020e0000 {
 179                         compatible = "fsl,imx6q-hdmi-video";
 180                         reg = <0x020e0000 0x1000>;
 181                         reg-names = "hdmi_gpr";
 182                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 184                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 185                                         <&clks IMX6QDL_CLK_HSI_TX>;
 186                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 187                         status = "disabled";
 188                 };
 189
 190                 hdmi_audio: hdmi_audio@00120000 {
 191                         compatible = "fsl,imx6q-hdmi-audio";
 192                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 193                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 194                                         <&clks IMX6QDL_CLK_HSI_TX>;
 195                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 196                         dmas = <&sdma 2 24 0>;
 197                         dma-names = "tx";
 198                         status = "disabled";
 199                 };
 200
 201                 hdmi_cec: hdmi_cec@00120000 {
 202                         compatible = "fsl,imx6q-hdmi-cec";
 203                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 204                         status = "disabled";
 205                 };
 206
 207                 aips-bus@02000000 { /* AIPS1 */
 208                         compatible = "fsl,aips-bus", "simple-bus";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         reg = <0x02000000 0x100000>;
 212                         ranges;
 213
 214                         spba-bus@02000000 {
 215                                 compatible = "fsl,spba-bus", "simple-bus";
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 reg = <0x02000000 0x40000>;
 219                                 ranges;
 220
 221                                 spdif: spdif@02004000 {
 222                                         compatible = "fsl,imx35-spdif";
 223                                         reg = <0x02004000 0x4000>;
 224                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 225                                         dmas = <&sdma 14 18 0>,
 226                                                <&sdma 15 18 0>;
 227                                         dma-names = "rx", "tx";
 228                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 229                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 230                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 231                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
 232                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 233                                         clock-names = "core",  "rxtx0",
 234                                                       "rxtx1", "rxtx2",
 235                                                       "rxtx3", "rxtx4",
 236                                                       "rxtx5", "rxtx6",
 237                                                       "rxtx7", "dma";
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ecspi1: ecspi@02008000 {
 242                                         #address-cells = <1>;
 243                                         #size-cells = <0>;
 244                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 245                                         reg = <0x02008000 0x4000>;
 246                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 248                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 249                                         clock-names = "ipg", "per";
 250                                         status = "disabled";
 251                                 };
 252
 253                                 ecspi2: ecspi@0200c000 {
 254                                         #address-cells = <1>;
 255                                         #size-cells = <0>;
 256                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 257                                         reg = <0x0200c000 0x4000>;
 258                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 259                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 260                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 261                                         clock-names = "ipg", "per";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 ecspi3: ecspi@02010000 {
 266                                         #address-cells = <1>;
 267                                         #size-cells = <0>;
 268                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 269                                         reg = <0x02010000 0x4000>;
 270                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 271                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 272                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 273                                         clock-names = "ipg", "per";
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ecspi4: ecspi@02014000 {
 278                                         #address-cells = <1>;
 279                                         #size-cells = <0>;
 280                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 281                                         reg = <0x02014000 0x4000>;
 282                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 283                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 284                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 285                                         clock-names = "ipg", "per";
 286                                         status = "disabled";
 287                                 };
 288
 289                                 uart1: serial@02020000 {
 290                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 291                                         reg = <0x02020000 0x4000>;
 292                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 293                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 294                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 295                                         clock-names = "ipg", "per";
 296                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 297                                         dma-names = "rx", "tx";
 298                                         status = "disabled";
 299                                 };
 300
 301                                 esai: esai@02024000 {
 302                                         compatible = "fsl,imx35-esai";
 303                                         reg = <0x02024000 0x4000>;
 304                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 305                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 306                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 307                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 308                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 309                                                  <&clks IMX6QDL_CLK_SPBA>;
 310                                         clock-names = "core", "mem", "extal", "fsys", "dma";
 311                                         dmas = <&sdma 23 21 0>,
 312                                                <&sdma 24 21 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 ssi1: ssi@02028000 {
 318                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 319                                         reg = <0x02028000 0x4000>;
 320                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 322                                                  <&clks IMX6QDL_CLK_SSI1>;
 323                                         clock-names = "ipg", "baud";
 324                                         dmas = <&sdma 37 1 0>,
 325                                                <&sdma 38 1 0>;
 326                                         dma-names = "rx", "tx";
 327                                         fsl,fifo-depth = <15>;
 328                                         fsl,ssi-dma-events = <38 37>;
 329                                         status = "disabled";
 330                                 };
 331
 332                                 ssi2: ssi@0202c000 {
 333                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 334                                         reg = <0x0202c000 0x4000>;
 335                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 336                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 337                                                  <&clks IMX6QDL_CLK_SSI2>;
 338                                         clock-names = "ipg", "baud";
 339                                         dmas = <&sdma 41 1 0>,
 340                                                <&sdma 42 1 0>;
 341                                         dma-names = "rx", "tx";
 342                                         fsl,fifo-depth = <15>;
 343                                         fsl,ssi-dma-events = <42 41>;
 344                                         status = "disabled";
 345                                 };
 346
 347                                 ssi3: ssi@02030000 {
 348                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 349                                         reg = <0x02030000 0x4000>;
 350                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 351                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 352                                                  <&clks IMX6QDL_CLK_SSI3>;
 353                                         clock-names = "ipg", "baud";
 354                                         dmas = <&sdma 45 1 0>,
 355                                                <&sdma 46 1 0>;
 356                                         dma-names = "rx", "tx";
 357                                         fsl,fifo-depth = <15>;
 358                                         fsl,ssi-dma-events = <46 45>;
 359                                         status = "disabled";
 360                                 };
 361
 362                                 asrc: asrc@02034000 {
 363                                         compatible = "fsl,imx53-asrc";
 364                                         reg = <0x02034000 0x4000>;
 365                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 366                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 367                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 368                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 369                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 370                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 371                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 372                                                 <&clks IMX6QDL_CLK_SPBA>;
 373                                         clock-names = "mem", "ipg", "asrck_0",
 374                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 375                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 376                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 377                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 378                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 379                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 380                                         dma-names = "rxa", "rxb", "rxc",
 381                                                 "txa", "txb", "txc";
 382                                         fsl,asrc-rate  = <48000>;
 383                                         fsl,asrc-width = <16>;
 384                                         status = "okay";
 385                                 };
 386
 387                                 spba@0203c000 {
 388                                         reg = <0x0203c000 0x4000>;
 389                                 };
 390                         };
 391
 392                         vpu: vpu@02040000 {
 393                                 compatible = "fsl,imx6-vpu";
 394                                 reg = <0x02040000 0x3c000>;
 395                                 reg-names = "vpu_regs";
 396                                 interrupts = <0 3 IRQ_TYPE_EDGE_RISING>,
 397                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 398                                 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
 399                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 400                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
 401                                          <&clks IMX6QDL_CLK_OCRAM>;
 402                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 403                                 iramsize = <0x21000>;
 404                                 iram = <&ocram>;
 405                                 resets = <&src 1>;
 406                                 power-domains = <&gpc 1>;
 407                         };
 408
 409                         aipstz@0207c000 { /* AIPSTZ1 */
 410                                 reg = <0x0207c000 0x4000>;
 411                         };
 412
 413                         pwm1: pwm@02080000 {
 414                                 #pwm-cells = <2>;
 415                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 416                                 reg = <0x02080000 0x4000>;
 417                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 419                                          <&clks IMX6QDL_CLK_PWM1>;
 420                                 clock-names = "ipg", "per";
 421                         };
 422
 423                         pwm2: pwm@02084000 {
 424                                 #pwm-cells = <2>;
 425                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 426                                 reg = <0x02084000 0x4000>;
 427                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 429                                          <&clks IMX6QDL_CLK_PWM2>;
 430                                 clock-names = "ipg", "per";
 431                         };
 432
 433                         pwm3: pwm@02088000 {
 434                                 #pwm-cells = <2>;
 435                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 436                                 reg = <0x02088000 0x4000>;
 437                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 438                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 439                                          <&clks IMX6QDL_CLK_PWM3>;
 440                                 clock-names = "ipg", "per";
 441                         };
 442
 443                         pwm4: pwm@0208c000 {
 444                                 #pwm-cells = <2>;
 445                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 446                                 reg = <0x0208c000 0x4000>;
 447                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 449                                          <&clks IMX6QDL_CLK_PWM4>;
 450                                 clock-names = "ipg", "per";
 451                         };
 452
 453                         flexcan1: can@02090000 {
 454                                 compatible = "fsl,imx6q-flexcan";
 455                                 reg = <0x02090000 0x4000>;
 456                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 457                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 458                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 459                                 clock-names = "ipg", "per";
 460                                 stop-mode = <&gpr 0x34 28 0x10 17>;
 461                                 status = "disabled";
 462                         };
 463
 464                         flexcan2: can@02094000 {
 465                                 compatible = "fsl,imx6q-flexcan";
 466                                 reg = <0x02094000 0x4000>;
 467                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 468                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 469                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 470                                 clock-names = "ipg", "per";
 471                                 stop-mode = <&gpr 0x34 29 0x10 18>;
 472                                 status = "disabled";
 473                         };
 474
 475                         gpt: gpt@02098000 {
 476                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 477                                 reg = <0x02098000 0x4000>;
 478                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 479                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 480                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 481                                 clock-names = "ipg", "per";
 482                         };
 483
 484                         gpio1: gpio@0209c000 {
 485                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 486                                 reg = <0x0209c000 0x4000>;
 487                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 488                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 489                                 gpio-controller;
 490                                 #gpio-cells = <2>;
 491                                 interrupt-controller;
 492                                 #interrupt-cells = <2>;
 493                         };
 494
 495                         gpio2: gpio@020a0000 {
 496                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 497                                 reg = <0x020a0000 0x4000>;
 498                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 499                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 500                                 gpio-controller;
 501                                 #gpio-cells = <2>;
 502                                 interrupt-controller;
 503                                 #interrupt-cells = <2>;
 504                         };
 505
 506                         gpio3: gpio@020a4000 {
 507                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 508                                 reg = <0x020a4000 0x4000>;
 509                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 511                                 gpio-controller;
 512                                 #gpio-cells = <2>;
 513                                 interrupt-controller;
 514                                 #interrupt-cells = <2>;
 515                         };
 516
 517                         gpio4: gpio@020a8000 {
 518                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 519                                 reg = <0x020a8000 0x4000>;
 520                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 521                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 522                                 gpio-controller;
 523                                 #gpio-cells = <2>;
 524                                 interrupt-controller;
 525                                 #interrupt-cells = <2>;
 526                         };
 527
 528                         gpio5: gpio@020ac000 {
 529                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 530                                 reg = <0x020ac000 0x4000>;
 531                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 532                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 533                                 gpio-controller;
 534                                 #gpio-cells = <2>;
 535                                 interrupt-controller;
 536                                 #interrupt-cells = <2>;
 537                         };
 538
 539                         gpio6: gpio@020b0000 {
 540                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 541                                 reg = <0x020b0000 0x4000>;
 542                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 543                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 544                                 gpio-controller;
 545                                 #gpio-cells = <2>;
 546                                 interrupt-controller;
 547                                 #interrupt-cells = <2>;
 548                         };
 549
 550                         gpio7: gpio@020b4000 {
 551                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 552                                 reg = <0x020b4000 0x4000>;
 553                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 554                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 555                                 gpio-controller;
 556                                 #gpio-cells = <2>;
 557                                 interrupt-controller;
 558                                 #interrupt-cells = <2>;
 559                         };
 560
 561                         kpp: kpp@020b8000 {
 562                                 reg = <0x020b8000 0x4000>;
 563                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 564                         };
 565
 566                         wdog1: wdog@020bc000 {
 567                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 568                                 reg = <0x020bc000 0x4000>;
 569                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 570                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 571                         };
 572
 573                         wdog2: wdog@020c0000 {
 574                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 575                                 reg = <0x020c0000 0x4000>;
 576                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 577                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 578                                 status = "disabled";
 579                         };
 580
 581                         clks: ccm@020c4000 {
 582                                 compatible = "fsl,imx6q-ccm";
 583                                 reg = <0x020c4000 0x4000>;
 584                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 585                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 586                                 #clock-cells = <1>;
 587                         };
 588
 589                         anatop: anatop@020c8000 {
 590                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 591                                 reg = <0x020c8000 0x1000>;
 592                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 593                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 594                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 595
 596                                 regulator-1p1@110 {
 597                                         compatible = "fsl,anatop-regulator";
 598                                         regulator-name = "vdd1p1";
 599                                         regulator-min-microvolt = <800000>;
 600                                         regulator-max-microvolt = <1375000>;
 601                                         regulator-always-on;
 602                                         anatop-reg-offset = <0x110>;
 603                                         anatop-vol-bit-shift = <8>;
 604                                         anatop-vol-bit-width = <5>;
 605                                         anatop-min-bit-val = <4>;
 606                                         anatop-min-voltage = <800000>;
 607                                         anatop-max-voltage = <1375000>;
 608                                 };
 609
 610                                 regulator-3p0@120 {
 611                                         compatible = "fsl,anatop-regulator";
 612                                         regulator-name = "vdd3p0";
 613                                         regulator-min-microvolt = <2800000>;
 614                                         regulator-max-microvolt = <3150000>;
 615                                         regulator-always-on;
 616                                         anatop-reg-offset = <0x120>;
 617                                         anatop-vol-bit-shift = <8>;
 618                                         anatop-vol-bit-width = <5>;
 619                                         anatop-min-bit-val = <0>;
 620                                         anatop-min-voltage = <2625000>;
 621                                         anatop-max-voltage = <3400000>;
 622                                 };
 623
 624                                 regulator-2p5@130 {
 625                                         compatible = "fsl,anatop-regulator";
 626                                         regulator-name = "vdd2p5";
 627                                         regulator-min-microvolt = <2000000>;
 628                                         regulator-max-microvolt = <2750000>;
 629                                         regulator-always-on;
 630                                         anatop-reg-offset = <0x130>;
 631                                         anatop-vol-bit-shift = <8>;
 632                                         anatop-vol-bit-width = <5>;
 633                                         anatop-min-bit-val = <0>;
 634                                         anatop-min-voltage = <2000000>;
 635                                         anatop-max-voltage = <2750000>;
 636                                 };
 637
 638                                 reg_arm: regulator-vddcore@140 {
 639                                         compatible = "fsl,anatop-regulator";
 640                                         regulator-name = "vddarm";
 641                                         regulator-min-microvolt = <725000>;
 642                                         regulator-max-microvolt = <1450000>;
 643                                         regulator-always-on;
 644                                         anatop-reg-offset = <0x140>;
 645                                         anatop-vol-bit-shift = <0>;
 646                                         anatop-vol-bit-width = <5>;
 647                                         anatop-delay-reg-offset = <0x170>;
 648                                         anatop-delay-bit-shift = <24>;
 649                                         anatop-delay-bit-width = <2>;
 650                                         anatop-min-bit-val = <1>;
 651                                         anatop-min-voltage = <725000>;
 652                                         anatop-max-voltage = <1450000>;
 653                                         regulator-allow-bypass;
 654                                 };
 655
 656                                 reg_pu: regulator-vddpu@140 {
 657                                         compatible = "fsl,anatop-regulator";
 658                                         regulator-name = "vddpu";
 659                                         regulator-min-microvolt = <725000>;
 660                                         regulator-max-microvolt = <1450000>;
 661                                         regulator-enable-ramp-delay = <150>;
 662                                         regulator-boot-on;
 663                                         anatop-reg-offset = <0x140>;
 664                                         anatop-vol-bit-shift = <9>;
 665                                         anatop-vol-bit-width = <5>;
 666                                         anatop-delay-reg-offset = <0x170>;
 667                                         anatop-delay-bit-shift = <26>;
 668                                         anatop-delay-bit-width = <2>;
 669                                         anatop-min-bit-val = <1>;
 670                                         anatop-min-voltage = <725000>;
 671                                         anatop-max-voltage = <1450000>;
 672                                         regulator-allow-bypass;
 673                                 };
 674
 675                                 reg_soc: regulator-vddsoc@140 {
 676                                         compatible = "fsl,anatop-regulator";
 677                                         regulator-name = "vddsoc";
 678                                         regulator-min-microvolt = <725000>;
 679                                         regulator-max-microvolt = <1450000>;
 680                                         regulator-always-on;
 681                                         anatop-reg-offset = <0x140>;
 682                                         anatop-vol-bit-shift = <18>;
 683                                         anatop-vol-bit-width = <5>;
 684                                         anatop-delay-reg-offset = <0x170>;
 685                                         anatop-delay-bit-shift = <28>;
 686                                         anatop-delay-bit-width = <2>;
 687                                         anatop-min-bit-val = <1>;
 688                                         anatop-min-voltage = <725000>;
 689                                         anatop-max-voltage = <1450000>;
 690                                         regulator-allow-bypass;
 691                                 };
 692                         };
 693
 694                         tempmon: tempmon {
 695                                 compatible = "fsl,imx6q-tempmon";
 696                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 697                                 fsl,tempmon = <&anatop>;
 698                                 fsl,tempmon-data = <&ocotp>;
 699                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 700                         };
 701
 702                         usbphy1: usbphy@020c9000 {
 703                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 704                                 reg = <0x020c9000 0x1000>;
 705                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 706                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 707                                 fsl,anatop = <&anatop>;
 708                         };
 709
 710                         usbphy2: usbphy@020ca000 {
 711                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 712                                 reg = <0x020ca000 0x1000>;
 713                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 715                                 fsl,anatop = <&anatop>;
 716                         };
 717
 718                         usbphy_nop1: usbphy_nop1 {
 719                                 compatible = "usb-nop-xceiv";
 720                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 721                                 clock-names = "main_clk";
 722                         };
 723
 724                         usbphy_nop2: usbphy_nop2 {
 725                                 compatible = "usb-nop-xceiv";
 726                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 727                                 clock-names = "main_clk";
 728                         };
 729
 730                         caam_snvs: caam-snvs@020cc000 {
 731                                 compatible = "fsl,imx6q-caam-snvs";
 732                                 reg = <0x020cc000 0x4000>;
 733                         };
 734
 735                         snvs@020cc000 {
 736                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 737                                 #address-cells = <1>;
 738                                 #size-cells = <1>;
 739                                 ranges = <0 0x020cc000 0x4000>;
 740
 741                                 snvs-rtc-lp@34 {
 742                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 743                                         reg = <0x34 0x58>;
 744                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 745                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 746                                 };
 747                         };
 748
 749                         epit1: epit@020d0000 { /* EPIT1 */
 750                                 reg = <0x020d0000 0x4000>;
 751                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 752                         };
 753
 754                         epit2: epit@020d4000 { /* EPIT2 */
 755                                 reg = <0x020d4000 0x4000>;
 756                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 757                         };
 758
 759                         src: src@020d8000 {
 760                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 761                                 reg = <0x020d8000 0x4000>;
 762                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 763                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 764                                 #reset-cells = <1>;
 765                         };
 766
 767                         gpc: gpc@020dc000 {
 768                                 compatible = "fsl,imx6q-gpc";
 769                                 reg = <0x020dc000 0x4000>;
 770                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 771                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 772                                 pu-supply = <&reg_pu>;
 773                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 774                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 775                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 776                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 777                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 778                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 779                                 #power-domain-cells = <1>;
 780                         };
 781
 782                         gpr: iomuxc-gpr@020e0000 {
 783                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 784                                 reg = <0x020e0000 0x38>;
 785                         };
 786
 787                         iomuxc: iomuxc@020e0000 {
 788                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 789                                 reg = <0x020e0000 0x4000>;
 790                         };
 791
 792                         ldb: ldb@020e0008 {
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                                 gpr = <&gpr>;
 796                                 status = "disabled";
 797
 798                                 lvds-channel@0 {
 799                                         reg = <0>;
 800                                         status = "disabled";
 801                                 };
 802
 803                                 lvds-channel@1 {
 804                                         reg = <1>;
 805                                         status = "disabled";
 806                                 };
 807                         };
 808
 809                         dcic1: dcic@020e4000 {
 810                                 compatible = "fsl,imx6q-dcic";
 811                                 reg = <0x020e4000 0x4000>;
 812                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 813                                 clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
 814                                 clock-names = "dcic", "disp-axi";
 815                                 gpr = <&gpr>;
 816                                 status = "disabled";
 817                         };
 818
 819                         dcic2: dcic@020e8000 {
 820                                 compatible = "fsl,imx6q-dcic";
 821                                 reg = <0x020e8000 0x4000>;
 822                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
 824                                 clock-names = "dcic", "disp-axi";
 825                                 gpr = <&gpr>;
 826                                 status = "disabled";
 827                         };
 828
 829                         sdma: sdma@020ec000 {
 830                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 831                                 reg = <0x020ec000 0x4000>;
 832                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 834                                          <&clks IMX6QDL_CLK_SDMA>;
 835                                 clock-names = "ipg", "ahb";
 836                                 #dma-cells = <3>;
 837                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 838                         };
 839                 };
 840
 841                 aips-bus@02100000 { /* AIPS2 */
 842                         compatible = "fsl,aips-bus", "simple-bus";
 843                         #address-cells = <1>;
 844                         #size-cells = <1>;
 845                         reg = <0x02100000 0x100000>;
 846                         ranges;
 847
 848                         crypto: caam@2100000 {
 849                                 compatible = "fsl,sec-v4.0";
 850                                 #address-cells = <1>;
 851                                 #size-cells = <1>;
 852                                 reg = <0x2100000 0x40000>;
 853                                 ranges = <0 0x2100000 0x40000>;
 854                                 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
 855                                 clocks = <&clks IMX6QDL_CAAM_MEM>, <&clks IMX6QDL_CAAM_ACLK>, <&clks IMX6QDL_CAAM_IPG> ,<&clks IMX6QDL_CLK_EIM_SLOW>;
 856                                 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
 857
 858                                 sec_jr0: jr0@1000 {
 859                                         compatible = "fsl,sec-v4.0-job-ring";
 860                                         reg = <0x1000 0x1000>;
 861                                         interrupt-parent = <&intc>;
 862                                         interrupts = <0 105 0x4>;
 863                                 };
 864
 865                                 sec_jr1: jr1@2000 {
 866                                         compatible = "fsl,sec-v4.0-job-ring";
 867                                         reg = <0x2000 0x1000>;
 868                                         interrupt-parent = <&intc>;
 869                                         interrupts = <0 106 0x4>;
 870                                 };
 871                         };
 872
 873                         aipstz@0217c000 { /* AIPSTZ2 */
 874                                 reg = <0x0217c000 0x4000>;
 875                         };
 876
 877                         usbotg: usb@02184000 {
 878                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 879                                 reg = <0x02184000 0x200>;
 880                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 881                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 882                                 fsl,usbphy = <&usbphy1>;
 883                                 fsl,usbmisc = <&usbmisc 0>;
 884                                 fsl,anatop = <&anatop>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usbh1: usb@02184200 {
 889                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 890                                 reg = <0x02184200 0x200>;
 891                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 893                                 fsl,usbphy = <&usbphy2>;
 894                                 fsl,usbmisc = <&usbmisc 1>;
 895                                 status = "disabled";
 896                         };
 897
 898                         usbh2: usb@02184400 {
 899                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 900                                 reg = <0x02184400 0x200>;
 901                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 903                                 fsl,usbmisc = <&usbmisc 2>;
 904                                 phy_type = "hsic";
 905                                 fsl,usbphy = <&usbphy_nop1>;
 906                                 fsl,anatop = <&anatop>;
 907                                 status = "disabled";
 908                         };
 909
 910                         usbh3: usb@02184600 {
 911                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 912                                 reg = <0x02184600 0x200>;
 913                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 915                                 fsl,usbmisc = <&usbmisc 3>;
 916                                 phy_type = "hsic";
 917                                 fsl,usbphy = <&usbphy_nop2>;
 918                                 fsl,anatop = <&anatop>;
 919                                 status = "disabled";
 920                         };
 921
 922                         usbmisc: usbmisc@02184800 {
 923                                 #index-cells = <1>;
 924                                 compatible = "fsl,imx6q-usbmisc";
 925                                 reg = <0x02184800 0x200>;
 926                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 927                         };
 928
 929                         fec: ethernet@02188000 {
 930                                 compatible = "fsl,imx6q-fec";
 931                                 reg = <0x02188000 0x4000>;
 932                                 interrupts-extended =
 933                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 934                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 936                                          <&clks IMX6QDL_CLK_ENET>,
 937                                          <&clks IMX6QDL_CLK_ENET_REF>;
 938                                 clock-names = "ipg", "ahb", "ptp";
 939                                 status = "disabled";
 940                         };
 941
 942                         mlb: mlb@0218c000 {
 943                                 compatible = "fsl,imx6q-mlb150";
 944                                 reg = <0x0218c000 0x4000>;
 945                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 946                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 947                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 948                                 clocks = <&clks IMX6QDL_CLK_MLB>,
 949                                          <&clks IMX6QDL_CLK_PLL8_MLB>;
 950                                 clock-names = "mlb", "pll8_mlb";
 951                                 iram = <&ocram>;
 952                                 status = "disabled";
 953                         };
 954
 955                         usdhc1: usdhc@02190000 {
 956                                 compatible = "fsl,imx6q-usdhc";
 957                                 reg = <0x02190000 0x4000>;
 958                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 959                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 960                                          <&clks IMX6QDL_CLK_USDHC1>,
 961                                          <&clks IMX6QDL_CLK_USDHC1>;
 962                                 clock-names = "ipg", "ahb", "per";
 963                                 bus-width = <4>;
 964                                 status = "disabled";
 965                         };
 966
 967                         usdhc2: usdhc@02194000 {
 968                                 compatible = "fsl,imx6q-usdhc";
 969                                 reg = <0x02194000 0x4000>;
 970                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 971                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 972                                          <&clks IMX6QDL_CLK_USDHC2>,
 973                                          <&clks IMX6QDL_CLK_USDHC2>;
 974                                 clock-names = "ipg", "ahb", "per";
 975                                 bus-width = <4>;
 976                                 status = "disabled";
 977                         };
 978
 979                         usdhc3: usdhc@02198000 {
 980                                 compatible = "fsl,imx6q-usdhc";
 981                                 reg = <0x02198000 0x4000>;
 982                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 983                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 984                                          <&clks IMX6QDL_CLK_USDHC3>,
 985                                          <&clks IMX6QDL_CLK_USDHC3>;
 986                                 clock-names = "ipg", "ahb", "per";
 987                                 bus-width = <4>;
 988                                 status = "disabled";
 989                         };
 990
 991                         usdhc4: usdhc@0219c000 {
 992                                 compatible = "fsl,imx6q-usdhc";
 993                                 reg = <0x0219c000 0x4000>;
 994                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 995                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 996                                          <&clks IMX6QDL_CLK_USDHC4>,
 997                                          <&clks IMX6QDL_CLK_USDHC4>;
 998                                 clock-names = "ipg", "ahb", "per";
 999                                 bus-width = <4>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c1: i2c@021a0000 {
1004                                 #address-cells = <1>;
1005                                 #size-cells = <0>;
1006                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1007                                 reg = <0x021a0000 0x4000>;
1008                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1010                                 status = "disabled";
1011                         };
1012
1013                         i2c2: i2c@021a4000 {
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1017                                 reg = <0x021a4000 0x4000>;
1018                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1019                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1020                                 status = "disabled";
1021                         };
1022
1023                         i2c3: i2c@021a8000 {
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1027                                 reg = <0x021a8000 0x4000>;
1028                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1029                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1030                                 status = "disabled";
1031                         };
1032
1033                         romcp@021ac000 {
1034                                 reg = <0x021ac000 0x4000>;
1035                         };
1036
1037                         mmdc0-1@021b0000 { /* MMDC0-1 */
1038                                 compatible = "fsl,imx6q-mmdc-combine";
1039                                 reg = <0x021b0000 0x8000>;
1040                         };
1041
1042                         mmdc0: mmdc@021b0000 { /* MMDC0 */
1043                                 compatible = "fsl,imx6q-mmdc";
1044                                 reg = <0x021b0000 0x4000>;
1045                         };
1046
1047                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1048                                 reg = <0x021b4000 0x4000>;
1049                         };
1050
1051                         weim: weim@021b8000 {
1052                                 compatible = "fsl,imx6q-weim";
1053                                 reg = <0x021b8000 0x4000>;
1054                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1055                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1056                         };
1057
1058                         ocotp: ocotp-ctrl@021bc000 {
1059                                 compatible = "syscon";
1060                                 reg = <0x021bc000 0x4000>;
1061                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1062                         };
1063
1064                         ocotp-fuse@021bc000 {
1065                                 compatible = "fsl,imx6q-ocotp";
1066                                 reg = <0x021bc000 0x4000>;
1067                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1068                         };
1069
1070                         tzasc@021d0000 { /* TZASC1 */
1071                                 reg = <0x021d0000 0x4000>;
1072                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1073                         };
1074
1075                         tzasc@021d4000 { /* TZASC2 */
1076                                 reg = <0x021d4000 0x4000>;
1077                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1078                         };
1079
1080                         audmux: audmux@021d8000 {
1081                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1082                                 reg = <0x021d8000 0x4000>;
1083                                 status = "disabled";
1084                         };
1085
1086                         mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */
1087                                 compatible = "fsl,imx6q-mipi-csi2";
1088                                 reg = <0x021dc000 0x4000>;
1089                                 interrupts = <0 100 0x04>, <0 101 0x04>;
1090                                 clocks = <&clks 138>, <&clks 53>, <&clks 204>;
1091                                 /* Note: clks 138 is hsi_tx, however, the dphy_c
1092                                  * hsi_tx and pll_refclk use the same clk gate.
1093                                  * In current clk driver, open/close clk gate do
1094                                  * use hsi_tx for a temporary debug purpose.
1095                                  */
1096                                 clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
1097                                 status = "disabled";
1098                         };
1099
1100                         mipi@021e0000 { /* MIPI-DSI */
1101                                 reg = <0x021e0000 0x4000>;
1102                         };
1103
1104                         vdoa@021e4000 {
1105                                 compatible = "fsl,imx6q-vdoa";
1106                                 reg = <0x021e4000 0x4000>;
1107                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1108                                 clocks = <&clks IMX6QDL_CLK_VDOA>;
1109                                 iram = <&ocram>;
1110                         };
1111
1112                         uart2: serial@021e8000 {
1113                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1114                                 reg = <0x021e8000 0x4000>;
1115                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1116                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1117                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1118                                 clock-names = "ipg", "per";
1119                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1120                                 dma-names = "rx", "tx";
1121                                 status = "disabled";
1122                         };
1123
1124                         uart3: serial@021ec000 {
1125                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1126                                 reg = <0x021ec000 0x4000>;
1127                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1128                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1129                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1130                                 clock-names = "ipg", "per";
1131                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1132                                 dma-names = "rx", "tx";
1133                                 status = "disabled";
1134                         };
1135
1136                         uart4: serial@021f0000 {
1137                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1138                                 reg = <0x021f0000 0x4000>;
1139                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1140                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1141                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1142                                 clock-names = "ipg", "per";
1143                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1144                                 dma-names = "rx", "tx";
1145                                 status = "disabled";
1146                         };
1147
1148                         uart5: serial@021f4000 {
1149                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1150                                 reg = <0x021f4000 0x4000>;
1151                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1152                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1153                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1154                                 clock-names = "ipg", "per";
1155                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1156                                 dma-names = "rx", "tx";
1157                                 status = "disabled";
1158                         };
1159                 };
1160
1161                 ipu1: ipu@02400000 {
1162                         compatible = "fsl,imx6q-ipu";
1163                         reg = <0x02400000 0x400000>;
1164                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1166                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1167                                  <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
1168                                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
1169                                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
1170                         clock-names = "bus",
1171                                       "di0", "di1",
1172                                       "di0_sel", "di1_sel",
1173                                       "ldb_di0", "ldb_di1";
1174                         resets = <&src 2>;
1175                         bypass_reset = <0>;
1176                 };
1177         };
1178 };