arch/arm/boot/dts/imx6sl-evk.dts

   1 /*
   2  * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sl.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloLite EVK Board";
  16         compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
  17
  18         battery: max8903@0 {
  19                 compatible = "fsl,max8903-charger";
  20                 pinctrl-names = "default";
  21                 dok_input = <&gpio4 13 1>;
  22                 uok_input = <&gpio4 13 1>;
  23                 chg_input = <&gpio4 15 1>;
  24                 flt_input = <&gpio4 14 1>;
  25                 fsl,dcm_always_high;
  26                 fsl,dc_valid;
  27                 fsl,adc_disable;
  28                 status = "okay";
  29         };
  30
  31         memory {
  32                 reg = <0x80000000 0x40000000>;
  33         };
  34
  35         regulators {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 reg_lcd_3v3: lcd-3v3 {
  41                         compatible = "regulator-fixed";
  42                         regulator-name = "lcd-3v3";
  43                         gpio = <&gpio4 3 0>;
  44                         enable-active-high;
  45                 };
  46
  47                 reg_usb_otg1_vbus: regulator@0 {
  48                         compatible = "regulator-fixed";
  49                         reg = <0>;
  50                         regulator-name = "usb_otg1_vbus";
  51                         regulator-min-microvolt = <5000000>;
  52                         regulator-max-microvolt = <5000000>;
  53                         gpio = <&gpio4 0 0>;
  54                         enable-active-high;
  55                 };
  56
  57                 reg_usb_otg2_vbus: regulator@1 {
  58                         compatible = "regulator-fixed";
  59                         reg = <1>;
  60                         regulator-name = "usb_otg2_vbus";
  61                         regulator-min-microvolt = <5000000>;
  62                         regulator-max-microvolt = <5000000>;
  63                         gpio = <&gpio4 2 0>;
  64                         enable-active-high;
  65                 };
  66
  67                 reg_aud3v: regulator@2 {
  68                         compatible = "regulator-fixed";
  69                         reg = <2>;
  70                         regulator-name = "wm8962-supply-3v15";
  71                         regulator-min-microvolt = <3150000>;
  72                         regulator-max-microvolt = <3150000>;
  73                         regulator-boot-on;
  74                 };
  75
  76                 reg_aud4v: regulator@3 {
  77                         compatible = "regulator-fixed";
  78                         reg = <3>;
  79                         regulator-name = "wm8962-supply-4v2";
  80                         regulator-min-microvolt = <4325000>;
  81                         regulator-max-microvolt = <4325000>;
  82                         regulator-boot-on;
  83                 };
  84         };
  85
  86         backlight {
  87                 compatible = "pwm-backlight";
  88                 pwms = <&pwm1 0 5000000>;
  89                 brightness-levels = <0 4 8 16 32 64 128 255>;
  90                 default-brightness-level = <6>;
  91         };
  92
  93         pxp_v4l2_out {
  94                 compatible = "fsl,imx6sl-pxp-v4l2";
  95                 status = "okay";
  96         };
  97
  98         sound {
  99                 compatible = "fsl,imx6q-sabresd-wm8962",
 100                            "fsl,imx-audio-wm8962";
 101                 model = "wm8962-audio";
 102                 cpu-dai = <&ssi2>;
 103                 audio-codec = <&codec>;
 104                 audio-routing =
 105                         "Headphone Jack", "HPOUTL",
 106                         "Headphone Jack", "HPOUTR",
 107                         "Ext Spk", "SPKOUTL",
 108                         "Ext Spk", "SPKOUTR",
 109                         "AMIC", "MICBIAS",
 110                         "IN3R", "AMIC";
 111                 amic-mono;
 112                 mux-int-port = <2>;
 113                 mux-ext-port = <3>;
 114                 hp-det-gpios = <&gpio4 19 1>;
 115         };
 116
 117         sound-spdif {
 118                 compatible = "fsl,imx-audio-spdif",
 119                            "fsl,imx6sl-evk-spdif";
 120                 model = "imx-spdif";
 121                 spdif-controller = <&spdif>;
 122                 spdif-out;
 123         };
 124 };
 125
 126 &audmux {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_audmux>;
 129         status = "okay";
 130 };
 131
 132 &clks {
 133         assigned-clocks = <&clks IMX6SL_PLL4_BYPASS_SRC>,
 134                           <&clks IMX6SL_PLL4_BYPASS>,
 135                           <&clks IMX6SL_CLK_EXTERN_AUDIO_SEL>,
 136                           <&clks IMX6SL_CLK_EXTERN_AUDIO>,
 137                           <&clks IMX6SL_CLK_PLL4_POST_DIV>;
 138         assigned-clock-parents = <&clks IMX6SL_CLK_OSC>,
 139                                 <&clks IMX6SL_PLL4_BYPASS_SRC>,
 140                                 <&clks IMX6SL_CLK_PLL4_AUDIO_DIV>;
 141         assigned-clock-rates = <0>, <0>, <0>, <24000000>,
 142                                 <24000000>;
 143 };
 144
 145 &csi {
 146         port {
 147                 csi_ep: endpoint {
 148                         remote-endpoint = <&ov5640_ep>;
 149                 };
 150         };
 151 };
 152
 153 &cpu0 {
 154         arm-supply = <&sw1a_reg>;
 155         soc-supply = <&sw1c_reg>;
 156 };
 157
 158 &ecspi1 {
 159         fsl,spi-num-chipselects = <1>;
 160         cs-gpios = <&gpio4 11 0>;
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_ecspi1>;
 163         status = "okay";
 164
 165         flash: m25p80@0 {
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 compatible = "st,m25p32";
 169                 spi-max-frequency = <20000000>;
 170                 reg = <0>;
 171         };
 172 };
 173
 174 &epdc {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_epdc_0>;
 177         V3P3-supply = <&V3P3_reg>;
 178         VCOM-supply = <&VCOM_reg>;
 179         DISPLAY-supply = <&DISPLAY_reg>;
 180         status = "okay";
 181 };
 182
 183 &fec {
 184         pinctrl-names = "default", "sleep";
 185         pinctrl-0 = <&pinctrl_fec>;
 186         pinctrl-1 = <&pinctrl_fec_sleep>;
 187         phy-mode = "rmii";
 188         status = "okay";
 189 };
 190
 191 &gpc {
 192         /* use ldo-bypass, u-boot will check it and configure */
 193         fsl,ldo-bypass = <1>;
 194         /* watchdog select of reset source */
 195         fsl,wdog-reset = <1>;
 196 };
 197
 198 &i2c1 {
 199         clock-frequency = <100000>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_i2c1>;
 202         status = "okay";
 203
 204         pmic: pfuze100@08 {
 205                 compatible = "fsl,pfuze100";
 206                 reg = <0x08>;
 207
 208                 regulators {
 209                         sw1a_reg: sw1ab {
 210                                 regulator-min-microvolt = <300000>;
 211                                 regulator-max-microvolt = <1875000>;
 212                                 regulator-boot-on;
 213                                 regulator-always-on;
 214                                 regulator-ramp-delay = <6250>;
 215                         };
 216
 217                         sw1c_reg: sw1c {
 218                                 regulator-min-microvolt = <300000>;
 219                                 regulator-max-microvolt = <1875000>;
 220                                 regulator-boot-on;
 221                                 regulator-always-on;
 222                                 regulator-ramp-delay = <6250>;
 223                         };
 224
 225                         sw2_reg: sw2 {
 226                                 regulator-min-microvolt = <800000>;
 227                                 regulator-max-microvolt = <3300000>;
 228                                 regulator-boot-on;
 229                                 regulator-always-on;
 230                         };
 231
 232                         sw3a_reg: sw3a {
 233                                 regulator-min-microvolt = <400000>;
 234                                 regulator-max-microvolt = <1975000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                         };
 238
 239                         sw3b_reg: sw3b {
 240                                 regulator-min-microvolt = <400000>;
 241                                 regulator-max-microvolt = <1975000>;
 242                                 regulator-boot-on;
 243                                 regulator-always-on;
 244                         };
 245
 246                         sw4_reg: sw4 {
 247                                 regulator-min-microvolt = <800000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                         };
 250
 251                         swbst_reg: swbst {
 252                                 regulator-min-microvolt = <5000000>;
 253                                 regulator-max-microvolt = <5150000>;
 254                         };
 255
 256                         snvs_reg: vsnvs {
 257                                 regulator-min-microvolt = <1000000>;
 258                                 regulator-max-microvolt = <3000000>;
 259                                 regulator-boot-on;
 260                                 regulator-always-on;
 261                         };
 262
 263                         vref_reg: vrefddr {
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                         };
 267
 268                         vgen1_reg: vgen1 {
 269                                 regulator-min-microvolt = <800000>;
 270                                 regulator-max-microvolt = <1550000>;
 271                                 regulator-always-on;
 272                         };
 273
 274                         vgen2_reg: vgen2 {
 275                                 regulator-min-microvolt = <800000>;
 276                                 regulator-max-microvolt = <1550000>;
 277                         };
 278
 279                         vgen3_reg: vgen3 {
 280                                 regulator-min-microvolt = <1800000>;
 281                                 regulator-max-microvolt = <3300000>;
 282                                 regulator-always-on;
 283                         };
 284
 285                         vgen4_reg: vgen4 {
 286                                 regulator-min-microvolt = <1800000>;
 287                                 regulator-max-microvolt = <3300000>;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen5_reg: vgen5 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen6_reg: vgen6 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-always-on;
 301                         };
 302                 };
 303         };
 304
 305         elan@10 {
 306                 compatible = "elan,elan-touch";
 307                 reg = <0x10>;
 308                 interrupt-parent = <&gpio2>;
 309                 interrupts = <10 2>;
 310                 gpio_elan_cs = <&gpio2 9 0>;
 311                 gpio_elan_rst = <&gpio4 4 0>;
 312                 gpio_intr = <&gpio2 10 0>;
 313                 status = "okay";
 314         };
 315
 316         mma8450@1c {
 317                 compatible = "fsl,mma8450";
 318                 reg = <0x1c>;
 319         };
 320
 321         max17135@48 {
 322                 compatible = "maxim,max17135";
 323                 reg = <0x48>;
 324                 vneg_pwrup = <1>;
 325                 gvee_pwrup = <2>;
 326                 vpos_pwrup = <10>;
 327                 gvdd_pwrup = <12>;
 328                 gvdd_pwrdn = <1>;
 329                 vpos_pwrdn = <2>;
 330                 gvee_pwrdn = <8>;
 331                 vneg_pwrdn = <10>;
 332                 gpio_pmic_pwrgood = <&gpio2 13 0>;
 333                 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
 334                 gpio_pmic_wakeup = <&gpio2 14 0>;
 335                 gpio_pmic_v3p3 = <&gpio2 7 0>;
 336                 gpio_pmic_intr = <&gpio2 12 0>;
 337
 338                 regulators {
 339                         DISPLAY_reg: DISPLAY {
 340                                 regulator-name = "DISPLAY";
 341                         };
 342
 343                         GVDD_reg: GVDD {
 344                                 /* 20v */
 345                                 regulator-name = "GVDD";
 346                         };
 347
 348                         GVEE_reg: GVEE {
 349                                 /* -22v */
 350                                 regulator-name = "GVEE";
 351                         };
 352
 353                         HVINN_reg: HVINN {
 354                                 /* -22v */
 355                                 regulator-name = "HVINN";
 356                         };
 357
 358                         HVINP_reg: HVINP {
 359                                 /* 20v */
 360                                 regulator-name = "HVINP";
 361                         };
 362
 363                         VCOM_reg: VCOM {
 364                                 regulator-name = "VCOM";
 365                                 /* 2's-compliment, -4325000 */
 366                                 regulator-min-microvolt = <0xffbe0178>;
 367                                 /* 2's-compliment, -500000 */
 368                                 regulator-max-microvolt = <0xfff85ee0>;
 369                         };
 370
 371                         VNEG_reg: VNEG {
 372                                 /* -15v */
 373                                 regulator-name = "VNEG";
 374                         };
 375
 376                         VPOS_reg: VPOS {
 377                                 /* 15v */
 378                                 regulator-name = "VPOS";
 379                         };
 380
 381                         V3P3_reg: V3P3 {
 382                                 regulator-name = "V3P3";
 383                         };
 384                 };
 385         };
 386
 387 };
 388
 389 &i2c2 {
 390         clock-frequency = <100000>;
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_i2c2>;
 393         status = "okay";
 394
 395         codec: wm8962@1a {
 396                 compatible = "wlf,wm8962";
 397                 reg = <0x1a>;
 398                 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
 399                 DCVDD-supply = <&vgen3_reg>;
 400                 DBVDD-supply = <&reg_aud3v>;
 401                 AVDD-supply = <&vgen3_reg>;
 402                 CPVDD-supply = <&vgen3_reg>;
 403                 MICVDD-supply = <&reg_aud3v>;
 404                 PLLVDD-supply = <&vgen3_reg>;
 405                 SPKVDD1-supply = <&reg_aud4v>;
 406                 SPKVDD2-supply = <&reg_aud4v>;
 407                 amic-mono;
 408         };
 409
 410 };
 411
 412 &i2c3 {
 413         clock-frequency = <100000>;
 414         pinctrl-names = "default";
 415         pinctrl-0 = <&pinctrl_i2c3>;
 416         status = "disabled";
 417
 418         ov5640: ov5640@3c {
 419                 compatible = "ovti,ov5640";
 420                 reg = <0x3c>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&pinctrl_csi_0>;
 423                 clocks = <&clks IMX6SL_CLK_CSI>;
 424                 clock-names = "csi_mclk";
 425                 AVDD-supply = <&vgen6_reg>;  /* 2.8v */
 426                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 427                 pwn-gpios = <&gpio1 25 1>;
 428                 rst-gpios = <&gpio1 26 0>;
 429                 csi_id = <0>;
 430                 mclk = <24000000>;
 431                 mclk_source = <0>;
 432                 port {
 433                         ov5640_ep: endpoint {
 434                                 remote-endpoint = <&csi_ep>;
 435                         };
 436                 };
 437         };
 438 };
 439
 440 &iomuxc {
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&pinctrl_hog>;
 443
 444         imx6sl-evk {
 445                 pinctrl_hog: hoggrp {
 446                         fsl,pins = <
 447                                 MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
 448                                 MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
 449                                 MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
 450                                 MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
 451                                 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
 452                                 MX6SL_PAD_KEY_COL4__GPIO4_IO00  0x80000000
 453                                 MX6SL_PAD_KEY_COL5__GPIO4_IO02  0x80000000
 454                                 MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
 455                                 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
 456                                 MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
 457                                 MX6SL_PAD_FEC_RX_ER__GPIO4_IO19   0x1b0b0
 458                                 MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000
 459                                 MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
 460                                 MX6SL_PAD_KEY_COL6__GPIO4_IO04    0x110b0
 461                         >;
 462                 };
 463
 464                 pinctrl_audmux: audmuxgrp {
 465                         fsl,pins = <
 466                                 MX6SL_PAD_AUD_RXD__AUD3_RXD       0x4130b0
 467                                 MX6SL_PAD_AUD_TXC__AUD3_TXC       0x4130b0
 468                                 MX6SL_PAD_AUD_TXD__AUD3_TXD       0x4110b0
 469                                 MX6SL_PAD_AUD_TXFS__AUD3_TXFS     0x4130b0
 470                                 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
 471                         >;
 472                 };
 473
 474
 475                 pinctrl_ecspi1: ecspi1grp {
 476                         fsl,pins = <
 477                                 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO      0x100b1
 478                                 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI      0x100b1
 479                                 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK      0x100b1
 480                         >;
 481                 };
 482
 483                 pinctrl_epdc_0: epdcgrp-0 {
 484                         fsl,pins = <
 485                                 MX6SL_PAD_EPDC_D0__EPDC_DATA00  0x80000000
 486                                 MX6SL_PAD_EPDC_D1__EPDC_DATA01  0x80000000
 487                                 MX6SL_PAD_EPDC_D2__EPDC_DATA02  0x80000000
 488                                 MX6SL_PAD_EPDC_D3__EPDC_DATA03  0x80000000
 489                                 MX6SL_PAD_EPDC_D4__EPDC_DATA04  0x80000000
 490                                 MX6SL_PAD_EPDC_D5__EPDC_DATA05  0x80000000
 491                                 MX6SL_PAD_EPDC_D6__EPDC_DATA06  0x80000000
 492                                 MX6SL_PAD_EPDC_D7__EPDC_DATA07  0x80000000
 493                                 MX6SL_PAD_EPDC_D8__EPDC_DATA08  0x80000000
 494                                 MX6SL_PAD_EPDC_D9__EPDC_DATA09  0x80000000
 495                                 MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
 496                                 MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
 497                                 MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
 498                                 MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
 499                                 MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
 500                                 MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
 501                                 MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
 502                                 MX6SL_PAD_EPDC_GDSP__EPDC_GDSP   0x80000000
 503                                 MX6SL_PAD_EPDC_GDOE__EPDC_GDOE   0x80000000
 504                                 MX6SL_PAD_EPDC_GDRL__EPDC_GDRL   0x80000000
 505                                 MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
 506                                 MX6SL_PAD_EPDC_SDOE__EPDC_SDOE   0x80000000
 507                                 MX6SL_PAD_EPDC_SDLE__EPDC_SDLE   0x80000000
 508                                 MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
 509                                 MX6SL_PAD_EPDC_BDR0__EPDC_BDR0   0x80000000
 510                                 MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
 511                                 MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
 512                                 MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
 513                         >;
 514                 };
 515
 516                 pinctrl_fec: fecgrp {
 517                         fsl,pins = <
 518                                 MX6SL_PAD_FEC_MDC__FEC_MDC              0x1b0b0
 519                                 MX6SL_PAD_FEC_MDIO__FEC_MDIO            0x1b0b0
 520                                 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV         0x1b0b0
 521                                 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0        0x1b0b0
 522                                 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1        0x1b0b0
 523                                 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN          0x1b0b0
 524                                 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0        0x1b0b0
 525                                 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1        0x1b0b0
 526                                 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT      0x4001b0a8
 527                         >;
 528                 };
 529
 530                 pinctrl_fec_sleep: fecgrp-sleep {
 531                         fsl,pins = <
 532                                 MX6SL_PAD_FEC_MDC__GPIO4_IO23           0x3080
 533                                 MX6SL_PAD_FEC_MDIO__GPIO4_IO20          0x3080
 534                                 MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25        0x3080
 535                                 MX6SL_PAD_FEC_RXD0__GPIO4_IO17          0x3080
 536                                 MX6SL_PAD_FEC_RXD1__GPIO4_IO18          0x3080
 537                                 MX6SL_PAD_FEC_TX_EN__GPIO4_IO22         0x3080
 538                                 MX6SL_PAD_FEC_TXD0__GPIO4_IO24          0x3080
 539                                 MX6SL_PAD_FEC_TXD1__GPIO4_IO16          0x3080
 540                                 MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26       0x3080
 541                         >;
 542                 };
 543
 544                 pinctrl_i2c1: i2c1grp {
 545                         fsl,pins = <
 546                                 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
 547                                 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
 548                         >;
 549                 };
 550
 551                 pinctrl_i2c2: i2c2grp {
 552                         fsl,pins = <
 553                                 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
 554                                 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
 555                         >;
 556                 };
 557
 558                 pinctrl_i2c3: i2c3grp {
 559                         fsl,pins = <
 560                                 MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
 561                                 MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
 562                         >;
 563                 };
 564
 565                 pinctrl_kpp: kppgrp {
 566                         fsl,pins = <
 567                                 MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
 568                                 MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
 569                                 MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
 570                                 MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
 571                                 MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
 572                                 MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
 573                         >;
 574                 };
 575
 576                 pinctrl_lcdif_dat: lcdifdatgrp {
 577                         fsl,pins = <
 578                                 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
 579                                 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
 580                                 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
 581                                 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
 582                                 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
 583                                 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
 584                                 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
 585                                 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
 586                                 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
 587                                 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
 588                                 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
 589                                 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
 590                                 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
 591                                 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
 592                                 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
 593                                 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
 594                                 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
 595                                 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
 596                                 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
 597                                 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
 598                                 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
 599                                 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
 600                                 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
 601                                 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
 602                         >;
 603                 };
 604
 605                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 606                         fsl,pins = <
 607                                 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
 608                                 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
 609                                 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
 610                                 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
 611                         >;
 612                 };
 613
 614                 pinctrl_pwm1: pwm1grp {
 615                         fsl,pins = <
 616                                 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
 617                         >;
 618                 };
 619
 620                 pinctrl_pwm1_sleep: pwm1grp-sleep {
 621                         fsl,pins = <
 622                                 MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
 623                         >;
 624                 };
 625
 626                 pinctrl_spdif: spdifgrp {
 627                         fsl,pins = <
 628                                 MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
 629                         >;
 630                 };
 631
 632                 pinctrl_uart1: uart1grp {
 633                         fsl,pins = <
 634                                 MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x1b0b1
 635                                 MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x1b0b1
 636                         >;
 637                 };
 638
 639                 pinctrl_uart4_1: uart4grp-1 {
 640                         fsl,pins = <
 641                                 MX6SL_PAD_SD1_DAT4__UART4_RX_DATA       0x1b0b1
 642                                 MX6SL_PAD_SD1_DAT5__UART4_TX_DATA       0x1b0b1
 643                                 MX6SL_PAD_SD1_DAT7__UART4_CTS_B         0x1b0b1
 644                                 MX6SL_PAD_SD1_DAT6__UART4_RTS_B         0x1b0b1
 645                         >;
 646                 };
 647
 648                 pinctrl_uart4dte_1: uart4dtegrp-1 {
 649                         fsl,pins = <
 650                                 MX6SL_PAD_SD1_DAT5__UART4_RX_DATA       0x1b0b1
 651                                 MX6SL_PAD_SD1_DAT4__UART4_TX_DATA       0x1b0b1
 652                                 MX6SL_PAD_SD1_DAT6__UART4_CTS_B         0x1b0b1
 653                                 MX6SL_PAD_SD1_DAT7__UART4_RTS_B         0x1b0b1
 654                         >;
 655                 };
 656
 657                 pinctrl_usbotg1: usbotg1grp {
 658                         fsl,pins = <
 659                                 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID      0x17059
 660                         >;
 661                 };
 662
 663                 pinctrl_usdhc1: usdhc1grp {
 664                         fsl,pins = <
 665                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x17059
 666                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x10059
 667                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x17059
 668                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x17059
 669                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x17059
 670                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x17059
 671                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x17059
 672                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x17059
 673                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x17059
 674                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x17059
 675                         >;
 676                 };
 677
 678                 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 679                         fsl,pins = <
 680                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x170b9
 681                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x100b9
 682                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170b9
 683                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170b9
 684                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170b9
 685                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170b9
 686                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170b9
 687                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170b9
 688                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170b9
 689                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170b9
 690                         >;
 691                 };
 692
 693                 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 694                         fsl,pins = <
 695                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x170f9
 696                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x100f9
 697                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170f9
 698                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170f9
 699                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170f9
 700                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170f9
 701                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170f9
 702                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170f9
 703                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170f9
 704                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170f9
 705                         >;
 706                 };
 707
 708                 pinctrl_usdhc2: usdhc2grp {
 709                         fsl,pins = <
 710                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x17059
 711                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x10059
 712                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x17059
 713                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x17059
 714                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x17059
 715                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x17059
 716                         >;
 717                 };
 718
 719                 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 720                         fsl,pins = <
 721                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x170b9
 722                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x100b9
 723                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170b9
 724                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170b9
 725                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170b9
 726                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170b9
 727                         >;
 728                 };
 729
 730                 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 731                         fsl,pins = <
 732                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x170f9
 733                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x100f9
 734                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170f9
 735                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170f9
 736                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170f9
 737                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170f9
 738                         >;
 739                 };
 740
 741                 pinctrl_usdhc3: usdhc3grp {
 742                         fsl,pins = <
 743                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x17059
 744                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x10059
 745                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x17059
 746                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x17059
 747                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x17059
 748                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x17059
 749                         >;
 750                 };
 751
 752                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 753                         fsl,pins = <
 754                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x170b9
 755                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x100b9
 756                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170b9
 757                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170b9
 758                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170b9
 759                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170b9
 760                         >;
 761                 };
 762
 763                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 764                         fsl,pins = <
 765                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x170f9
 766                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x100f9
 767                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170f9
 768                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170f9
 769                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170f9
 770                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170f9
 771                         >;
 772                 };
 773
 774                 pinctrl_csi_0: csigrp-0 {
 775                         fsl,pins = <
 776                                 MX6SL_PAD_EPDC_GDRL__CSI_MCLK   0x110b0
 777                                 MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
 778                                 MX6SL_PAD_EPDC_GDSP__CSI_VSYNC  0x110b0
 779                                 MX6SL_PAD_EPDC_GDOE__CSI_HSYNC  0x110b0
 780                                 MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
 781                                 MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
 782                                 MX6SL_PAD_EPDC_D7__CSI_DATA07   0x110b0
 783                                 MX6SL_PAD_EPDC_D6__CSI_DATA06   0x110b0
 784                                 MX6SL_PAD_EPDC_D5__CSI_DATA05   0x110b0
 785                                 MX6SL_PAD_EPDC_D4__CSI_DATA04   0x110b0
 786                                 MX6SL_PAD_EPDC_D3__CSI_DATA03   0x110b0
 787                                 MX6SL_PAD_EPDC_D2__CSI_DATA02   0x110b0
 788                                 MX6SL_PAD_EPDC_D1__CSI_DATA01   0x110b0
 789                                 MX6SL_PAD_EPDC_D0__CSI_DATA00   0x110b0
 790                                 MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
 791                                 MX6SL_PAD_EPDC_SDOE__GPIO1_IO25  0x80000000
 792                         >;
 793                 };
 794         };
 795 };
 796
 797 &pxp {
 798         status = "okay";
 799 };
 800
 801 &kpp {
 802         pinctrl-names = "default";
 803         pinctrl-0 = <&pinctrl_kpp>;
 804         linux,keymap = <
 805                         MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
 806                         MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
 807                         MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
 808                         MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
 809                         MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
 810                         MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
 811                         MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
 812                         MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
 813         >;
 814         status = "okay";
 815 };
 816
 817 &lcdif {
 818         pinctrl-names = "default";
 819         pinctrl-0 = <&pinctrl_lcdif_dat
 820                      &pinctrl_lcdif_ctrl>;
 821         lcd-supply = <&reg_lcd_3v3>;
 822         display = <&display>;
 823         status = "okay";
 824
 825         display: display {
 826                 bits-per-pixel = <16>;
 827                 bus-width = <24>;
 828
 829                 display-timings {
 830                         native-mode = <&timing0>;
 831                         timing0: timing0 {
 832                                 clock-frequency = <33500000>;
 833                                 hactive = <800>;
 834                                 vactive = <480>;
 835                                 hback-porch = <89>;
 836                                 hfront-porch = <164>;
 837                                 vback-porch = <23>;
 838                                 vfront-porch = <10>;
 839                                 hsync-len = <10>;
 840                                 vsync-len = <10>;
 841                                 hsync-active = <0>;
 842                                 vsync-active = <0>;
 843                                 de-active = <1>;
 844                                 pixelclk-active = <0>;
 845                         };
 846                 };
 847         };
 848 };
 849
 850 &pwm1 {
 851         pinctrl-names = "default", "sleep";
 852         pinctrl-0 = <&pinctrl_pwm1>;
 853         pinctrl-1 = <&pinctrl_pwm1_sleep>;
 854         status = "okay";
 855 };
 856
 857 &spdif {
 858         pinctrl-names = "default";
 859         pinctrl-0 = <&pinctrl_spdif>;
 860         assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>,
 861                           <&clks IMX6SL_CLK_SPDIF0_PODF>;
 862         assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>;
 863         assigned-clock-rates = <0>, <227368421>;
 864         status = "okay";
 865 };
 866
 867 &ssi2 {
 868         fsl,mode = "i2s-slave";
 869         assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>,
 870                           <&clks IMX6SL_CLK_SSI2>;
 871         assigned-clock-rates = <0>, <24000000>;
 872         status = "okay";
 873 };
 874
 875 &uart1 {
 876         pinctrl-names = "default";
 877         pinctrl-0 = <&pinctrl_uart1>;
 878         status = "okay";
 879 };
 880
 881 &usbotg1 {
 882         vbus-supply = <&reg_usb_otg1_vbus>;
 883         pinctrl-names = "default";
 884         pinctrl-0 = <&pinctrl_usbotg1>;
 885         disable-over-current;
 886         status = "okay";
 887 };
 888
 889 &usbotg2 {
 890         vbus-supply = <&reg_usb_otg2_vbus>;
 891         dr_mode = "host";
 892         disable-over-current;
 893         status = "okay";
 894 };
 895
 896 &usdhc1 {
 897         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 898         pinctrl-0 = <&pinctrl_usdhc1>;
 899         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 900         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 901         bus-width = <8>;
 902         cd-gpios = <&gpio4 7 0>;
 903         wp-gpios = <&gpio4 6 0>;
 904         keep-power-in-suspend;
 905         enable-sdio-wakeup;
 906         status = "okay";
 907 };
 908
 909 &usdhc2 {
 910         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 911         pinctrl-0 = <&pinctrl_usdhc2>;
 912         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 913         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 914         cd-gpios = <&gpio5 0 0>;
 915         wp-gpios = <&gpio4 29 0>;
 916         keep-power-in-suspend;
 917         enable-sdio-wakeup;
 918         status = "okay";
 919 };
 920
 921 &usdhc3 {
 922         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 923         pinctrl-0 = <&pinctrl_usdhc3>;
 924         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 925         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 926         cd-gpios = <&gpio3 22 0>;
 927         keep-power-in-suspend;
 928         enable-sdio-wakeup;
 929         status = "okay";
 930 };