arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &lcdif;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  57                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg_can_xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory {
  74                 reg = <0 0>; /* will be filled by U-Boot */
  75         };
  76
  77         clocks {
  78                 mclk: mclk {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <26000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcd_pwr>;
  89                 enable-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  90                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  91                 power-supply = <&reg_3v3>;
  92                 /*
  93                  * a poor man's way to create a 1:1 relationship between
  94                  * the PWM value and the actual duty cycle
  95                  */
  96                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  97                                      10 11 12 13 14 15 16 17 18 19
  98                                      20 21 22 23 24 25 26 27 28 29
  99                                      30 31 32 33 34 35 36 37 38 39
 100                                      40 41 42 43 44 45 46 47 48 49
 101                                      50 51 52 53 54 55 56 57 58 59
 102                                      60 61 62 63 64 65 66 67 68 69
 103                                      70 71 72 73 74 75 76 77 78 79
 104                                      80 81 82 83 84 85 86 87 88 89
 105                                      90 91 92 93 94 95 96 97 98 99
 106                                     100>;
 107                 default-brightness-level = <50>;
 108         };
 109
 110         i2c_gpio: i2c-gpio {
 111                 compatible = "i2c-gpio";
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 116                 gpios = <
 117                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 118                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 119                 >;
 120                 clock-frequency = <400000>;
 121                 status = "okay";
 122
 123                 ds1339: rtc@68 {
 124                         compatible = "dallas,ds1339";
 125                         reg = <0x68>;
 126                         status = "disabled";
 127                 };
 128         };
 129
 130         lcd-panel {
 131                 compatible = "edt,etm0700g0dh6";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_lcd_rst>;
 134                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 135                 power-supply = <&reg_3v3>;
 136                 backlight = <&backlight>;
 137                 bus-format-override = "rgb24";
 138
 139                 port {
 140                         panel_in: endpoint {
 141                                 remote-endpoint = <&display_out>;
 142                         };
 143                 };
 144         };
 145
 146         leds {
 147                 compatible = "gpio-leds";
 148
 149                 user_led: user {
 150                         label = "Heartbeat";
 151                         pinctrl-names = "default";
 152                         pinctrl-0 = <&pinctrl_led>;
 153                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 154                         linux,default-trigger = "heartbeat";
 155                 };
 156         };
 157
 158         reg_3v3_etn: regulator-3v3etn {
 159                 compatible = "regulator-fixed";
 160                 regulator-name = "3V3_ETN";
 161                 regulator-min-microvolt = <3300000>;
 162                 regulator-max-microvolt = <3300000>;
 163                 pinctrl-names = "default";
 164                 pinctrl-0 = <&pinctrl_etnphy_power>;
 165                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 166                 enable-active-high;
 167         };
 168
 169         reg_2v5: regulator-2v5 {
 170                 compatible = "regulator-fixed";
 171                 regulator-name = "2V5";
 172                 regulator-min-microvolt = <2500000>;
 173                 regulator-max-microvolt = <2500000>;
 174                 regulator-always-on;
 175         };
 176
 177         reg_3v3: regulator-3v3 {
 178                 compatible = "regulator-fixed";
 179                 regulator-name = "3V3";
 180                 regulator-min-microvolt = <3300000>;
 181                 regulator-max-microvolt = <3300000>;
 182                 regulator-always-on;
 183         };
 184
 185         reg_can_xcvr: regulator-canxcvr {
 186                 compatible = "regulator-fixed";
 187                 regulator-name = "CAN XCVR";
 188                 regulator-min-microvolt = <3300000>;
 189                 regulator-max-microvolt = <3300000>;
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 192                 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
 193         };
 194
 195         reg_usbh1_vbus: regulator-usbh1vbus {
 196                 compatible = "regulator-fixed";
 197                 regulator-name = "usbh1_vbus";
 198                 regulator-min-microvolt = <5000000>;
 199                 regulator-max-microvolt = <5000000>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 202                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 203                 enable-active-high;
 204         };
 205
 206         reg_usbotg_vbus: regulator-usbotgvbus {
 207                 compatible = "regulator-fixed";
 208                 regulator-name = "usbotg_vbus";
 209                 regulator-min-microvolt = <5000000>;
 210                 regulator-max-microvolt = <5000000>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 213                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 214                 enable-active-high;
 215         };
 216
 217         spi_gpio: spi-gpio {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 compatible = "spi-gpio";
 221                 pinctrl-names = "default";
 222                 pinctrl-0 = <&pinctrl_spi_gpio>;
 223                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 224                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 225                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 226                 num-chipselects = <2>;
 227                 cs-gpios = <
 228                         &gpio1 29 GPIO_ACTIVE_HIGH
 229                         &gpio1 10 GPIO_ACTIVE_HIGH
 230                 >;
 231                 status = "disabled";
 232
 233                 spi@0 {
 234                         compatible = "spidev";
 235                         reg = <0>;
 236                         spi-max-frequency = <660000>;
 237                 };
 238
 239                 spi@1 {
 240                         compatible = "spidev";
 241                         reg = <1>;
 242                         spi-max-frequency = <660000>;
 243                 };
 244         };
 245
 246         sound {
 247                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 248                              "simple-audio-card";
 249                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 250                 simple-audio-card,format = "i2s";
 251                 simple-audio-card,bitclock-master = <&codec_dai>;
 252                 simple-audio-card,frame-master = <&codec_dai>;
 253                 simple-audio-card,widgets =
 254                         "Microphone", "Mic Jack",
 255                         "Line", "Line In",
 256                         "Line", "Line Out",
 257                         "Headphone", "Headphone Jack";
 258                 simple-audio-card,routing =
 259                         "MIC_IN", "Mic Jack",
 260                         "Mic Jack", "Mic Bias",
 261                         "Headphone Jack", "HP_OUT";
 262
 263                 cpu_dai: simple-audio-card,cpu {
 264                         sound-dai = <&sai2>;
 265                 };
 266
 267                 codec_dai: simple-audio-card,codec {
 268                         sound-dai = <&sgtl5000>;
 269                 };
 270         };
 271 };
 272
 273 &can1 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_flexcan1>;
 276         xceiver-supply = <&reg_can_xcvr>;
 277         status = "okay";
 278 };
 279
 280 &can2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_flexcan2>;
 283         xceiver-supply = <&reg_can_xcvr>;
 284         status = "okay";
 285 };
 286
 287 &ecspi2 {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_ecspi2>;
 290         cs-gpios = <
 291                 &gpio1 29 GPIO_ACTIVE_HIGH
 292                 &gpio1 10 GPIO_ACTIVE_HIGH
 293         >;
 294         status = "disabled";
 295
 296         spidev0: spi@0 {
 297                 compatible = "spidev";
 298                 reg = <0>;
 299                 spi-max-frequency = <60000000>;
 300         };
 301
 302         spidev1: spi@1 {
 303                 compatible = "spidev";
 304                 reg = <1>;
 305                 spi-max-frequency = <60000000>;
 306         };
 307 };
 308
 309 &fec1 {
 310         pinctrl-names = "default", "sleep";
 311         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 312         pinctrl-1 = <&pinctrl_enet1_sleep &pinctrl_enet1_mdio_sleep
 313                      &pinctrl_etnphy0_rst_sleep>;
 314         phy-mode = "rmii";
 315         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 316         phy-reset-post-delay = <10>;
 317         phy-supply = <&reg_3v3_etn>;
 318         phy-handle = <&etnphy0>;
 319         status = "okay";
 320
 321         mdio {
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324
 325                 etnphy0: ethernet-phy@0 {
 326                         compatible = "ethernet-phy-ieee802.3-c22";
 327                         reg = <0>;
 328                         pinctrl-names = "default";
 329                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 330                         interrupt-parent = <&gpio5>;
 331                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 332                         status = "okay";
 333                 };
 334
 335                 etnphy1: ethernet-phy@2 {
 336                         compatible = "ethernet-phy-ieee802.3-c22";
 337                         reg = <2>;
 338                         pinctrl-names = "default";
 339                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 340                         interrupt-parent = <&gpio4>;
 341                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 342                         status = "okay";
 343                 };
 344         };
 345 };
 346
 347 &fec2 {
 348         pinctrl-names = "default", "sleep";
 349         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 350         pinctrl-1 = <&pinctrl_enet2_sleep &pinctrl_etnphy1_rst_sleep>;
 351         phy-mode = "rmii";
 352         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 353         phy-supply = <&reg_3v3_etn>;
 354         phy-handle = <&etnphy1>;
 355         status = "disabled";
 356 };
 357
 358 &gpmi {
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&pinctrl_gpmi_nand>;
 361         nand-on-flash-bbt;
 362         fsl,no-blockmark-swap;
 363         status = "okay";
 364 };
 365
 366 &i2c2 {
 367         pinctrl-names = "default", "gpio";
 368         pinctrl-0 = <&pinctrl_i2c2>;
 369         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 370         scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 371         sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 372         clock-frequency = <400000>;
 373         status = "okay";
 374
 375         sgtl5000: codec@0a {
 376                 compatible = "fsl,sgtl5000";
 377                 reg = <0x0a>;
 378                 #sound-dai-cells = <0>;
 379                 VDDA-supply = <&reg_2v5>;
 380                 VDDIO-supply = <&reg_3v3>;
 381                 clocks = <&mclk>;
 382         };
 383
 384         polytouch: polytouch@38 {
 385                 compatible = "edt,edt-ft5x06";
 386                 reg = <0x38>;
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 389                 interrupt-parent = <&gpio5>;
 390                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 391                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 392                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 393                 wakeup-source;
 394         };
 395
 396         touchscreen: touchscreen@48 {
 397                 compatible = "ti,tsc2007";
 398                 reg = <0x48>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pinctrl_tsc2007>;
 401                 interrupt-parent = <&gpio3>;
 402                 interrupts = <26 IRQ_TYPE_NONE>;
 403                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 404                 ti,x-plate-ohms = <660>;
 405                 wakeup-source;
 406         };
 407 };
 408
 409 &kpp {
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_kpp>;
 412         /* sample keymap */
 413         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 414         linux,keymap = <
 415                 MATRIX_KEY(4, 4, KEY_POWER)
 416                 MATRIX_KEY(4, 5, KEY_KP0)
 417                 MATRIX_KEY(4, 6, KEY_KP1)
 418                 MATRIX_KEY(4, 7, KEY_KP2)
 419                 MATRIX_KEY(5, 4, KEY_KP3)
 420                 MATRIX_KEY(5, 5, KEY_KP4)
 421                 MATRIX_KEY(5, 6, KEY_KP5)
 422                 MATRIX_KEY(5, 7, KEY_KP6)
 423                 MATRIX_KEY(6, 4, KEY_KP7)
 424                 MATRIX_KEY(6, 5, KEY_KP8)
 425                 MATRIX_KEY(6, 6, KEY_KP9)
 426         >;
 427         status = "okay";
 428 };
 429
 430 &lcdif {
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_disp0_1>;
 433         status = "okay";
 434
 435         port {
 436                 display_out: endpoint {
 437                         remote-endpoint = <&panel_in>;
 438                 };
 439         };
 440
 441         display-timings {
 442                 VGA {
 443                         clock-frequency = <25200000>;
 444                         hactive = <640>;
 445                         vactive = <480>;
 446                         hback-porch = <48>;
 447                         hsync-len = <96>;
 448                         hfront-porch = <16>;
 449                         vback-porch = <31>;
 450                         vsync-len = <2>;
 451                         vfront-porch = <12>;
 452                         hsync-active = <0>;
 453                         vsync-active = <0>;
 454                         de-active = <1>;
 455                         pixelclk-active = <1>;
 456                 };
 457
 458                 ETV570 {
 459                         u-boot,panel-name = "edt,et057090dhu";
 460                         clock-frequency = <25200000>;
 461                         hactive = <640>;
 462                         vactive = <480>;
 463                         hback-porch = <114>;
 464                         hsync-len = <30>;
 465                         hfront-porch = <16>;
 466                         vback-porch = <32>;
 467                         vsync-len = <3>;
 468                         vfront-porch = <10>;
 469                         hsync-active = <0>;
 470                         vsync-active = <0>;
 471                         de-active = <1>;
 472                         pixelclk-active = <1>;
 473                 };
 474
 475                 ET0350 {
 476                         u-boot,panel-name = "edt,et0350g0dh6";
 477                         clock-frequency = <6413760>;
 478                         hactive = <320>;
 479                         vactive = <240>;
 480                         hback-porch = <34>;
 481                         hsync-len = <34>;
 482                         hfront-porch = <20>;
 483                         vback-porch = <15>;
 484                         vsync-len = <3>;
 485                         vfront-porch = <4>;
 486                         hsync-active = <0>;
 487                         vsync-active = <0>;
 488                         de-active = <1>;
 489                         pixelclk-active = <1>;
 490                 };
 491
 492                 ET0430 {
 493                         u-boot,panel-name = "edt,et0430g0dh6";
 494                         clock-frequency = <9009000>;
 495                         hactive = <480>;
 496                         vactive = <272>;
 497                         hback-porch = <2>;
 498                         hsync-len = <41>;
 499                         hfront-porch = <2>;
 500                         vback-porch = <2>;
 501                         vsync-len = <10>;
 502                         vfront-porch = <2>;
 503                         hsync-active = <0>;
 504                         vsync-active = <0>;
 505                         de-active = <1>;
 506                         pixelclk-active = <0>;
 507                 };
 508
 509                 ET0500 {
 510                         clock-frequency = <33264000>;
 511                         hactive = <800>;
 512                         vactive = <480>;
 513                         hback-porch = <88>;
 514                         hsync-len = <128>;
 515                         hfront-porch = <40>;
 516                         vback-porch = <33>;
 517                         vsync-len = <2>;
 518                         vfront-porch = <10>;
 519                         hsync-active = <0>;
 520                         vsync-active = <0>;
 521                         de-active = <1>;
 522                         pixelclk-active = <1>;
 523                 };
 524
 525                 ET0700 { /* same timing as ET0500 */
 526                         u-boot,panel-name = "edt,etm0700g0dh6";
 527                         clock-frequency = <33264000>;
 528                         hactive = <800>;
 529                         vactive = <480>;
 530                         hback-porch = <88>;
 531                         hsync-len = <128>;
 532                         hfront-porch = <40>;
 533                         vback-porch = <33>;
 534                         vsync-len = <2>;
 535                         vfront-porch = <10>;
 536                         hsync-active = <0>;
 537                         vsync-active = <0>;
 538                         de-active = <1>;
 539                         pixelclk-active = <1>;
 540                 };
 541
 542                 ETQ570 {
 543                         clock-frequency = <6596040>;
 544                         hactive = <320>;
 545                         vactive = <240>;
 546                         hback-porch = <38>;
 547                         hsync-len = <30>;
 548                         hfront-porch = <30>;
 549                         vback-porch = <16>;
 550                         vsync-len = <3>;
 551                         vfront-porch = <4>;
 552                         hsync-active = <0>;
 553                         vsync-active = <0>;
 554                         de-active = <1>;
 555                         pixelclk-active = <1>;
 556                 };
 557         };
 558 };
 559
 560 &pwm5 {
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pinctrl_pwm5>;
 563         #pwm-cells = <3>;
 564         status = "okay";
 565 };
 566
 567 &sai2 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&pinctrl_sai2>;
 570         status = "okay";
 571 };
 572
 573 &uart1 {
 574         pinctrl-names = "default";
 575         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 576         uart-has-rtscts;
 577         status = "okay";
 578 };
 579
 580 &uart2 {
 581         pinctrl-names = "default";
 582         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 583         uart-has-rtscts;
 584         status = "okay";
 585 };
 586
 587 &uart5 {
 588         pinctrl-names = "default";
 589         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 590         uart-has-rtscts;
 591         status = "okay";
 592 };
 593
 594 &usbotg1 {
 595         vbus-supply = <&reg_usbotg_vbus>;
 596         dr_mode = "peripheral";
 597         disable-over-current;
 598         status = "okay";
 599 };
 600
 601 &usbotg2 {
 602         vbus-supply = <&reg_usbh1_vbus>;
 603         dr_mode = "host";
 604         disable-over-current;
 605         status = "okay";
 606 };
 607
 608 &usdhc1 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 611         bus-width = <4>;
 612         no-1-8-v;
 613         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 614         fsl,wp-controller;
 615         status = "okay";
 616 };
 617
 618 &iomuxc {
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&pinctrl_hog>;
 621
 622         pinctrl_hog: hoggrp {
 623         };
 624
 625         pinctrl_led: ledgrp {
 626                 fsl,pins = <
 627                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 628                 >;
 629         };
 630
 631         pinctrl_disp0_1: disp0grp-1 {
 632                 fsl,pins = <
 633                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 634                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 635                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 636                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 637                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 638                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 639                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 640                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 641                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 642                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 643                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 644                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 645                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 646                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 647                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 648                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 649                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 650                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 651                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 652                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 653                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 654                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 655                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 656                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 657                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 658                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 659                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 660                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 661                 >;
 662         };
 663
 664         pinctrl_disp0_2: disp0grp-2 {
 665                 fsl,pins = <
 666                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 667                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 668                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 669                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 670                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 671                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 672                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 673                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 674                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 675                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 676                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 677                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 678                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 679                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 680                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 681                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 682                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 683                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 684                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 685                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 686                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 687                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 688                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 689                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 690                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 691                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 692                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 693                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 694                 >;
 695         };
 696
 697         pinctrl_ecspi2: ecspi2grp {
 698                 fsl,pins = <
 699                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 700                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 701                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 702                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 703                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 704                 >;
 705         };
 706
 707         pinctrl_edt_ft5x06: edt-ft5x06grp {
 708                 fsl,pins = <
 709                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 710                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 711                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 712                 >;
 713         };
 714
 715         pinctrl_enet1: enet1grp {
 716                 fsl,pins = <
 717                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 718                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 719                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 720                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 721                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 722                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 723                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 724                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000018
 725                 >;
 726         };
 727
 728         pinctrl_enet1_mdio: enet1-mdiogrp {
 729                 fsl,pins = <
 730                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 731                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 732                 >;
 733         };
 734
 735         pinctrl_enet1_mdio_sleep: enet1-mdio-sleepgrp {
 736                 fsl,pins = <
 737                         MX6UL_PAD_GPIO1_IO07__GPIO1_IO07        0x038b0
 738                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x038b0
 739                 >;
 740         };
 741
 742         pinctrl_enet1_sleep: enet1-sleepgrp {
 743                 fsl,pins = <
 744                         MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x038b0
 745                         MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x038b0
 746                         MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x038b0
 747                         MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x038b0
 748                         MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05       0x038b0
 749                         MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x038b0
 750                         MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0x038b0
 751                         MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06      0x038b0
 752                 >;
 753         };
 754
 755         pinctrl_enet2: enet2grp {
 756                 fsl,pins = <
 757                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 758                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 759                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 760                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 761                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 762                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 763                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 764                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000018
 765                 >;
 766         };
 767
 768         pinctrl_enet2_sleep: enet2grp {
 769                 fsl,pins = <
 770                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 771                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 772                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 773                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 774                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 775                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 776                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 777                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000018
 778                 >;
 779         };
 780
 781         pinctrl_etnphy_power: etnphy-pwrgrp {
 782                 fsl,pins = <
 783                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 784                 >;
 785         };
 786
 787         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 788                 fsl,pins = <
 789                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 790                 >;
 791         };
 792
 793         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 794                 fsl,pins = <
 795                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 796                 >;
 797         };
 798
 799         pinctrl_etnphy0_rst_sleep: etnphy-rst-sleepgrp-0 {
 800                 fsl,pins = <
 801                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x038b0
 802                 >;
 803         };
 804
 805         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 806                 fsl,pins = <
 807                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 808                 >;
 809         };
 810
 811         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 812                 fsl,pins = <
 813                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 814                 >;
 815         };
 816
 817         pinctrl_etnphy1_rst_sleep: etnphy-rst-sleepgrp-1 {
 818                 fsl,pins = <
 819                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x038b0
 820                 >;
 821         };
 822
 823         pinctrl_flexcan1: flexcan1grp {
 824                 fsl,pins = <
 825                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 826                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 827                 >;
 828         };
 829
 830         pinctrl_flexcan2: flexcan2grp {
 831                 fsl,pins = <
 832                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 833                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 834                 >;
 835         };
 836
 837         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 838                 fsl,pins = <
 839                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 840                 >;
 841         };
 842
 843         pinctrl_gpmi_nand: gpminandgrp {
 844                 fsl,pins = <
 845                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 846                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 847                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 848                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 849                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 850                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 851                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 852                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 853                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 854                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 855                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 856                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 857                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 858                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 859                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 860                 >;
 861         };
 862
 863         pinctrl_i2c_gpio: i2c-gpiogrp {
 864                 fsl,pins = <
 865                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 866                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 867                 >;
 868         };
 869
 870         pinctrl_i2c2: i2c2grp {
 871                 fsl,pins = <
 872                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 873                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 874                 >;
 875         };
 876
 877         pinctrl_i2c2_gpio: i2c2-gpiogrp {
 878                 fsl,pins = <
 879                         MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0x4001b0b9
 880                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0x4001b0b9
 881                 >;
 882         };
 883
 884         pinctrl_kpp: kppgrp {
 885                 fsl,pins = <
 886                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 887                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 888                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 889                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 890                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 891                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 892                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 893                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 894                 >;
 895         };
 896
 897         pinctrl_lcd_pwr: lcd-pwrgrp {
 898                 fsl,pins = <
 899                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 900                 >;
 901         };
 902
 903         pinctrl_lcd_rst: lcd-rstgrp {
 904                 fsl,pins = <
 905                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 906                 >;
 907         };
 908
 909         pinctrl_pwm5: pwm5grp {
 910                 fsl,pins = <
 911                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 912                 >;
 913         };
 914
 915         pinctrl_sai2: sai2grp {
 916                 fsl,pins = <
 917                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 918                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 919                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 920                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 921                 >;
 922         };
 923
 924         pinctrl_spi_gpio: spi-gpiogrp {
 925                 fsl,pins = <
 926                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 927                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 928                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 929                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 930                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 931                 >;
 932         };
 933
 934         pinctrl_tsc2007: tsc2007grp {
 935                 fsl,pins = <
 936                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 937                 >;
 938         };
 939
 940         pinctrl_uart1: uart1grp {
 941                 fsl,pins = <
 942                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 943                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 944                 >;
 945         };
 946
 947         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 948                 fsl,pins = <
 949                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 950                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 951                 >;
 952         };
 953
 954         pinctrl_uart2: uart2grp {
 955                 fsl,pins = <
 956                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 957                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 958                 >;
 959         };
 960
 961         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 962                 fsl,pins = <
 963                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 964                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 965                 >;
 966         };
 967
 968         pinctrl_uart5: uart5grp {
 969                 fsl,pins = <
 970                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 971                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 972                 >;
 973         };
 974
 975         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 976                 fsl,pins = <
 977                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 978                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 979                 >;
 980         };
 981
 982         pinctrl_usbh1_oc: usbh1-ocgrp {
 983                 fsl,pins = <
 984                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 985                 >;
 986         };
 987
 988         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 989                 fsl,pins = <
 990                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 991                 >;
 992         };
 993
 994         pinctrl_usbotg_oc: usbotg-ocgrp {
 995                 fsl,pins = <
 996                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 997                 >;
 998         };
 999
1000         pinctrl_usbotg_vbus: usbotg-vbusgrp {
1001                 fsl,pins = <
1002                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
1003                 >;
1004         };
1005
1006         pinctrl_usdhc1: usdhc1grp {
1007                 fsl,pins = <
1008                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
1009                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
1010                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
1011                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
1012                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
1013                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
1014                 >;
1015         };
1016
1017         pinctrl_usdhc1_cd: usdhc1cdgrp {
1018                 fsl,pins = <
1019                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
1020                 >;
1021         };
1022
1023         pinctrl_usdhc2: usdhc2grp {
1024                 fsl,pins = <
1025                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
1026                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
1027                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
1028                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
1029                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
1030                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
1031                         /* eMMC RESET */
1032                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
1033                 >;
1034         };
1035 };