ARM: dts: imx6ul-tx6ul: disable DS1339 which is not normally equipped on the TXUL...
[karo-tx-linux.git] / arch / arm / boot / dts / imx6ul-tx6ul.dtsi
1 /*
2  * Copyright 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10
11 / {
12         aliases {
13                 can0 = &can2;
14                 can1 = &can1;
15                 display = &display;
16                 i2c0 = &i2c_gpio;
17                 i2c1 = &i2c2;
18                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
19                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
20                 pwm0 = &pwm5;
21                 reg_can_xcvr = &reg_can_xcvr;
22                 serial2 = &uart5;
23 //              spi0 = &ecspi2;
24                 spi0 = &spi_gpio;
25                 stk5led = &user_led;
26                 usbh1 = &usbotg2;
27                 usbotg = &usbotg1;
28         };
29
30         chosen {
31                 stdout-path = &uart1;
32         };
33
34         memory {
35                 reg = <0 0>; /* will be filled by U-Boot */
36         };
37
38         clocks {
39                 #address-cells = <1>;
40                 #size-cells = <0>;
41                 mclk: clock@0 {
42                         compatible = "fixed-clock";
43                         reg = <0>;
44                         #clock-cells = <0>;
45                         clock-frequency = <27000000>;
46                 };
47         };
48
49         backlight: backlight {
50                 compatible = "pwm-backlight";
51                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
52                 power-supply = <&reg_3v3>;
53                 /*
54                  * a poor man's way to create a 1:1 relationship between
55                  * the PWM value and the actual duty cycle
56                  */
57                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
58                                      10 11 12 13 14 15 16 17 18 19
59                                      20 21 22 23 24 25 26 27 28 29
60                                      30 31 32 33 34 35 36 37 38 39
61                                      40 41 42 43 44 45 46 47 48 49
62                                      50 51 52 53 54 55 56 57 58 59
63                                      60 61 62 63 64 65 66 67 68 69
64                                      70 71 72 73 74 75 76 77 78 79
65                                      80 81 82 83 84 85 86 87 88 89
66                                      90 91 92 93 94 95 96 97 98 99
67                                     100>;
68                 default-brightness-level = <50>;
69         };
70
71         gpio-keys {
72                 compatible = "gpio-keys";
73         };
74
75         i2c_gpio: i2c-gpio {
76                 compatible = "i2c-gpio";
77                 #address-cells = <1>;
78                 #size-cells = <0>;
79                 pinctrl-names = "default";
80                 pinctrl-0 = <&pinctrl_i2c_gpio>;
81                 gpios = <
82                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
83                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
84                 >;
85                 clock-frequency = <400000>;
86                 status = "okay";
87
88                 ds1339: rtc@68 {
89                         compatible = "dallas,ds1339";
90                         reg = <0x68>;
91                         status = "disabled";
92                 };
93         };
94
95         leds {
96                 compatible = "gpio-leds";
97
98                 user_led: user {
99                         label = "Heartbeat";
100                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
101                         linux,default-trigger = "heartbeat";
102                 };
103         };
104
105         regulators {
106                 compatible = "simple-bus";
107                 #address-cells = <1>;
108                 #size-cells = <0>;
109
110                 reg_3v3_etn: regulator@0 {
111                         compatible = "regulator-fixed";
112                         reg = <0>;
113                         regulator-name = "3V3_ETN";
114                         regulator-min-microvolt = <3300000>;
115                         regulator-max-microvolt = <3300000>;
116                         pinctrl-names = "default";
117                         pinctrl-0 = <&pinctrl_etnphy_power>;
118                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
119                         enable-active-high;
120                 };
121
122                 reg_2v5: regulator@1 {
123                         compatible = "regulator-fixed";
124                         reg = <1>;
125                         regulator-name = "2V5";
126                         regulator-min-microvolt = <2500000>;
127                         regulator-max-microvolt = <2500000>;
128                         regulator-always-on;
129                 };
130
131                 reg_3v3: regulator@2 {
132                         compatible = "regulator-fixed";
133                         reg = <2>;
134                         regulator-name = "3V3";
135                         regulator-min-microvolt = <3300000>;
136                         regulator-max-microvolt = <3300000>;
137                         regulator-always-on;
138                 };
139
140                 reg_can_xcvr: regulator@3 {
141                         compatible = "regulator-fixed";
142                         reg = <3>;
143                         regulator-name = "CAN XCVR";
144                         regulator-min-microvolt = <3300000>;
145                         regulator-max-microvolt = <3300000>;
146                         pinctrl-names = "default";
147                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
148                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
149                         enable-active-low;
150                 };
151
152                 reg_lcd_pwr: regulator@5 {
153                         compatible = "regulator-fixed";
154                         reg = <5>;
155                         regulator-name = "LCD POWER";
156                         regulator-min-microvolt = <3300000>;
157                         regulator-max-microvolt = <3300000>;
158                         pinctrl-names = "default";
159                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
160                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161                         enable-active-high;
162                         regulator-boot-on;
163                         regulator-always-on;
164                 };
165
166                 reg_usbh1_vbus: regulator@6 {
167                         compatible = "regulator-fixed";
168                         reg = <6>;
169                         regulator-name = "usbh1_vbus";
170                         regulator-min-microvolt = <5000000>;
171                         regulator-max-microvolt = <5000000>;
172                         pinctrl-names = "default";
173                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
174                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
175                         enable-active-high;
176                 };
177
178                 reg_usbotg_vbus: regulator@7 {
179                         compatible = "regulator-fixed";
180                         reg = <7>;
181                         regulator-name = "usbotg_vbus";
182                         regulator-min-microvolt = <5000000>;
183                         regulator-max-microvolt = <5000000>;
184                         pinctrl-names = "default";
185                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
186                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
187                         enable-active-high;
188                 };
189         };
190
191         spi_gpio: spi-gpio {
192                 #address-cells = <1>;
193                 #size-cells = <0>;
194                 compatible = "spi-gpio";
195                 pinctrl-names = "default";
196                 pinctrl-0 = <&pinctrl_spi_gpio>;
197                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
198                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
199                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
200                 num-chipselects = <2>;
201                 cs-gpios = <
202                         &gpio1 29 GPIO_ACTIVE_HIGH
203                         &gpio1 10 GPIO_ACTIVE_HIGH
204                 >;
205                 status = "okay";
206
207                 spidev0: spi@0 {
208                         compatible = "spidev";
209                         reg = <0>;
210                         spi-max-frequency = <54000000>;
211                 };
212
213                 spidev1: spi@1 {
214                         compatible = "spidev";
215                         reg = <1>;
216                         spi-max-frequency = <54000000>;
217                 };
218         };
219 };
220
221 &can1 {
222         pinctrl-names = "default";
223         pinctrl-0 = <&pinctrl_flexcan1>;
224         xceiver-supply = <&reg_can_xcvr>;
225         status = "okay";
226 };
227
228 &can2 {
229         pinctrl-names = "default";
230         pinctrl-0 = <&pinctrl_flexcan2>;
231         xceiver-supply = <&reg_can_xcvr>;
232         status = "okay";
233 };
234
235 #if 0
236 &ecspi2 {
237         pinctrl-names = "default";
238         pinctrl-0 = <&pinctrl_ecspi2>;
239         fsl,spi-num-chipselects = <2>;
240         cs-gpios = <
241                 &gpio1 29 GPIO_ACTIVE_HIGH
242                 &gpio1 10 GPIO_ACTIVE_HIGH
243         >;
244         status = "okay";
245
246         spidev0: spi@0 {
247                 compatible = "spidev";
248                 reg = <0>;
249                 spi-max-frequency = <54000000>;
250         };
251
252         spidev1: spi@1 {
253                 compatible = "spidev";
254                 reg = <1>;
255                 spi-max-frequency = <54000000>;
256         };
257 };
258 #endif
259
260 &fec1 {
261         pinctrl-names = "default";
262         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
263         phy-mode = "rmii";
264         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
265         phy-supply = <&reg_3v3_etn>;
266         phy-handle = <&etnphy0>;
267         status = "okay";
268
269         mdio {
270                 #address-cells = <1>;
271                 #size-cells = <0>;
272
273                 etnphy0: ethernet-phy@0 {
274                         compatible = "ethernet-phy-ieee802.3-c22";
275                         reg = <0>;
276                         interrupt-parent = <&gpio5>;
277                         interrupts = <5>;
278                         status = "okay";
279                 };
280
281                 etnphy1: ethernet-phy@1 {
282                         compatible = "ethernet-phy-ieee802.3-c22";
283                         reg = <1>;
284                         status = "okay";
285                 };
286         };
287 };
288
289 &fec2 {
290         pinctrl-names = "default";
291         pinctrl-0 = <&pinctrl_enet2>;
292         phy-mode = "rmii";
293         phy-supply = <&reg_3v3_etn>;
294         phy-handle = <&etnphy1>;
295         status = "okay";
296 };
297
298 &gpmi {
299         pinctrl-names = "default";
300         pinctrl-0 = <&pinctrl_gpmi_nand>;
301         nand-on-flash-bbt;
302         fsl,no-blockmark-swap;
303         status = "okay";
304 };
305
306 &i2c2 {
307         pinctrl-names = "default";
308         pinctrl-0 = <&pinctrl_i2c2>;
309         clock-frequency = <400000>;
310         status = "okay";
311
312         sgtl5000: sgtl5000@0a {
313                 compatible = "fsl,sgtl5000";
314                 reg = <0x0a>;
315                 VDDA-supply = <&reg_2v5>;
316                 VDDIO-supply = <&reg_3v3>;
317                 clocks = <&mclk>;
318         };
319
320         polytouch: edt-ft5x06@38 {
321                 compatible = "edt,edt-ft5x06";
322                 reg = <0x38>;
323                 pinctrl-names = "default";
324                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
325                 interrupt-parent = <&gpio5>;
326                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
327                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
328                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
329                 linux,wakeup;
330         };
331
332         touchscreen: tsc2007@48 {
333                 compatible = "ti,tsc2007";
334                 reg = <0x48>;
335                 pinctrl-names = "default";
336                 pinctrl-0 = <&pinctrl_tsc2007>;
337                 interrupt-parent = <&gpio3>;
338                 interrupts = <26 0>;
339                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
340                 ti,x-plate-ohms = <660>;
341                 linux,wakeup;
342         };
343 };
344
345 &iomuxc {
346         pinctrl-names = "default";
347         pinctrl-0 = <&pinctrl_hog>;
348
349         imx6qdl-tx6 {
350                 pinctrl_hog: hoggrp {
351                         fsl,pins = <
352                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
353                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
354                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
355                         >;
356                 };
357
358                 pinctrl_disp0_1: disp0grp-1 {
359                         fsl,pins = <
360                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
361                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
362                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
363                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
364                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
365                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
366                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
367                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
368                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
369                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
370                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
371                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
372                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
373                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
374                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
375                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
376                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
377                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
378                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
379                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
380                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
381                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
382                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
383                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
384                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
385                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
386                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
387                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
388                         >;
389                 };
390
391                 pinctrl_disp0_2: disp0grp-2 {
392                         fsl,pins = <
393                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
394                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
395                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
396                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
397                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
398                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
399                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
400                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
401                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
402                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
403                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
404                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
405                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
406                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
407                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
408                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
409                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
410                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
411                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
412                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
413                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
414                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
415                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
416                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
417                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
418                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
419                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
420                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
421                         >;
422                 };
423
424                 pinctrl_ecspi2: ecspi2grp {
425                         fsl,pins = <
426                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
427                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
428                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
429                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
430                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
431                         >;
432                 };
433
434                 pinctrl_edt_ft5x06: edt-ft5x06grp {
435                         fsl,pins = <
436                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
437                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
438                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
439                         >;
440                 };
441
442                 pinctrl_enet1: enet1grp {
443                         fsl,pins = <
444                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
445                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
446                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
447                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
448                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
449                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
450                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
451                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
452                         >;
453                 };
454
455                 pinctrl_enet2: enet2grp {
456                         fsl,pins = <
457                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
458                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
459                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
460                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
461                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
462                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
463                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
464                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
465                         >;
466                 };
467
468                 pinctrl_enet_mdio: enet-mdiogrp {
469                         fsl,pins = <
470                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
471                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
472                         >;
473                 };
474
475                 pinctrl_etnphy_power: etnphy-pwrgrp {
476                         fsl,pins = <
477                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
478                         >;
479                 };
480
481                 pinctrl_flexcan1: flexcan1grp {
482                         fsl,pins = <
483                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
484                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
485                         >;
486                 };
487
488                 pinctrl_flexcan2: flexcan2grp {
489                         fsl,pins = <
490                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
491                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
492                         >;
493                 };
494
495                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
496                         fsl,pins = <
497                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
498                         >;
499                 };
500
501                 pinctrl_gpmi_nand: gpminandgrp {
502                         fsl,pins = <
503                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
504                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
505                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
506                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
507                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
508                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
509                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
510                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
511                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
512                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
513                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
514                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
515                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
516                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
517                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
518                         >;
519                 };
520
521                 pinctrl_i2c_gpio: i2c-gpiogrp {
522                         fsl,pins = <
523                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
524                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
525                         >;
526                 };
527
528                 pinctrl_i2c2: i2c2grp {
529                         fsl,pins = <
530                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
531                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
532                         >;
533                 };
534
535                 pinctrl_kpp: kppgrp {
536                         fsl,pins = <
537                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
538                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
539                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
540                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
541                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
542                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
543                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
544                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
545                         >;
546                 };
547
548                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
549                         fsl,pins = <
550                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
551                         >;
552                 };
553
554                 pinctrl_pwm5: pwm5grp {
555                         fsl,pins = <
556                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
557                         >;
558                 };
559
560                 pinctrl_sai2: sai2grp {
561                         fsl,pins = <
562                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
563                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
564                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
565                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
566                         >;
567                 };
568
569                 pinctrl_spi_gpio: spi-gpiogrp {
570                         fsl,pins = <
571                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
572                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
573                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
574                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
575                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
576                         >;
577                 };
578
579                 pinctrl_tsc2007: tsc2007grp {
580                         fsl,pins = <
581                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
582                         >;
583                 };
584
585                 pinctrl_uart1: uart1grp {
586                         fsl,pins = <
587                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
588                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
589                         >;
590                 };
591
592                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
593                         fsl,pins = <
594                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
595                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
596                         >;
597                 };
598
599                 pinctrl_uart2: uart2grp {
600                         fsl,pins = <
601                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
602                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
603                         >;
604                 };
605
606                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
607                         fsl,pins = <
608                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
609                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
610                         >;
611                 };
612
613                 pinctrl_uart5: uart5grp {
614                         fsl,pins = <
615                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
616                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
617                         >;
618                 };
619
620                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
621                         fsl,pins = <
622                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
623                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
624                         >;
625                 };
626
627                 pinctrl_usbh1_oc: usbh1-ocgrp {
628                         fsl,pins = <
629                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
630                         >;
631                 };
632
633                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
634                         fsl,pins = <
635                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
636                         >;
637                 };
638
639                 pinctrl_usbotg_oc: usbotg-ocgrp {
640                         fsl,pins = <
641                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
642                         >;
643                 };
644
645                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
646                         fsl,pins = <
647                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
648                         >;
649                 };
650
651                 pinctrl_usdhc1: usdhc1grp {
652                         fsl,pins = <
653                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
654                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
655                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
656                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
657                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
658                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
659                                 /* SD1 CD */
660                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
661                         >;
662                 };
663                 pinctrl_usdhc2: usdhc2grp {
664                         fsl,pins = <
665                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
666                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
667                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
668                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
669                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
670                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
671                                 /* eMMC RESET */
672                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
673                         >;
674                 };
675         };
676 };
677
678 &kpp {
679         pinctrl-names = "default";
680         pinctrl-0 = <&pinctrl_kpp>;
681         /* sample keymap */
682         /* row/col 0,1 are mapped to KPP row/col 6,7 */
683         linux,keymap = <
684                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
685                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
686                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
687                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
688                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
689                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
690                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
691                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
692                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
693                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
694                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
695         >;
696         status = "okay";
697 };
698
699 &lcdif {
700         pinctrl-names = "default";
701         pinctrl-0 = <&pinctrl_disp0_1>;
702         lcd-supply = <&reg_lcd_pwr>;
703         display = <&display>;
704         status = "okay";
705
706         display: display@di0 {
707                 bits-per-pixel = <32>;
708                 bus-width = <24>;
709                 status = "okay";
710
711                 display-timings {
712                         VGA {
713                                 clock-frequency = <25200000>;
714                                 hactive = <640>;
715                                 vactive = <480>;
716                                 hback-porch = <48>;
717                                 hsync-len = <96>;
718                                 hfront-porch = <16>;
719                                 vback-porch = <31>;
720                                 vsync-len = <2>;
721                                 vfront-porch = <12>;
722                                 hsync-active = <0>;
723                                 vsync-active = <0>;
724                                 de-active = <1>;
725                                 pixelclk-active = <0>;
726                         };
727
728                         ETV570 {
729                                 clock-frequency = <25200000>;
730                                 hactive = <640>;
731                                 vactive = <480>;
732                                 hback-porch = <114>;
733                                 hsync-len = <30>;
734                                 hfront-porch = <16>;
735                                 vback-porch = <32>;
736                                 vsync-len = <3>;
737                                 vfront-porch = <10>;
738                                 hsync-active = <0>;
739                                 vsync-active = <0>;
740                                 de-active = <1>;
741                                 pixelclk-active = <0>;
742                         };
743
744                         ET0350 {
745                                 clock-frequency = <6413760>;
746                                 hactive = <320>;
747                                 vactive = <240>;
748                                 hback-porch = <34>;
749                                 hsync-len = <34>;
750                                 hfront-porch = <20>;
751                                 vback-porch = <15>;
752                                 vsync-len = <3>;
753                                 vfront-porch = <4>;
754                                 hsync-active = <0>;
755                                 vsync-active = <0>;
756                                 de-active = <1>;
757                                 pixelclk-active = <0>;
758                         };
759
760                         ET0430 {
761                                 clock-frequency = <9009000>;
762                                 hactive = <480>;
763                                 vactive = <272>;
764                                 hback-porch = <2>;
765                                 hsync-len = <41>;
766                                 hfront-porch = <2>;
767                                 vback-porch = <2>;
768                                 vsync-len = <10>;
769                                 vfront-porch = <2>;
770                                 hsync-active = <0>;
771                                 vsync-active = <0>;
772                                 de-active = <1>;
773                                 pixelclk-active = <1>;
774                         };
775
776                         ET0500 {
777                                 clock-frequency = <33264000>;
778                                 hactive = <800>;
779                                 vactive = <480>;
780                                 hback-porch = <88>;
781                                 hsync-len = <128>;
782                                 hfront-porch = <40>;
783                                 vback-porch = <33>;
784                                 vsync-len = <2>;
785                                 vfront-porch = <10>;
786                                 hsync-active = <0>;
787                                 vsync-active = <0>;
788                                 de-active = <1>;
789                                 pixelclk-active = <0>;
790                         };
791
792                         ET0700 { /* same as ET0500 */
793                                 clock-frequency = <33264000>;
794                                 hactive = <800>;
795                                 vactive = <480>;
796                                 hback-porch = <88>;
797                                 hsync-len = <128>;
798                                 hfront-porch = <40>;
799                                 vback-porch = <33>;
800                                 vsync-len = <2>;
801                                 vfront-porch = <10>;
802                                 hsync-active = <0>;
803                                 vsync-active = <0>;
804                                 de-active = <1>;
805                                 pixelclk-active = <0>;
806                         };
807
808                         ETQ570 {
809                                 clock-frequency = <6596040>;
810                                 hactive = <320>;
811                                 vactive = <240>;
812                                 hback-porch = <38>;
813                                 hsync-len = <30>;
814                                 hfront-porch = <30>;
815                                 vback-porch = <16>;
816                                 vsync-len = <3>;
817                                 vfront-porch = <4>;
818                                 hsync-active = <0>;
819                                 vsync-active = <0>;
820                                 de-active = <1>;
821                                 pixelclk-active = <0>;
822                         };
823                 };
824         };
825 };
826
827 &pwm5 {
828         pinctrl-names = "default";
829         pinctrl-0 = <&pinctrl_pwm5>;
830         #pwm-cells = <3>;
831         status = "okay";
832 };
833
834 &sai2 {
835         pinctrl-names = "default";
836         pinctrl-0 = <&pinctrl_sai2>;
837         status = "okay";
838 };
839
840 &uart1 {
841         pinctrl-names = "default";
842         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
843         status = "okay";
844 };
845
846 &uart2 {
847         pinctrl-names = "default";
848         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
849         status = "okay";
850 };
851
852 &uart5 {
853         pinctrl-names = "default";
854         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
855         status = "okay";
856 };
857
858 &usbotg2 {
859         vbus-supply = <&reg_usbh1_vbus>;
860         dr_mode = "host";
861         disable-over-current;
862         status = "okay";
863 };
864
865 &usbotg1 {
866         vbus-supply = <&reg_usbotg_vbus>;
867         dr_mode = "peripheral";
868         disable-over-current;
869         status = "okay";
870 };
871
872 &usdhc1 {
873         pinctrl-names = "default";
874         pinctrl-0 = <&pinctrl_usdhc1>;
875         bus-width = <4>;
876         no-1-8-v;
877         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
878         fsl,wp-controller;
879         status = "okay";
880 };