53a12adfa04cf83d2fd343884c9ffd3c269c6be9
[karo-tx-linux.git] / arch / arm / boot / dts / imx6ul-tx6ul.dtsi
1 /*
2  * Copyright 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10
11 / {
12         aliases {
13                 can0 = &can2;
14                 can1 = &can1;
15                 display = &display;
16                 i2c0 = &i2c_gpio;
17                 i2c1 = &i2c2;
18                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
19                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
20                 pwm0 = &pwm5;
21                 reg_can_xcvr = &reg_can_xcvr;
22                 serial2 = &uart5;
23 //              spi0 = &ecspi2;
24                 spi0 = &spi_gpio;
25                 stk5led = &user_led;
26                 usbh1 = &usbotg2;
27                 usbotg = &usbotg1;
28         };
29
30         chosen {
31                 stdout-path = &uart1;
32         };
33
34         memory {
35                 reg = <0 0>; /* will be filled by U-Boot */
36         };
37
38         clocks {
39                 #address-cells = <1>;
40                 #size-cells = <0>;
41                 mclk: clock@0 {
42                         compatible = "fixed-clock";
43                         reg = <0>;
44                         #clock-cells = <0>;
45                         clock-frequency = <27000000>;
46                 };
47         };
48
49         backlight: backlight {
50                 compatible = "pwm-backlight";
51                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
52                 power-supply = <&reg_3v3>;
53                 /*
54                  * a poor man's way to create a 1:1 relationship between
55                  * the PWM value and the actual duty cycle
56                  */
57                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
58                                      10 11 12 13 14 15 16 17 18 19
59                                      20 21 22 23 24 25 26 27 28 29
60                                      30 31 32 33 34 35 36 37 38 39
61                                      40 41 42 43 44 45 46 47 48 49
62                                      50 51 52 53 54 55 56 57 58 59
63                                      60 61 62 63 64 65 66 67 68 69
64                                      70 71 72 73 74 75 76 77 78 79
65                                      80 81 82 83 84 85 86 87 88 89
66                                      90 91 92 93 94 95 96 97 98 99
67                                     100>;
68                 default-brightness-level = <50>;
69         };
70
71         gpio-keys {
72                 compatible = "gpio-keys";
73         };
74
75         i2c_gpio: i2c-gpio {
76                 compatible = "i2c-gpio";
77                 #address-cells = <1>;
78                 #size-cells = <0>;
79                 pinctrl-names = "default";
80                 pinctrl-0 = <&pinctrl_i2c_gpio>;
81                 gpios = <
82                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
83                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
84                 >;
85                 clock-frequency = <400000>;
86                 status = "okay";
87
88                 ds1339: rtc@68 {
89                         compatible = "dallas,ds1339";
90                         reg = <0x68>;
91                         status = "disabled";
92                 };
93         };
94
95         leds {
96                 compatible = "gpio-leds";
97
98                 user_led: user {
99                         label = "Heartbeat";
100                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
101                         linux,default-trigger = "heartbeat";
102                 };
103         };
104
105         regulators {
106                 compatible = "simple-bus";
107                 #address-cells = <1>;
108                 #size-cells = <0>;
109
110                 reg_3v3_etn: regulator@0 {
111                         compatible = "regulator-fixed";
112                         reg = <0>;
113                         regulator-name = "3V3_ETN";
114                         regulator-min-microvolt = <3300000>;
115                         regulator-max-microvolt = <3300000>;
116                         pinctrl-names = "default";
117                         pinctrl-0 = <&pinctrl_etnphy_power>;
118                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
119                         enable-active-high;
120                 };
121
122                 reg_2v5: regulator@1 {
123                         compatible = "regulator-fixed";
124                         reg = <1>;
125                         regulator-name = "2V5";
126                         regulator-min-microvolt = <2500000>;
127                         regulator-max-microvolt = <2500000>;
128                         regulator-always-on;
129                 };
130
131                 reg_3v3: regulator@2 {
132                         compatible = "regulator-fixed";
133                         reg = <2>;
134                         regulator-name = "3V3";
135                         regulator-min-microvolt = <3300000>;
136                         regulator-max-microvolt = <3300000>;
137                         regulator-always-on;
138                 };
139
140                 reg_can_xcvr: regulator@3 {
141                         compatible = "regulator-fixed";
142                         reg = <3>;
143                         regulator-name = "CAN XCVR";
144                         regulator-min-microvolt = <3300000>;
145                         regulator-max-microvolt = <3300000>;
146                         pinctrl-names = "default";
147                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
148                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
149                         enable-active-low;
150                 };
151
152                 reg_lcd_pwr: regulator@5 {
153                         compatible = "regulator-fixed";
154                         reg = <5>;
155                         regulator-name = "LCD POWER";
156                         regulator-min-microvolt = <3300000>;
157                         regulator-max-microvolt = <3300000>;
158                         pinctrl-names = "default";
159                         pinctrl-0 = <&pinctrl_lcd_pwr>;
160                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161                         enable-active-high;
162                         regulator-boot-on;
163                         regulator-always-on;
164                 };
165
166                 reg_lcd_reset: regulator@6 {
167                         compatible = "regulator-fixed";
168                         reg = <6>;
169                         regulator-name = "LCD RESET";
170                         regulator-min-microvolt = <3300000>;
171                         regulator-max-microvolt = <3300000>;
172                         pinctrl-names = "default";
173                         pinctrl-0 = <&pinctrl_lcd_reset>;
174                         gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
175                         enable-active-high;
176                         regulator-boot-on;
177                         regulator-always-on;
178                 };
179
180                 reg_usbh1_vbus: regulator@7 {
181                         compatible = "regulator-fixed";
182                         reg = <7>;
183                         regulator-name = "usbh1_vbus";
184                         regulator-min-microvolt = <5000000>;
185                         regulator-max-microvolt = <5000000>;
186                         pinctrl-names = "default";
187                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
188                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
189                         enable-active-high;
190                 };
191
192                 reg_usbotg_vbus: regulator@8 {
193                         compatible = "regulator-fixed";
194                         reg = <8>;
195                         regulator-name = "usbotg_vbus";
196                         regulator-min-microvolt = <5000000>;
197                         regulator-max-microvolt = <5000000>;
198                         pinctrl-names = "default";
199                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
200                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
201                         enable-active-high;
202                 };
203         };
204
205         spi_gpio: spi-gpio {
206                 #address-cells = <1>;
207                 #size-cells = <0>;
208                 compatible = "spi-gpio";
209                 pinctrl-names = "default";
210                 pinctrl-0 = <&pinctrl_spi_gpio>;
211                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
212                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
213                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
214                 num-chipselects = <2>;
215                 cs-gpios = <
216                         &gpio1 29 GPIO_ACTIVE_HIGH
217                         &gpio1 10 GPIO_ACTIVE_HIGH
218                 >;
219                 status = "okay";
220
221                 spidev0: spi@0 {
222                         compatible = "spidev";
223                         reg = <0>;
224                         spi-max-frequency = <54000000>;
225                 };
226
227                 spidev1: spi@1 {
228                         compatible = "spidev";
229                         reg = <1>;
230                         spi-max-frequency = <54000000>;
231                 };
232         };
233 };
234
235 &can1 {
236         pinctrl-names = "default";
237         pinctrl-0 = <&pinctrl_flexcan1>;
238         xceiver-supply = <&reg_can_xcvr>;
239         status = "okay";
240 };
241
242 &can2 {
243         pinctrl-names = "default";
244         pinctrl-0 = <&pinctrl_flexcan2>;
245         xceiver-supply = <&reg_can_xcvr>;
246         status = "okay";
247 };
248
249 #if 0
250 &ecspi2 {
251         pinctrl-names = "default";
252         pinctrl-0 = <&pinctrl_ecspi2>;
253         fsl,spi-num-chipselects = <2>;
254         cs-gpios = <
255                 &gpio1 29 GPIO_ACTIVE_HIGH
256                 &gpio1 10 GPIO_ACTIVE_HIGH
257         >;
258         status = "okay";
259
260         spidev0: spi@0 {
261                 compatible = "spidev";
262                 reg = <0>;
263                 spi-max-frequency = <54000000>;
264         };
265
266         spidev1: spi@1 {
267                 compatible = "spidev";
268                 reg = <1>;
269                 spi-max-frequency = <54000000>;
270         };
271 };
272 #endif
273
274 &fec1 {
275         pinctrl-names = "default";
276         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
277         phy-mode = "rmii";
278         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
279         phy-supply = <&reg_3v3_etn>;
280         phy-handle = <&etnphy0>;
281         status = "okay";
282
283         mdio {
284                 #address-cells = <1>;
285                 #size-cells = <0>;
286
287                 etnphy0: ethernet-phy@0 {
288                         compatible = "ethernet-phy-ieee802.3-c22";
289                         reg = <0>;
290                         interrupt-parent = <&gpio5>;
291                         interrupts = <5>;
292                         status = "okay";
293                 };
294
295                 etnphy1: ethernet-phy@1 {
296                         compatible = "ethernet-phy-ieee802.3-c22";
297                         reg = <1>;
298                         status = "okay";
299                 };
300         };
301 };
302
303 &fec2 {
304         pinctrl-names = "default";
305         pinctrl-0 = <&pinctrl_enet2>;
306         phy-mode = "rmii";
307         phy-supply = <&reg_3v3_etn>;
308         phy-handle = <&etnphy1>;
309         status = "okay";
310 };
311
312 &gpmi {
313         pinctrl-names = "default";
314         pinctrl-0 = <&pinctrl_gpmi_nand>;
315         nand-on-flash-bbt;
316         fsl,no-blockmark-swap;
317         status = "okay";
318 };
319
320 &i2c2 {
321         pinctrl-names = "default";
322         pinctrl-0 = <&pinctrl_i2c2>;
323         clock-frequency = <400000>;
324         status = "okay";
325
326         sgtl5000: sgtl5000@0a {
327                 compatible = "fsl,sgtl5000";
328                 reg = <0x0a>;
329                 VDDA-supply = <&reg_2v5>;
330                 VDDIO-supply = <&reg_3v3>;
331                 clocks = <&mclk>;
332         };
333
334         polytouch: edt-ft5x06@38 {
335                 compatible = "edt,edt-ft5x06";
336                 reg = <0x38>;
337                 pinctrl-names = "default";
338                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
339                 interrupt-parent = <&gpio5>;
340                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
341                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
342                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
343                 linux,wakeup;
344         };
345
346         touchscreen: tsc2007@48 {
347                 compatible = "ti,tsc2007";
348                 reg = <0x48>;
349                 pinctrl-names = "default";
350                 pinctrl-0 = <&pinctrl_tsc2007>;
351                 interrupt-parent = <&gpio3>;
352                 interrupts = <26 0>;
353                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
354                 ti,x-plate-ohms = <660>;
355                 linux,wakeup;
356         };
357 };
358
359 &iomuxc {
360         pinctrl-names = "default";
361         pinctrl-0 = <&pinctrl_hog>;
362
363         imx6qdl-tx6 {
364                 pinctrl_hog: hoggrp {
365                         fsl,pins = <
366                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
367                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
368                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
369                         >;
370                 };
371
372                 pinctrl_disp0_1: disp0grp-1 {
373                         fsl,pins = <
374                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
375                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
376                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
377                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
378                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
379                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
380                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
381                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
382                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
383                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
384                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
385                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
386                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
387                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
388                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
389                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
390                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
391                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
392                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
393                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
394                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
395                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
396                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
397                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
398                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
399                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
400                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
401                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
402                         >;
403                 };
404
405                 pinctrl_disp0_2: disp0grp-2 {
406                         fsl,pins = <
407                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
408                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
409                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
410                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
411                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
412                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
413                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
414                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
415                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
416                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
417                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
418                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
419                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
420                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
421                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
422                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
423                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
424                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
425                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
426                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
427                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
428                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
429                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
430                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
431                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
432                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
433                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
434                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
435                         >;
436                 };
437
438                 pinctrl_ecspi2: ecspi2grp {
439                         fsl,pins = <
440                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
441                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
442                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
443                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
444                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
445                         >;
446                 };
447
448                 pinctrl_edt_ft5x06: edt-ft5x06grp {
449                         fsl,pins = <
450                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
451                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
452                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
453                         >;
454                 };
455
456                 pinctrl_enet1: enet1grp {
457                         fsl,pins = <
458                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
459                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
460                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
461                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
462                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
463                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
464                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
465                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
466                         >;
467                 };
468
469                 pinctrl_enet2: enet2grp {
470                         fsl,pins = <
471                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
472                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
473                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
474                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
475                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
476                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
477                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
478                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
479                         >;
480                 };
481
482                 pinctrl_enet_mdio: enet-mdiogrp {
483                         fsl,pins = <
484                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
485                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
486                         >;
487                 };
488
489                 pinctrl_etnphy_power: etnphy-pwrgrp {
490                         fsl,pins = <
491                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
492                         >;
493                 };
494
495                 pinctrl_flexcan1: flexcan1grp {
496                         fsl,pins = <
497                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
498                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
499                         >;
500                 };
501
502                 pinctrl_flexcan2: flexcan2grp {
503                         fsl,pins = <
504                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
505                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
506                         >;
507                 };
508
509                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
510                         fsl,pins = <
511                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
512                         >;
513                 };
514
515                 pinctrl_gpmi_nand: gpminandgrp {
516                         fsl,pins = <
517                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
518                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
519                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
520                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
521                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
522                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
523                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
524                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
525                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
526                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
527                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
528                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
529                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
530                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
531                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
532                         >;
533                 };
534
535                 pinctrl_i2c_gpio: i2c-gpiogrp {
536                         fsl,pins = <
537                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
538                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
539                         >;
540                 };
541
542                 pinctrl_i2c2: i2c2grp {
543                         fsl,pins = <
544                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
545                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
546                         >;
547                 };
548
549                 pinctrl_kpp: kppgrp {
550                         fsl,pins = <
551                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
552                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
553                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
554                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
555                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
556                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
557                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
558                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
559                         >;
560                 };
561
562                 pinctrl_lcd_pwr: lcd-pwrgrp {
563                         fsl,pins = <
564                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
565                         >;
566                 };
567
568                 pinctrl_lcd_reset: lcd-resetgrp {
569                         fsl,pins = <
570                                 MX6UL_PAD_LCD_RESET__GPIO3_IO04         0x0b0b0 /* LCD RESET */
571                         >;
572                 };
573
574                 pinctrl_pwm5: pwm5grp {
575                         fsl,pins = <
576                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
577                         >;
578                 };
579
580                 pinctrl_sai2: sai2grp {
581                         fsl,pins = <
582                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
583                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
584                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
585                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
586                         >;
587                 };
588
589                 pinctrl_spi_gpio: spi-gpiogrp {
590                         fsl,pins = <
591                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
592                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
593                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
594                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
595                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
596                         >;
597                 };
598
599                 pinctrl_tsc2007: tsc2007grp {
600                         fsl,pins = <
601                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
602                         >;
603                 };
604
605                 pinctrl_uart1: uart1grp {
606                         fsl,pins = <
607                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
608                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
609                         >;
610                 };
611
612                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
613                         fsl,pins = <
614                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
615                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
616                         >;
617                 };
618
619                 pinctrl_uart2: uart2grp {
620                         fsl,pins = <
621                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
622                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
623                         >;
624                 };
625
626                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
627                         fsl,pins = <
628                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
629                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
630                         >;
631                 };
632
633                 pinctrl_uart5: uart5grp {
634                         fsl,pins = <
635                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
636                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
637                         >;
638                 };
639
640                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
641                         fsl,pins = <
642                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
643                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
644                         >;
645                 };
646
647                 pinctrl_usbh1_oc: usbh1-ocgrp {
648                         fsl,pins = <
649                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
650                         >;
651                 };
652
653                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
654                         fsl,pins = <
655                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
656                         >;
657                 };
658
659                 pinctrl_usbotg_oc: usbotg-ocgrp {
660                         fsl,pins = <
661                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
662                         >;
663                 };
664
665                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
666                         fsl,pins = <
667                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
668                         >;
669                 };
670
671                 pinctrl_usdhc1: usdhc1grp {
672                         fsl,pins = <
673                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
674                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
675                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
676                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
677                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
678                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
679                                 /* SD1 CD */
680                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
681                         >;
682                 };
683                 pinctrl_usdhc2: usdhc2grp {
684                         fsl,pins = <
685                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
686                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
687                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
688                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
689                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
690                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
691                                 /* eMMC RESET */
692                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
693                         >;
694                 };
695         };
696 };
697
698 &kpp {
699         pinctrl-names = "default";
700         pinctrl-0 = <&pinctrl_kpp>;
701         /* sample keymap */
702         /* row/col 0,1 are mapped to KPP row/col 6,7 */
703         linux,keymap = <
704                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
705                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
706                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
707                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
708                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
709                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
710                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
711                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
712                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
713                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
714                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
715         >;
716         status = "okay";
717 };
718
719 &lcdif {
720         pinctrl-names = "default";
721         pinctrl-0 = <&pinctrl_disp0_1>;
722         lcd-supply = <&reg_lcd_pwr>;
723         display = <&display>;
724         status = "okay";
725
726         display: display@di0 {
727                 bits-per-pixel = <32>;
728                 bus-width = <24>;
729                 status = "okay";
730
731                 display-timings {
732                         VGA {
733                                 clock-frequency = <25200000>;
734                                 hactive = <640>;
735                                 vactive = <480>;
736                                 hback-porch = <48>;
737                                 hsync-len = <96>;
738                                 hfront-porch = <16>;
739                                 vback-porch = <31>;
740                                 vsync-len = <2>;
741                                 vfront-porch = <12>;
742                                 hsync-active = <0>;
743                                 vsync-active = <0>;
744                                 de-active = <1>;
745                                 pixelclk-active = <0>;
746                         };
747
748                         ETV570 {
749                                 clock-frequency = <25200000>;
750                                 hactive = <640>;
751                                 vactive = <480>;
752                                 hback-porch = <114>;
753                                 hsync-len = <30>;
754                                 hfront-porch = <16>;
755                                 vback-porch = <32>;
756                                 vsync-len = <3>;
757                                 vfront-porch = <10>;
758                                 hsync-active = <0>;
759                                 vsync-active = <0>;
760                                 de-active = <1>;
761                                 pixelclk-active = <0>;
762                         };
763
764                         ET0350 {
765                                 clock-frequency = <6413760>;
766                                 hactive = <320>;
767                                 vactive = <240>;
768                                 hback-porch = <34>;
769                                 hsync-len = <34>;
770                                 hfront-porch = <20>;
771                                 vback-porch = <15>;
772                                 vsync-len = <3>;
773                                 vfront-porch = <4>;
774                                 hsync-active = <0>;
775                                 vsync-active = <0>;
776                                 de-active = <1>;
777                                 pixelclk-active = <0>;
778                         };
779
780                         ET0430 {
781                                 clock-frequency = <9009000>;
782                                 hactive = <480>;
783                                 vactive = <272>;
784                                 hback-porch = <2>;
785                                 hsync-len = <41>;
786                                 hfront-porch = <2>;
787                                 vback-porch = <2>;
788                                 vsync-len = <10>;
789                                 vfront-porch = <2>;
790                                 hsync-active = <0>;
791                                 vsync-active = <0>;
792                                 de-active = <1>;
793                                 pixelclk-active = <1>;
794                         };
795
796                         ET0500 {
797                                 clock-frequency = <33264000>;
798                                 hactive = <800>;
799                                 vactive = <480>;
800                                 hback-porch = <88>;
801                                 hsync-len = <128>;
802                                 hfront-porch = <40>;
803                                 vback-porch = <33>;
804                                 vsync-len = <2>;
805                                 vfront-porch = <10>;
806                                 hsync-active = <0>;
807                                 vsync-active = <0>;
808                                 de-active = <1>;
809                                 pixelclk-active = <0>;
810                         };
811
812                         ET0700 { /* same as ET0500 */
813                                 clock-frequency = <33264000>;
814                                 hactive = <800>;
815                                 vactive = <480>;
816                                 hback-porch = <88>;
817                                 hsync-len = <128>;
818                                 hfront-porch = <40>;
819                                 vback-porch = <33>;
820                                 vsync-len = <2>;
821                                 vfront-porch = <10>;
822                                 hsync-active = <0>;
823                                 vsync-active = <0>;
824                                 de-active = <1>;
825                                 pixelclk-active = <0>;
826                         };
827
828                         ETQ570 {
829                                 clock-frequency = <6596040>;
830                                 hactive = <320>;
831                                 vactive = <240>;
832                                 hback-porch = <38>;
833                                 hsync-len = <30>;
834                                 hfront-porch = <30>;
835                                 vback-porch = <16>;
836                                 vsync-len = <3>;
837                                 vfront-porch = <4>;
838                                 hsync-active = <0>;
839                                 vsync-active = <0>;
840                                 de-active = <1>;
841                                 pixelclk-active = <0>;
842                         };
843                 };
844         };
845 };
846
847 &pwm5 {
848         pinctrl-names = "default";
849         pinctrl-0 = <&pinctrl_pwm5>;
850         #pwm-cells = <3>;
851         status = "okay";
852 };
853
854 &sai2 {
855         pinctrl-names = "default";
856         pinctrl-0 = <&pinctrl_sai2>;
857         status = "okay";
858 };
859
860 &uart1 {
861         pinctrl-names = "default";
862         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
863         status = "okay";
864 };
865
866 &uart2 {
867         pinctrl-names = "default";
868         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
869         status = "okay";
870 };
871
872 &uart5 {
873         pinctrl-names = "default";
874         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
875         status = "okay";
876 };
877
878 &usbotg2 {
879         vbus-supply = <&reg_usbh1_vbus>;
880         dr_mode = "host";
881         disable-over-current;
882         status = "okay";
883 };
884
885 &usbotg1 {
886         vbus-supply = <&reg_usbotg_vbus>;
887         dr_mode = "peripheral";
888         disable-over-current;
889         status = "okay";
890 };
891
892 &usdhc1 {
893         pinctrl-names = "default";
894         pinctrl-0 = <&pinctrl_usdhc1>;
895         bus-width = <4>;
896         no-1-8-v;
897         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
898         fsl,wp-controller;
899         status = "okay";
900 };