arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46
  47 / {
  48         aliases {
  49                 can0 = &can2;
  50                 can1 = &can1;
  51                 display = &display;
  52                 i2c0 = &i2c_gpio;
  53                 i2c1 = &i2c2;
  54                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  55                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  56                 pwm0 = &pwm5;
  57                 reg_can_xcvr = &reg_can_xcvr;
  58                 serial2 = &uart5;
  59 //              spi0 = &ecspi2;
  60                 spi0 = &spi_gpio;
  61                 stk5led = &user_led;
  62                 usbh1 = &usbotg2;
  63                 usbotg = &usbotg1;
  64         };
  65
  66         chosen {
  67                 stdout-path = &uart1;
  68         };
  69
  70         memory {
  71                 reg = <0 0>; /* will be filled by U-Boot */
  72         };
  73
  74         clocks {
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 mclk: clock@0 {
  78                         compatible = "fixed-clock";
  79                         reg = <0>;
  80                         #clock-cells = <0>;
  81                         clock-frequency = <27000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  88                 power-supply = <&reg_3v3>;
  89                 /*
  90                  * a poor man's way to create a 1:1 relationship between
  91                  * the PWM value and the actual duty cycle
  92                  */
  93                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  94                                      10 11 12 13 14 15 16 17 18 19
  95                                      20 21 22 23 24 25 26 27 28 29
  96                                      30 31 32 33 34 35 36 37 38 39
  97                                      40 41 42 43 44 45 46 47 48 49
  98                                      50 51 52 53 54 55 56 57 58 59
  99                                      60 61 62 63 64 65 66 67 68 69
 100                                      70 71 72 73 74 75 76 77 78 79
 101                                      80 81 82 83 84 85 86 87 88 89
 102                                      90 91 92 93 94 95 96 97 98 99
 103                                     100>;
 104                 default-brightness-level = <50>;
 105         };
 106
 107         gpio-keys {
 108                 compatible = "gpio-keys";
 109         };
 110
 111         i2c_gpio: i2c-gpio {
 112                 compatible = "i2c-gpio";
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 117                 gpios = <
 118                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 119                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 120                 >;
 121                 clock-frequency = <400000>;
 122                 status = "okay";
 123
 124                 ds1339: rtc@68 {
 125                         compatible = "dallas,ds1339";
 126                         reg = <0x68>;
 127                         status = "disabled";
 128                 };
 129         };
 130
 131         leds {
 132                 compatible = "gpio-leds";
 133
 134                 user_led: user {
 135                         label = "Heartbeat";
 136                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 137                         linux,default-trigger = "heartbeat";
 138                 };
 139         };
 140
 141         regulators {
 142                 compatible = "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145
 146                 reg_3v3_etn: regulator@0 {
 147                         compatible = "regulator-fixed";
 148                         reg = <0>;
 149                         regulator-name = "3V3_ETN";
 150                         regulator-min-microvolt = <3300000>;
 151                         regulator-max-microvolt = <3300000>;
 152                         pinctrl-names = "default";
 153                         pinctrl-0 = <&pinctrl_etnphy_power>;
 154                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 155                         enable-active-high;
 156                 };
 157
 158                 reg_2v5: regulator@1 {
 159                         compatible = "regulator-fixed";
 160                         reg = <1>;
 161                         regulator-name = "2V5";
 162                         regulator-min-microvolt = <2500000>;
 163                         regulator-max-microvolt = <2500000>;
 164                         regulator-always-on;
 165                 };
 166
 167                 reg_3v3: regulator@2 {
 168                         compatible = "regulator-fixed";
 169                         reg = <2>;
 170                         regulator-name = "3V3";
 171                         regulator-min-microvolt = <3300000>;
 172                         regulator-max-microvolt = <3300000>;
 173                         regulator-always-on;
 174                 };
 175
 176                 reg_can_xcvr: regulator@3 {
 177                         compatible = "regulator-fixed";
 178                         reg = <3>;
 179                         regulator-name = "CAN XCVR";
 180                         regulator-min-microvolt = <3300000>;
 181                         regulator-max-microvolt = <3300000>;
 182                         pinctrl-names = "default";
 183                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 184                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 185                         enable-active-low;
 186                 };
 187
 188                 reg_lcd_pwr: regulator@5 {
 189                         compatible = "regulator-fixed";
 190                         reg = <5>;
 191                         regulator-name = "LCD POWER";
 192                         regulator-min-microvolt = <3300000>;
 193                         regulator-max-microvolt = <3300000>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_lcd_pwr>;
 196                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 197                         enable-active-high;
 198                         regulator-boot-on;
 199                         regulator-always-on;
 200                 };
 201
 202                 reg_lcd_reset: regulator@6 {
 203                         compatible = "regulator-fixed";
 204                         reg = <6>;
 205                         regulator-name = "LCD RESET";
 206                         regulator-min-microvolt = <3300000>;
 207                         regulator-max-microvolt = <3300000>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&pinctrl_lcd_reset>;
 210                         gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 211                         enable-active-high;
 212                         regulator-boot-on;
 213                         regulator-always-on;
 214                 };
 215
 216                 reg_usbh1_vbus: regulator@7 {
 217                         compatible = "regulator-fixed";
 218                         reg = <7>;
 219                         regulator-name = "usbh1_vbus";
 220                         regulator-min-microvolt = <5000000>;
 221                         regulator-max-microvolt = <5000000>;
 222                         pinctrl-names = "default";
 223                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 224                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 225                         enable-active-high;
 226                 };
 227
 228                 reg_usbotg_vbus: regulator@8 {
 229                         compatible = "regulator-fixed";
 230                         reg = <8>;
 231                         regulator-name = "usbotg_vbus";
 232                         regulator-min-microvolt = <5000000>;
 233                         regulator-max-microvolt = <5000000>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 236                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 237                         enable-active-high;
 238                 };
 239         };
 240
 241         spi_gpio: spi-gpio {
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 compatible = "spi-gpio";
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&pinctrl_spi_gpio>;
 247                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 248                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 249                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 250                 num-chipselects = <2>;
 251                 cs-gpios = <
 252                         &gpio1 29 GPIO_ACTIVE_HIGH
 253                         &gpio1 10 GPIO_ACTIVE_HIGH
 254                 >;
 255                 status = "okay";
 256
 257                 spidev0: spi@0 {
 258                         compatible = "spidev";
 259                         reg = <0>;
 260                         spi-max-frequency = <54000000>;
 261                 };
 262
 263                 spidev1: spi@1 {
 264                         compatible = "spidev";
 265                         reg = <1>;
 266                         spi-max-frequency = <54000000>;
 267                 };
 268         };
 269 };
 270
 271 &can1 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_flexcan1>;
 274         xceiver-supply = <&reg_can_xcvr>;
 275         status = "okay";
 276 };
 277
 278 &can2 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_flexcan2>;
 281         xceiver-supply = <&reg_can_xcvr>;
 282         status = "okay";
 283 };
 284
 285 #if 0
 286 &ecspi2 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_ecspi2>;
 289         fsl,spi-num-chipselects = <2>;
 290         cs-gpios = <
 291                 &gpio1 29 GPIO_ACTIVE_HIGH
 292                 &gpio1 10 GPIO_ACTIVE_HIGH
 293         >;
 294         status = "okay";
 295
 296         spidev0: spi@0 {
 297                 compatible = "spidev";
 298                 reg = <0>;
 299                 spi-max-frequency = <54000000>;
 300         };
 301
 302         spidev1: spi@1 {
 303                 compatible = "spidev";
 304                 reg = <1>;
 305                 spi-max-frequency = <54000000>;
 306         };
 307 };
 308 #endif
 309
 310 &fec1 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
 313         phy-mode = "rmii";
 314         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
 315         phy-supply = <&reg_3v3_etn>;
 316         phy-handle = <&etnphy0>;
 317         status = "okay";
 318
 319         mdio {
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322
 323                 etnphy0: ethernet-phy@0 {
 324                         compatible = "ethernet-phy-ieee802.3-c22";
 325                         reg = <0>;
 326                         interrupt-parent = <&gpio5>;
 327                         interrupts = <5>;
 328                         status = "okay";
 329                 };
 330
 331                 etnphy1: ethernet-phy@1 {
 332                         compatible = "ethernet-phy-ieee802.3-c22";
 333                         reg = <1>;
 334                         status = "okay";
 335                 };
 336         };
 337 };
 338
 339 &fec2 {
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_enet2>;
 342         phy-mode = "rmii";
 343         phy-supply = <&reg_3v3_etn>;
 344         phy-handle = <&etnphy1>;
 345         status = "disabled";
 346 };
 347
 348 &gpmi {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_gpmi_nand>;
 351         nand-on-flash-bbt;
 352         fsl,no-blockmark-swap;
 353         status = "okay";
 354 };
 355
 356 &i2c2 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_i2c2>;
 359         clock-frequency = <400000>;
 360         status = "okay";
 361
 362         sgtl5000: sgtl5000@0a {
 363                 compatible = "fsl,sgtl5000";
 364                 reg = <0x0a>;
 365                 VDDA-supply = <&reg_2v5>;
 366                 VDDIO-supply = <&reg_3v3>;
 367                 clocks = <&mclk>;
 368         };
 369
 370         polytouch: edt-ft5x06@38 {
 371                 compatible = "edt,edt-ft5x06";
 372                 reg = <0x38>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 375                 interrupt-parent = <&gpio5>;
 376                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 377                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 378                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 379                 linux,wakeup;
 380         };
 381
 382         touchscreen: tsc2007@48 {
 383                 compatible = "ti,tsc2007";
 384                 reg = <0x48>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&pinctrl_tsc2007>;
 387                 interrupt-parent = <&gpio3>;
 388                 interrupts = <26 0>;
 389                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 390                 ti,x-plate-ohms = <660>;
 391                 linux,wakeup;
 392         };
 393 };
 394
 395 &iomuxc {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_hog>;
 398
 399         imx6qdl-tx6 {
 400                 pinctrl_hog: hoggrp {
 401                         fsl,pins = <
 402                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 403                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 404                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 405                         >;
 406                 };
 407
 408                 pinctrl_disp0_1: disp0grp-1 {
 409                         fsl,pins = <
 410                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 411                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 412                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
 413                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
 414                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 415                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 416                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 417                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 418                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 419                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 420                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 421                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 422                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 423                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 424                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 425                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 426                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 427                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 428                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 429                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 430                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 431                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 432                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 433                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 434                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 435                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 436                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 437                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 438                         >;
 439                 };
 440
 441                 pinctrl_disp0_2: disp0grp-2 {
 442                         fsl,pins = <
 443                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 444                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 445                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 446                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 447                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 448                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 449                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 450                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 451                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 452                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 453                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 454                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 455                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 456                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 457                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 458                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 459                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 460                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 461                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 462                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 463                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 464                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 465                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 466                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 467                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 468                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 469                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 470                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 471                         >;
 472                 };
 473
 474                 pinctrl_ecspi2: ecspi2grp {
 475                         fsl,pins = <
 476                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 477                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 478                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 479                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 480                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 481                         >;
 482                 };
 483
 484                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 485                         fsl,pins = <
 486                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 487                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 488                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 489                         >;
 490                 };
 491
 492                 pinctrl_enet1: enet1grp {
 493                         fsl,pins = <
 494                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
 495                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
 496                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
 497                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
 498                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
 499                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
 500                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
 501                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
 502                         >;
 503                 };
 504
 505                 pinctrl_enet2: enet2grp {
 506                         fsl,pins = <
 507                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
 508                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
 509                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
 510                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
 511                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
 512                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
 513                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
 514                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
 515                         >;
 516                 };
 517
 518                 pinctrl_enet_mdio: enet-mdiogrp {
 519                         fsl,pins = <
 520                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 521                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 522                         >;
 523                 };
 524
 525                 pinctrl_etnphy_power: etnphy-pwrgrp {
 526                         fsl,pins = <
 527                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 528                         >;
 529                 };
 530
 531                 pinctrl_flexcan1: flexcan1grp {
 532                         fsl,pins = <
 533                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
 534                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
 535                         >;
 536                 };
 537
 538                 pinctrl_flexcan2: flexcan2grp {
 539                         fsl,pins = <
 540                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
 541                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
 542                         >;
 543                 };
 544
 545                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 546                         fsl,pins = <
 547                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 548                         >;
 549                 };
 550
 551                 pinctrl_gpmi_nand: gpminandgrp {
 552                         fsl,pins = <
 553                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 554                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 555                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 556                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 557                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 558                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 559                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 560                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 561                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 562                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 563                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 564                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 565                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 566                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 567                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 568                         >;
 569                 };
 570
 571                 pinctrl_i2c_gpio: i2c-gpiogrp {
 572                         fsl,pins = <
 573                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 574                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 575                         >;
 576                 };
 577
 578                 pinctrl_i2c2: i2c2grp {
 579                         fsl,pins = <
 580                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 581                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 582                         >;
 583                 };
 584
 585                 pinctrl_kpp: kppgrp {
 586                         fsl,pins = <
 587                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 588                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 589                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 590                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 591                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 592                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 593                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 594                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 595                         >;
 596                 };
 597
 598                 pinctrl_lcd_pwr: lcd-pwrgrp {
 599                         fsl,pins = <
 600                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 601                         >;
 602                 };
 603
 604                 pinctrl_lcd_reset: lcd-resetgrp {
 605                         fsl,pins = <
 606                                 MX6UL_PAD_LCD_RESET__GPIO3_IO04         0x0b0b0 /* LCD RESET */
 607                         >;
 608                 };
 609
 610                 pinctrl_pwm5: pwm5grp {
 611                         fsl,pins = <
 612                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 613                         >;
 614                 };
 615
 616                 pinctrl_sai2: sai2grp {
 617                         fsl,pins = <
 618                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 619                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 620                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 621                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 622                         >;
 623                 };
 624
 625                 pinctrl_spi_gpio: spi-gpiogrp {
 626                         fsl,pins = <
 627                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 628                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 629                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 630                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 631                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 632                         >;
 633                 };
 634
 635                 pinctrl_tsc2007: tsc2007grp {
 636                         fsl,pins = <
 637                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 638                         >;
 639                 };
 640
 641                 pinctrl_uart1: uart1grp {
 642                         fsl,pins = <
 643                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 644                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 645                         >;
 646                 };
 647
 648                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 649                         fsl,pins = <
 650                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 651                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 652                         >;
 653                 };
 654
 655                 pinctrl_uart2: uart2grp {
 656                         fsl,pins = <
 657                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 658                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 659                         >;
 660                 };
 661
 662                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 663                         fsl,pins = <
 664                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 665                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 666                         >;
 667                 };
 668
 669                 pinctrl_uart5: uart5grp {
 670                         fsl,pins = <
 671                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 672                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 673                         >;
 674                 };
 675
 676                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
 677                         fsl,pins = <
 678                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 679                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 680                         >;
 681                 };
 682
 683                 pinctrl_usbh1_oc: usbh1-ocgrp {
 684                         fsl,pins = <
 685                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 686                         >;
 687                 };
 688
 689                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 690                         fsl,pins = <
 691                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 692                         >;
 693                 };
 694
 695                 pinctrl_usbotg_oc: usbotg-ocgrp {
 696                         fsl,pins = <
 697                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 698                         >;
 699                 };
 700
 701                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 702                         fsl,pins = <
 703                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 704                         >;
 705                 };
 706
 707                 pinctrl_usdhc1: usdhc1grp {
 708                         fsl,pins = <
 709                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 710                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 711                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 712                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 713                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 714                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 715                                 /* SD1 CD */
 716                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 717                         >;
 718                 };
 719                 pinctrl_usdhc2: usdhc2grp {
 720                         fsl,pins = <
 721                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 722                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 723                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 724                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 725                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 726                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 727                                 /* eMMC RESET */
 728                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 729                         >;
 730                 };
 731         };
 732 };
 733
 734 &kpp {
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&pinctrl_kpp>;
 737         /* sample keymap */
 738         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 739         linux,keymap = <
 740                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 741                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 742                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 743                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 744                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 745                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 746                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 747                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 748                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 749                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 750                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 751         >;
 752         status = "okay";
 753 };
 754
 755 &lcdif {
 756         pinctrl-names = "default";
 757         pinctrl-0 = <&pinctrl_disp0_1>;
 758         lcd-supply = <&reg_lcd_pwr>;
 759         display = <&display>;
 760         status = "okay";
 761
 762         display: display@di0 {
 763                 bits-per-pixel = <32>;
 764                 bus-width = <24>;
 765                 status = "okay";
 766
 767                 display-timings {
 768                         VGA {
 769                                 clock-frequency = <25200000>;
 770                                 hactive = <640>;
 771                                 vactive = <480>;
 772                                 hback-porch = <48>;
 773                                 hsync-len = <96>;
 774                                 hfront-porch = <16>;
 775                                 vback-porch = <31>;
 776                                 vsync-len = <2>;
 777                                 vfront-porch = <12>;
 778                                 hsync-active = <0>;
 779                                 vsync-active = <0>;
 780                                 de-active = <1>;
 781                                 pixelclk-active = <1>;
 782                         };
 783
 784                         ETV570 {
 785                                 clock-frequency = <25200000>;
 786                                 hactive = <640>;
 787                                 vactive = <480>;
 788                                 hback-porch = <114>;
 789                                 hsync-len = <30>;
 790                                 hfront-porch = <16>;
 791                                 vback-porch = <32>;
 792                                 vsync-len = <3>;
 793                                 vfront-porch = <10>;
 794                                 hsync-active = <0>;
 795                                 vsync-active = <0>;
 796                                 de-active = <1>;
 797                                 pixelclk-active = <1>;
 798                         };
 799
 800                         ET0350 {
 801                                 clock-frequency = <6413760>;
 802                                 hactive = <320>;
 803                                 vactive = <240>;
 804                                 hback-porch = <34>;
 805                                 hsync-len = <34>;
 806                                 hfront-porch = <20>;
 807                                 vback-porch = <15>;
 808                                 vsync-len = <3>;
 809                                 vfront-porch = <4>;
 810                                 hsync-active = <0>;
 811                                 vsync-active = <0>;
 812                                 de-active = <1>;
 813                                 pixelclk-active = <1>;
 814                         };
 815
 816                         ET0430 {
 817                                 clock-frequency = <9009000>;
 818                                 hactive = <480>;
 819                                 vactive = <272>;
 820                                 hback-porch = <2>;
 821                                 hsync-len = <41>;
 822                                 hfront-porch = <2>;
 823                                 vback-porch = <2>;
 824                                 vsync-len = <10>;
 825                                 vfront-porch = <2>;
 826                                 hsync-active = <0>;
 827                                 vsync-active = <0>;
 828                                 de-active = <1>;
 829                                 pixelclk-active = <0>;
 830                         };
 831
 832                         ET0500 {
 833                                 clock-frequency = <33264000>;
 834                                 hactive = <800>;
 835                                 vactive = <480>;
 836                                 hback-porch = <88>;
 837                                 hsync-len = <128>;
 838                                 hfront-porch = <40>;
 839                                 vback-porch = <33>;
 840                                 vsync-len = <2>;
 841                                 vfront-porch = <10>;
 842                                 hsync-active = <0>;
 843                                 vsync-active = <0>;
 844                                 de-active = <1>;
 845                                 pixelclk-active = <1>;
 846                         };
 847
 848                         ET0700 { /* same as ET0500 */
 849                                 clock-frequency = <33264000>;
 850                                 hactive = <800>;
 851                                 vactive = <480>;
 852                                 hback-porch = <88>;
 853                                 hsync-len = <128>;
 854                                 hfront-porch = <40>;
 855                                 vback-porch = <33>;
 856                                 vsync-len = <2>;
 857                                 vfront-porch = <10>;
 858                                 hsync-active = <0>;
 859                                 vsync-active = <0>;
 860                                 de-active = <1>;
 861                                 pixelclk-active = <1>;
 862                         };
 863
 864                         ETQ570 {
 865                                 clock-frequency = <6596040>;
 866                                 hactive = <320>;
 867                                 vactive = <240>;
 868                                 hback-porch = <38>;
 869                                 hsync-len = <30>;
 870                                 hfront-porch = <30>;
 871                                 vback-porch = <16>;
 872                                 vsync-len = <3>;
 873                                 vfront-porch = <4>;
 874                                 hsync-active = <0>;
 875                                 vsync-active = <0>;
 876                                 de-active = <1>;
 877                                 pixelclk-active = <1>;
 878                         };
 879                 };
 880         };
 881 };
 882
 883 &pwm5 {
 884         pinctrl-names = "default";
 885         pinctrl-0 = <&pinctrl_pwm5>;
 886         #pwm-cells = <3>;
 887         status = "okay";
 888 };
 889
 890 &sai2 {
 891         pinctrl-names = "default";
 892         pinctrl-0 = <&pinctrl_sai2>;
 893         status = "okay";
 894 };
 895
 896 &uart1 {
 897         pinctrl-names = "default";
 898         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 899         status = "okay";
 900 };
 901
 902 &uart2 {
 903         pinctrl-names = "default";
 904         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 905         status = "okay";
 906 };
 907
 908 &uart5 {
 909         pinctrl-names = "default";
 910         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 911         status = "okay";
 912 };
 913
 914 &usbotg2 {
 915         vbus-supply = <&reg_usbh1_vbus>;
 916         dr_mode = "host";
 917         disable-over-current;
 918         status = "okay";
 919 };
 920
 921 &usbotg1 {
 922         vbus-supply = <&reg_usbotg_vbus>;
 923         dr_mode = "peripheral";
 924         disable-over-current;
 925         status = "okay";
 926 };
 927
 928 &usdhc1 {
 929         pinctrl-names = "default";
 930         pinctrl-0 = <&pinctrl_usdhc1>;
 931         bus-width = <4>;
 932         no-1-8-v;
 933         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 934         fsl,wp-controller;
 935         status = "okay";
 936 };