arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &lcdif;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  57                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg_can_xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory {
  74                 reg = <0 0>; /* will be filled by U-Boot */
  75         };
  76
  77         clocks {
  78                 mclk: mclk {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <26000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcd_pwr>;
  89                 enable-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  90                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  91                 power-supply = <&reg_3v3>;
  92                 /*
  93                  * a poor man's way to create a 1:1 relationship between
  94                  * the PWM value and the actual duty cycle
  95                  */
  96                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  97                                      10 11 12 13 14 15 16 17 18 19
  98                                      20 21 22 23 24 25 26 27 28 29
  99                                      30 31 32 33 34 35 36 37 38 39
 100                                      40 41 42 43 44 45 46 47 48 49
 101                                      50 51 52 53 54 55 56 57 58 59
 102                                      60 61 62 63 64 65 66 67 68 69
 103                                      70 71 72 73 74 75 76 77 78 79
 104                                      80 81 82 83 84 85 86 87 88 89
 105                                      90 91 92 93 94 95 96 97 98 99
 106                                     100>;
 107                 default-brightness-level = <50>;
 108         };
 109
 110         i2c_gpio: i2c-gpio {
 111                 compatible = "i2c-gpio";
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 116                 gpios = <
 117                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 118                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 119                 >;
 120                 clock-frequency = <400000>;
 121                 status = "okay";
 122
 123                 ds1339: rtc@68 {
 124                         compatible = "dallas,ds1339";
 125                         reg = <0x68>;
 126                         status = "disabled";
 127                 };
 128         };
 129
 130         lcd-panel {
 131                 compatible = "edt,etm0700g0dh6";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_lcd_rst>;
 134                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 135                 power-supply = <&reg_3v3>;
 136                 backlight = <&backlight>;
 137                 bus-format-override = "rgb24";
 138
 139                 port {
 140                         panel_in: endpoint {
 141                                 remote-endpoint = <&display_out>;
 142                         };
 143                 };
 144         };
 145
 146         leds {
 147                 compatible = "gpio-leds";
 148
 149                 user_led: user {
 150                         label = "Heartbeat";
 151                         pinctrl-names = "default";
 152                         pinctrl-0 = <&pinctrl_led>;
 153                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 154                         linux,default-trigger = "heartbeat";
 155                 };
 156         };
 157
 158         reg_3v3_etn: regulator-3v3etn {
 159                 compatible = "regulator-fixed";
 160                 regulator-name = "3V3_ETN";
 161                 regulator-min-microvolt = <3300000>;
 162                 regulator-max-microvolt = <3300000>;
 163                 pinctrl-names = "default";
 164                 pinctrl-0 = <&pinctrl_etnphy_power>;
 165                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 166                 enable-active-high;
 167         };
 168
 169         reg_2v5: regulator-2v5 {
 170                 compatible = "regulator-fixed";
 171                 regulator-name = "2V5";
 172                 regulator-min-microvolt = <2500000>;
 173                 regulator-max-microvolt = <2500000>;
 174                 regulator-always-on;
 175         };
 176
 177         reg_3v3: regulator-3v3 {
 178                 compatible = "regulator-fixed";
 179                 regulator-name = "3V3";
 180                 regulator-min-microvolt = <3300000>;
 181                 regulator-max-microvolt = <3300000>;
 182                 regulator-always-on;
 183         };
 184
 185         reg_can_xcvr: regulator-canxcvr {
 186                 compatible = "regulator-fixed";
 187                 regulator-name = "CAN XCVR";
 188                 regulator-min-microvolt = <3300000>;
 189                 regulator-max-microvolt = <3300000>;
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 192                 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
 193         };
 194
 195         reg_usbh1_vbus: regulator-usbh1vbus {
 196                 compatible = "regulator-fixed";
 197                 regulator-name = "usbh1_vbus";
 198                 regulator-min-microvolt = <5000000>;
 199                 regulator-max-microvolt = <5000000>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 202                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 203                 enable-active-high;
 204         };
 205
 206         reg_usbotg_vbus: regulator-usbotgvbus {
 207                 compatible = "regulator-fixed";
 208                 regulator-name = "usbotg_vbus";
 209                 regulator-min-microvolt = <5000000>;
 210                 regulator-max-microvolt = <5000000>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 213                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 214                 enable-active-high;
 215         };
 216
 217         spi_gpio: spi-gpio {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 compatible = "spi-gpio";
 221                 pinctrl-names = "default";
 222                 pinctrl-0 = <&pinctrl_spi_gpio>;
 223                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 224                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 225                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 226                 num-chipselects = <2>;
 227                 cs-gpios = <
 228                         &gpio1 29 GPIO_ACTIVE_HIGH
 229                         &gpio1 10 GPIO_ACTIVE_HIGH
 230                 >;
 231                 status = "disabled";
 232
 233                 spi@0 {
 234                         compatible = "spidev";
 235                         reg = <0>;
 236                         spi-max-frequency = <660000>;
 237                 };
 238
 239                 spi@1 {
 240                         compatible = "spidev";
 241                         reg = <1>;
 242                         spi-max-frequency = <660000>;
 243                 };
 244         };
 245
 246         sound {
 247                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 248                              "simple-audio-card";
 249                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 250                 simple-audio-card,format = "i2s";
 251                 simple-audio-card,bitclock-master = <&codec_dai>;
 252                 simple-audio-card,frame-master = <&codec_dai>;
 253                 simple-audio-card,widgets =
 254                         "Microphone", "Mic Jack",
 255                         "Line", "Line In",
 256                         "Line", "Line Out",
 257                         "Headphone", "Headphone Jack";
 258                 simple-audio-card,routing =
 259                         "MIC_IN", "Mic Jack",
 260                         "Mic Jack", "Mic Bias",
 261                         "Headphone Jack", "HP_OUT";
 262
 263                 cpu_dai: simple-audio-card,cpu {
 264                         sound-dai = <&sai2>;
 265                 };
 266
 267                 codec_dai: simple-audio-card,codec {
 268                         sound-dai = <&sgtl5000>;
 269                 };
 270         };
 271 };
 272
 273 &can1 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_flexcan1>;
 276         xceiver-supply = <&reg_can_xcvr>;
 277         status = "okay";
 278 };
 279
 280 &can2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_flexcan2>;
 283         xceiver-supply = <&reg_can_xcvr>;
 284         status = "okay";
 285 };
 286
 287 &ecspi2 {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_ecspi2>;
 290         cs-gpios = <
 291                 &gpio1 29 GPIO_ACTIVE_HIGH
 292                 &gpio1 10 GPIO_ACTIVE_HIGH
 293         >;
 294         status = "disabled";
 295
 296         spidev0: spi@0 {
 297                 compatible = "spidev";
 298                 reg = <0>;
 299                 spi-max-frequency = <60000000>;
 300         };
 301
 302         spidev1: spi@1 {
 303                 compatible = "spidev";
 304                 reg = <1>;
 305                 spi-max-frequency = <60000000>;
 306         };
 307 };
 308
 309 &fec1 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 312         phy-mode = "rmii";
 313         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 314         phy-reset-post-delay = <10>;
 315         phy-supply = <&reg_3v3_etn>;
 316         phy-handle = <&etnphy0>;
 317         status = "okay";
 318
 319         mdio {
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322
 323                 etnphy0: ethernet-phy@0 {
 324                         compatible = "ethernet-phy-ieee802.3-c22";
 325                         reg = <0>;
 326                         pinctrl-names = "default";
 327                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 328                         interrupt-parent = <&gpio5>;
 329                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 330                         status = "okay";
 331                 };
 332
 333                 etnphy1: ethernet-phy@2 {
 334                         compatible = "ethernet-phy-ieee802.3-c22";
 335                         reg = <2>;
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 338                         interrupt-parent = <&gpio4>;
 339                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 340                         status = "okay";
 341                 };
 342         };
 343 };
 344
 345 &fec2 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 348         phy-mode = "rmii";
 349         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 350         phy-supply = <&reg_3v3_etn>;
 351         phy-handle = <&etnphy1>;
 352         status = "disabled";
 353 };
 354
 355 &gpmi {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_gpmi_nand>;
 358         nand-on-flash-bbt;
 359         fsl,no-blockmark-swap;
 360         status = "okay";
 361 };
 362
 363 &i2c2 {
 364         pinctrl-names = "default", "gpio";
 365         pinctrl-0 = <&pinctrl_i2c2>;
 366         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 367         scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 368         sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 369         clock-frequency = <400000>;
 370         status = "okay";
 371
 372         sgtl5000: codec@0a {
 373                 compatible = "fsl,sgtl5000";
 374                 reg = <0x0a>;
 375                 #sound-dai-cells = <0>;
 376                 VDDA-supply = <&reg_2v5>;
 377                 VDDIO-supply = <&reg_3v3>;
 378                 clocks = <&mclk>;
 379         };
 380
 381         polytouch: polytouch@38 {
 382                 compatible = "edt,edt-ft5x06";
 383                 reg = <0x38>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 386                 interrupt-parent = <&gpio5>;
 387                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 388                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 389                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 390                 wakeup-source;
 391         };
 392
 393         touchscreen: touchscreen@48 {
 394                 compatible = "ti,tsc2007";
 395                 reg = <0x48>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&pinctrl_tsc2007>;
 398                 interrupt-parent = <&gpio3>;
 399                 interrupts = <26 IRQ_TYPE_NONE>;
 400                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 401                 ti,x-plate-ohms = <660>;
 402                 wakeup-source;
 403         };
 404 };
 405
 406 &kpp {
 407         pinctrl-names = "default";
 408         pinctrl-0 = <&pinctrl_kpp>;
 409         /* sample keymap */
 410         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 411         linux,keymap = <
 412                 MATRIX_KEY(4, 4, KEY_POWER)
 413                 MATRIX_KEY(4, 5, KEY_KP0)
 414                 MATRIX_KEY(4, 6, KEY_KP1)
 415                 MATRIX_KEY(4, 7, KEY_KP2)
 416                 MATRIX_KEY(5, 4, KEY_KP3)
 417                 MATRIX_KEY(5, 5, KEY_KP4)
 418                 MATRIX_KEY(5, 6, KEY_KP5)
 419                 MATRIX_KEY(5, 7, KEY_KP6)
 420                 MATRIX_KEY(6, 4, KEY_KP7)
 421                 MATRIX_KEY(6, 5, KEY_KP8)
 422                 MATRIX_KEY(6, 6, KEY_KP9)
 423         >;
 424         status = "okay";
 425 };
 426
 427 &lcdif {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_disp0_1>;
 430         status = "okay";
 431
 432         port {
 433                 display_out: endpoint {
 434                         remote-endpoint = <&panel_in>;
 435                 };
 436         };
 437
 438         display-timings {
 439                 VGA {
 440                         clock-frequency = <25200000>;
 441                         hactive = <640>;
 442                         vactive = <480>;
 443                         hback-porch = <48>;
 444                         hsync-len = <96>;
 445                         hfront-porch = <16>;
 446                         vback-porch = <31>;
 447                         vsync-len = <2>;
 448                         vfront-porch = <12>;
 449                         hsync-active = <0>;
 450                         vsync-active = <0>;
 451                         de-active = <1>;
 452                         pixelclk-active = <1>;
 453                 };
 454
 455                 ETV570 {
 456                         u-boot,panel-name = "edt,et057090dhu";
 457                         clock-frequency = <25200000>;
 458                         hactive = <640>;
 459                         vactive = <480>;
 460                         hback-porch = <114>;
 461                         hsync-len = <30>;
 462                         hfront-porch = <16>;
 463                         vback-porch = <32>;
 464                         vsync-len = <3>;
 465                         vfront-porch = <10>;
 466                         hsync-active = <0>;
 467                         vsync-active = <0>;
 468                         de-active = <1>;
 469                         pixelclk-active = <1>;
 470                 };
 471
 472                 ET0350 {
 473                         u-boot,panel-name = "edt,et0350g0dh6";
 474                         clock-frequency = <6413760>;
 475                         hactive = <320>;
 476                         vactive = <240>;
 477                         hback-porch = <34>;
 478                         hsync-len = <34>;
 479                         hfront-porch = <20>;
 480                         vback-porch = <15>;
 481                         vsync-len = <3>;
 482                         vfront-porch = <4>;
 483                         hsync-active = <0>;
 484                         vsync-active = <0>;
 485                         de-active = <1>;
 486                         pixelclk-active = <1>;
 487                 };
 488
 489                 ET0430 {
 490                         u-boot,panel-name = "edt,et0430g0dh6";
 491                         clock-frequency = <9009000>;
 492                         hactive = <480>;
 493                         vactive = <272>;
 494                         hback-porch = <2>;
 495                         hsync-len = <41>;
 496                         hfront-porch = <2>;
 497                         vback-porch = <2>;
 498                         vsync-len = <10>;
 499                         vfront-porch = <2>;
 500                         hsync-active = <0>;
 501                         vsync-active = <0>;
 502                         de-active = <1>;
 503                         pixelclk-active = <0>;
 504                 };
 505
 506                 ET0500 {
 507                         clock-frequency = <33264000>;
 508                         hactive = <800>;
 509                         vactive = <480>;
 510                         hback-porch = <88>;
 511                         hsync-len = <128>;
 512                         hfront-porch = <40>;
 513                         vback-porch = <33>;
 514                         vsync-len = <2>;
 515                         vfront-porch = <10>;
 516                         hsync-active = <0>;
 517                         vsync-active = <0>;
 518                         de-active = <1>;
 519                         pixelclk-active = <1>;
 520                 };
 521
 522                 ET0700 { /* same timing as ET0500 */
 523                         u-boot,panel-name = "edt,etm0700g0dh6";
 524                         clock-frequency = <33264000>;
 525                         hactive = <800>;
 526                         vactive = <480>;
 527                         hback-porch = <88>;
 528                         hsync-len = <128>;
 529                         hfront-porch = <40>;
 530                         vback-porch = <33>;
 531                         vsync-len = <2>;
 532                         vfront-porch = <10>;
 533                         hsync-active = <0>;
 534                         vsync-active = <0>;
 535                         de-active = <1>;
 536                         pixelclk-active = <1>;
 537                 };
 538
 539                 ETQ570 {
 540                         clock-frequency = <6596040>;
 541                         hactive = <320>;
 542                         vactive = <240>;
 543                         hback-porch = <38>;
 544                         hsync-len = <30>;
 545                         hfront-porch = <30>;
 546                         vback-porch = <16>;
 547                         vsync-len = <3>;
 548                         vfront-porch = <4>;
 549                         hsync-active = <0>;
 550                         vsync-active = <0>;
 551                         de-active = <1>;
 552                         pixelclk-active = <1>;
 553                 };
 554         };
 555 };
 556
 557 &pwm5 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&pinctrl_pwm5>;
 560         #pwm-cells = <3>;
 561         status = "okay";
 562 };
 563
 564 &sai2 {
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&pinctrl_sai2>;
 567         status = "okay";
 568 };
 569
 570 &uart1 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 573         uart-has-rtscts;
 574         status = "okay";
 575 };
 576
 577 &uart2 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 580         uart-has-rtscts;
 581         status = "okay";
 582 };
 583
 584 &uart5 {
 585         pinctrl-names = "default";
 586         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 587         uart-has-rtscts;
 588         status = "okay";
 589 };
 590
 591 &usbotg1 {
 592         vbus-supply = <&reg_usbotg_vbus>;
 593         dr_mode = "peripheral";
 594         disable-over-current;
 595         status = "okay";
 596 };
 597
 598 &usbotg2 {
 599         vbus-supply = <&reg_usbh1_vbus>;
 600         dr_mode = "host";
 601         disable-over-current;
 602         status = "okay";
 603 };
 604
 605 &usdhc1 {
 606         pinctrl-names = "default";
 607         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 608         bus-width = <4>;
 609         no-1-8-v;
 610         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 611         fsl,wp-controller;
 612         status = "okay";
 613 };
 614
 615 &iomuxc {
 616         pinctrl-names = "default";
 617         pinctrl-0 = <&pinctrl_hog>;
 618
 619         pinctrl_hog: hoggrp {
 620         };
 621
 622         pinctrl_led: ledgrp {
 623                 fsl,pins = <
 624                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 625                 >;
 626         };
 627
 628         pinctrl_disp0_1: disp0grp-1 {
 629                 fsl,pins = <
 630                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 631                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 632                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 633                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 634                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 635                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 636                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 637                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 638                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 639                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 640                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 641                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 642                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 643                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 644                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 645                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 646                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 647                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 648                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 649                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 650                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 651                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 652                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 653                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 654                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 655                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 656                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 657                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 658                 >;
 659         };
 660
 661         pinctrl_disp0_2: disp0grp-2 {
 662                 fsl,pins = <
 663                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 664                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 665                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 666                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 667                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 668                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 669                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 670                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 671                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 672                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 673                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 674                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 675                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 676                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 677                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 678                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 679                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 680                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 681                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 682                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 683                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 684                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 685                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 686                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 687                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 688                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 689                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 690                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 691                 >;
 692         };
 693
 694         pinctrl_ecspi2: ecspi2grp {
 695                 fsl,pins = <
 696                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 697                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 698                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 699                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 700                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 701                 >;
 702         };
 703
 704         pinctrl_edt_ft5x06: edt-ft5x06grp {
 705                 fsl,pins = <
 706                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 707                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 708                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 709                 >;
 710         };
 711
 712         pinctrl_enet1: enet1grp {
 713                 fsl,pins = <
 714                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 715                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 716                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 717                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 718                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 719                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 720                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 721                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000018
 722                 >;
 723         };
 724
 725         pinctrl_enet2: enet2grp {
 726                 fsl,pins = <
 727                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 728                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 729                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 730                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 731                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 732                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 733                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 734                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000018
 735                 >;
 736         };
 737
 738         pinctrl_enet1_mdio: enet1-mdiogrp {
 739                 fsl,pins = <
 740                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 741                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 742                 >;
 743         };
 744
 745         pinctrl_etnphy_power: etnphy-pwrgrp {
 746                 fsl,pins = <
 747                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 748                 >;
 749         };
 750
 751         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 752                 fsl,pins = <
 753                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 754                 >;
 755         };
 756
 757         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 758                 fsl,pins = <
 759                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 760                 >;
 761         };
 762
 763         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 764                 fsl,pins = <
 765                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 766                 >;
 767         };
 768
 769         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 770                 fsl,pins = <
 771                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 772                 >;
 773         };
 774
 775         pinctrl_flexcan1: flexcan1grp {
 776                 fsl,pins = <
 777                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 778                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 779                 >;
 780         };
 781
 782         pinctrl_flexcan2: flexcan2grp {
 783                 fsl,pins = <
 784                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 785                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 786                 >;
 787         };
 788
 789         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 790                 fsl,pins = <
 791                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 792                 >;
 793         };
 794
 795         pinctrl_gpmi_nand: gpminandgrp {
 796                 fsl,pins = <
 797                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 798                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 799                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 800                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 801                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 802                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 803                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 804                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 805                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 806                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 807                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 808                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 809                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 810                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 811                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 812                 >;
 813         };
 814
 815         pinctrl_i2c_gpio: i2c-gpiogrp {
 816                 fsl,pins = <
 817                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 818                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 819                 >;
 820         };
 821
 822         pinctrl_i2c2: i2c2grp {
 823                 fsl,pins = <
 824                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 825                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 826                 >;
 827         };
 828
 829         pinctrl_i2c2_gpio: i2c2-gpiogrp {
 830                 fsl,pins = <
 831                         MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0x4001b0b9
 832                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0x4001b0b9
 833                 >;
 834         };
 835
 836         pinctrl_kpp: kppgrp {
 837                 fsl,pins = <
 838                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 839                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 840                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 841                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 842                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 843                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 844                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 845                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 846                 >;
 847         };
 848
 849         pinctrl_lcd_pwr: lcd-pwrgrp {
 850                 fsl,pins = <
 851                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 852                 >;
 853         };
 854
 855         pinctrl_lcd_rst: lcd-rstgrp {
 856                 fsl,pins = <
 857                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 858                 >;
 859         };
 860
 861         pinctrl_pwm5: pwm5grp {
 862                 fsl,pins = <
 863                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 864                 >;
 865         };
 866
 867         pinctrl_sai2: sai2grp {
 868                 fsl,pins = <
 869                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 870                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 871                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 872                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 873                 >;
 874         };
 875
 876         pinctrl_spi_gpio: spi-gpiogrp {
 877                 fsl,pins = <
 878                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 879                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 880                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 881                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 882                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 883                 >;
 884         };
 885
 886         pinctrl_tsc2007: tsc2007grp {
 887                 fsl,pins = <
 888                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 889                 >;
 890         };
 891
 892         pinctrl_uart1: uart1grp {
 893                 fsl,pins = <
 894                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 895                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 896                 >;
 897         };
 898
 899         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 900                 fsl,pins = <
 901                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 902                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 903                 >;
 904         };
 905
 906         pinctrl_uart2: uart2grp {
 907                 fsl,pins = <
 908                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 909                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 910                 >;
 911         };
 912
 913         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 914                 fsl,pins = <
 915                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 916                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 917                 >;
 918         };
 919
 920         pinctrl_uart5: uart5grp {
 921                 fsl,pins = <
 922                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 923                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 924                 >;
 925         };
 926
 927         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 928                 fsl,pins = <
 929                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 930                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 931                 >;
 932         };
 933
 934         pinctrl_usbh1_oc: usbh1-ocgrp {
 935                 fsl,pins = <
 936                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 937                 >;
 938         };
 939
 940         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 941                 fsl,pins = <
 942                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 943                 >;
 944         };
 945
 946         pinctrl_usbotg_oc: usbotg-ocgrp {
 947                 fsl,pins = <
 948                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 949                 >;
 950         };
 951
 952         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 953                 fsl,pins = <
 954                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 955                 >;
 956         };
 957
 958         pinctrl_usdhc1: usdhc1grp {
 959                 fsl,pins = <
 960                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 961                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 962                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 963                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 964                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 965                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 966                 >;
 967         };
 968
 969         pinctrl_usdhc1_cd: usdhc1cdgrp {
 970                 fsl,pins = <
 971                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 972                 >;
 973         };
 974
 975         pinctrl_usdhc2: usdhc2grp {
 976                 fsl,pins = <
 977                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 978                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 979                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 980                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 981                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 982                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 983                         /* eMMC RESET */
 984                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 985                 >;
 986         };
 987 };