arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &display;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  57                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg_can_xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory {
  74                 reg = <0 0>; /* will be filled by U-Boot */
  75         };
  76
  77         clocks {
  78                 mclk: mclk {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <26000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcd_rst>;
  89                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
  90                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  91                 power-supply = <&reg_lcd_pwr>;
  92                 /*
  93                  * a poor man's way to create a 1:1 relationship between
  94                  * the PWM value and the actual duty cycle
  95                  */
  96                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  97                                      10 11 12 13 14 15 16 17 18 19
  98                                      20 21 22 23 24 25 26 27 28 29
  99                                      30 31 32 33 34 35 36 37 38 39
 100                                      40 41 42 43 44 45 46 47 48 49
 101                                      50 51 52 53 54 55 56 57 58 59
 102                                      60 61 62 63 64 65 66 67 68 69
 103                                      70 71 72 73 74 75 76 77 78 79
 104                                      80 81 82 83 84 85 86 87 88 89
 105                                      90 91 92 93 94 95 96 97 98 99
 106                                     100>;
 107                 default-brightness-level = <50>;
 108         };
 109
 110         i2c_gpio: i2c-gpio {
 111                 compatible = "i2c-gpio";
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 116                 gpios = <
 117                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 118                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 119                 >;
 120                 clock-frequency = <400000>;
 121                 status = "okay";
 122
 123                 ds1339: rtc@68 {
 124                         compatible = "dallas,ds1339";
 125                         reg = <0x68>;
 126                         status = "disabled";
 127                 };
 128         };
 129
 130         leds {
 131                 compatible = "gpio-leds";
 132
 133                 user_led: user {
 134                         label = "Heartbeat";
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_led>;
 137                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 138                         linux,default-trigger = "heartbeat";
 139                 };
 140         };
 141
 142         reg_3v3_etn: regulator-3v3etn {
 143                 compatible = "regulator-fixed";
 144                 regulator-name = "3V3_ETN";
 145                 regulator-min-microvolt = <3300000>;
 146                 regulator-max-microvolt = <3300000>;
 147                 pinctrl-names = "default";
 148                 pinctrl-0 = <&pinctrl_etnphy_power>;
 149                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 150                 enable-active-high;
 151         };
 152
 153         reg_2v5: regulator-2v5 {
 154                 compatible = "regulator-fixed";
 155                 regulator-name = "2V5";
 156                 regulator-min-microvolt = <2500000>;
 157                 regulator-max-microvolt = <2500000>;
 158                 regulator-always-on;
 159         };
 160
 161         reg_3v3: regulator-3v3 {
 162                 compatible = "regulator-fixed";
 163                 regulator-name = "3V3";
 164                 regulator-min-microvolt = <3300000>;
 165                 regulator-max-microvolt = <3300000>;
 166                 regulator-always-on;
 167         };
 168
 169         reg_can_xcvr: regulator-canxcvr {
 170                 compatible = "regulator-fixed";
 171                 regulator-name = "CAN XCVR";
 172                 regulator-min-microvolt = <3300000>;
 173                 regulator-max-microvolt = <3300000>;
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 176                 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
 177         };
 178
 179         reg_lcd_pwr: regulator-lcdpwr {
 180                 compatible = "regulator-fixed";
 181                 regulator-name = "LCD POWER";
 182                 regulator-min-microvolt = <3300000>;
 183                 regulator-max-microvolt = <3300000>;
 184                 pinctrl-names = "default";
 185                 pinctrl-0 = <&pinctrl_lcd_pwr>;
 186                 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 187                 enable-active-high;
 188                 regulator-boot-on;
 189                 regulator-always-on;
 190         };
 191
 192         reg_usbh1_vbus: regulator-usbh1vbus {
 193                 compatible = "regulator-fixed";
 194                 regulator-name = "usbh1_vbus";
 195                 regulator-min-microvolt = <5000000>;
 196                 regulator-max-microvolt = <5000000>;
 197                 pinctrl-names = "default";
 198                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 199                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 200                 enable-active-high;
 201         };
 202
 203         reg_usbotg_vbus: regulator-usbotgvbus {
 204                 compatible = "regulator-fixed";
 205                 regulator-name = "usbotg_vbus";
 206                 regulator-min-microvolt = <5000000>;
 207                 regulator-max-microvolt = <5000000>;
 208                 pinctrl-names = "default";
 209                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 210                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 211                 enable-active-high;
 212         };
 213
 214         spi_gpio: spi-gpio {
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 compatible = "spi-gpio";
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&pinctrl_spi_gpio>;
 220                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 221                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 222                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 223                 num-chipselects = <2>;
 224                 cs-gpios = <
 225                         &gpio1 29 GPIO_ACTIVE_HIGH
 226                         &gpio1 10 GPIO_ACTIVE_HIGH
 227                 >;
 228                 status = "disabled";
 229
 230                 spi@0 {
 231                         compatible = "spidev";
 232                         reg = <0>;
 233                         spi-max-frequency = <660000>;
 234                 };
 235
 236                 spi@1 {
 237                         compatible = "spidev";
 238                         reg = <1>;
 239                         spi-max-frequency = <660000>;
 240                 };
 241         };
 242
 243         sound {
 244                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 245                              "simple-audio-card";
 246                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 247                 simple-audio-card,format = "i2s";
 248                 simple-audio-card,bitclock-master = <&codec_dai>;
 249                 simple-audio-card,frame-master = <&codec_dai>;
 250                 simple-audio-card,widgets =
 251                         "Microphone", "Mic Jack",
 252                         "Line", "Line In",
 253                         "Line", "Line Out",
 254                         "Headphone", "Headphone Jack";
 255                 simple-audio-card,routing =
 256                         "MIC_IN", "Mic Jack",
 257                         "Mic Jack", "Mic Bias",
 258                         "Headphone Jack", "HP_OUT";
 259
 260                 cpu_dai: simple-audio-card,cpu {
 261                         sound-dai = <&sai2>;
 262                 };
 263
 264                 codec_dai: simple-audio-card,codec {
 265                         sound-dai = <&sgtl5000>;
 266                 };
 267         };
 268 };
 269
 270 &can1 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_flexcan1>;
 273         xceiver-supply = <&reg_can_xcvr>;
 274         status = "okay";
 275 };
 276
 277 &can2 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_flexcan2>;
 280         xceiver-supply = <&reg_can_xcvr>;
 281         status = "okay";
 282 };
 283
 284 &ecspi2 {
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_ecspi2>;
 287         cs-gpios = <
 288                 &gpio1 29 GPIO_ACTIVE_HIGH
 289                 &gpio1 10 GPIO_ACTIVE_HIGH
 290         >;
 291         status = "disabled";
 292
 293         spidev0: spi@0 {
 294                 compatible = "spidev";
 295                 reg = <0>;
 296                 spi-max-frequency = <60000000>;
 297         };
 298
 299         spidev1: spi@1 {
 300                 compatible = "spidev";
 301                 reg = <1>;
 302                 spi-max-frequency = <60000000>;
 303         };
 304 };
 305
 306 &fec1 {
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 309         phy-mode = "rmii";
 310         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 311         phy-reset-post-delay = <10>;
 312         phy-supply = <&reg_3v3_etn>;
 313         phy-handle = <&etnphy0>;
 314         status = "okay";
 315
 316         mdio {
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319
 320                 etnphy0: ethernet-phy@0 {
 321                         compatible = "ethernet-phy-ieee802.3-c22";
 322                         reg = <0>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 325                         interrupt-parent = <&gpio5>;
 326                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 327                         status = "okay";
 328                 };
 329
 330                 etnphy1: ethernet-phy@2 {
 331                         compatible = "ethernet-phy-ieee802.3-c22";
 332                         reg = <2>;
 333                         pinctrl-names = "default";
 334                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 335                         interrupt-parent = <&gpio4>;
 336                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 337                         status = "okay";
 338                 };
 339         };
 340 };
 341
 342 &fec2 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 345         phy-mode = "rmii";
 346         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 347         phy-supply = <&reg_3v3_etn>;
 348         phy-handle = <&etnphy1>;
 349         status = "disabled";
 350 };
 351
 352 &gpmi {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_gpmi_nand>;
 355         nand-on-flash-bbt;
 356         fsl,no-blockmark-swap;
 357         status = "okay";
 358 };
 359
 360 &i2c2 {
 361         pinctrl-names = "default", "gpio";
 362         pinctrl-0 = <&pinctrl_i2c2>;
 363         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 364         scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 365         sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 366         clock-frequency = <400000>;
 367         status = "okay";
 368
 369         sgtl5000: codec@0a {
 370                 compatible = "fsl,sgtl5000";
 371                 reg = <0x0a>;
 372                 #sound-dai-cells = <0>;
 373                 VDDA-supply = <&reg_2v5>;
 374                 VDDIO-supply = <&reg_3v3>;
 375                 clocks = <&mclk>;
 376         };
 377
 378         polytouch: polytouch@38 {
 379                 compatible = "edt,edt-ft5x06";
 380                 reg = <0x38>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 383                 interrupt-parent = <&gpio5>;
 384                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 385                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 386                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 387                 wakeup-source;
 388         };
 389
 390         touchscreen: touchscreen@48 {
 391                 compatible = "ti,tsc2007";
 392                 reg = <0x48>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&pinctrl_tsc2007>;
 395                 interrupt-parent = <&gpio3>;
 396                 interrupts = <26 IRQ_TYPE_NONE>;
 397                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 398                 ti,x-plate-ohms = <660>;
 399                 wakeup-source;
 400         };
 401 };
 402
 403 &kpp {
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_kpp>;
 406         /* sample keymap */
 407         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 408         linux,keymap = <
 409                 MATRIX_KEY(4, 4, KEY_POWER)
 410                 MATRIX_KEY(4, 5, KEY_KP0)
 411                 MATRIX_KEY(4, 6, KEY_KP1)
 412                 MATRIX_KEY(4, 7, KEY_KP2)
 413                 MATRIX_KEY(5, 4, KEY_KP3)
 414                 MATRIX_KEY(5, 5, KEY_KP4)
 415                 MATRIX_KEY(5, 6, KEY_KP5)
 416                 MATRIX_KEY(5, 7, KEY_KP6)
 417                 MATRIX_KEY(6, 4, KEY_KP7)
 418                 MATRIX_KEY(6, 5, KEY_KP8)
 419                 MATRIX_KEY(6, 6, KEY_KP9)
 420         >;
 421         status = "okay";
 422 };
 423
 424 &lcdif {
 425         pinctrl-names = "default";
 426         pinctrl-0 = <&pinctrl_disp0_1>;
 427         lcd-supply = <&reg_lcd_pwr>;
 428         display = <&display>;
 429         status = "okay";
 430
 431         display: display@di0 {
 432                 bits-per-pixel = <32>;
 433                 bus-width = <24>;
 434                 status = "okay";
 435
 436                 display-timings {
 437                         VGA {
 438                                 clock-frequency = <25200000>;
 439                                 hactive = <640>;
 440                                 vactive = <480>;
 441                                 hback-porch = <48>;
 442                                 hsync-len = <96>;
 443                                 hfront-porch = <16>;
 444                                 vback-porch = <31>;
 445                                 vsync-len = <2>;
 446                                 vfront-porch = <12>;
 447                                 hsync-active = <0>;
 448                                 vsync-active = <0>;
 449                                 de-active = <1>;
 450                                 pixelclk-active = <1>;
 451                         };
 452
 453                         ETV570 {
 454                                 clock-frequency = <25200000>;
 455                                 hactive = <640>;
 456                                 vactive = <480>;
 457                                 hback-porch = <114>;
 458                                 hsync-len = <30>;
 459                                 hfront-porch = <16>;
 460                                 vback-porch = <32>;
 461                                 vsync-len = <3>;
 462                                 vfront-porch = <10>;
 463                                 hsync-active = <0>;
 464                                 vsync-active = <0>;
 465                                 de-active = <1>;
 466                                 pixelclk-active = <1>;
 467                         };
 468
 469                         ET0350 {
 470                                 clock-frequency = <6413760>;
 471                                 hactive = <320>;
 472                                 vactive = <240>;
 473                                 hback-porch = <34>;
 474                                 hsync-len = <34>;
 475                                 hfront-porch = <20>;
 476                                 vback-porch = <15>;
 477                                 vsync-len = <3>;
 478                                 vfront-porch = <4>;
 479                                 hsync-active = <0>;
 480                                 vsync-active = <0>;
 481                                 de-active = <1>;
 482                                 pixelclk-active = <1>;
 483                         };
 484
 485                         ET0430 {
 486                                 clock-frequency = <9009000>;
 487                                 hactive = <480>;
 488                                 vactive = <272>;
 489                                 hback-porch = <2>;
 490                                 hsync-len = <41>;
 491                                 hfront-porch = <2>;
 492                                 vback-porch = <2>;
 493                                 vsync-len = <10>;
 494                                 vfront-porch = <2>;
 495                                 hsync-active = <0>;
 496                                 vsync-active = <0>;
 497                                 de-active = <1>;
 498                                 pixelclk-active = <0>;
 499                         };
 500
 501                         ET0500 {
 502                                 clock-frequency = <33264000>;
 503                                 hactive = <800>;
 504                                 vactive = <480>;
 505                                 hback-porch = <88>;
 506                                 hsync-len = <128>;
 507                                 hfront-porch = <40>;
 508                                 vback-porch = <33>;
 509                                 vsync-len = <2>;
 510                                 vfront-porch = <10>;
 511                                 hsync-active = <0>;
 512                                 vsync-active = <0>;
 513                                 de-active = <1>;
 514                                 pixelclk-active = <1>;
 515                         };
 516
 517                         ET0700 { /* same as ET0500 */
 518                                 clock-frequency = <33264000>;
 519                                 hactive = <800>;
 520                                 vactive = <480>;
 521                                 hback-porch = <88>;
 522                                 hsync-len = <128>;
 523                                 hfront-porch = <40>;
 524                                 vback-porch = <33>;
 525                                 vsync-len = <2>;
 526                                 vfront-porch = <10>;
 527                                 hsync-active = <0>;
 528                                 vsync-active = <0>;
 529                                 de-active = <1>;
 530                                 pixelclk-active = <1>;
 531                         };
 532
 533                         ETQ570 {
 534                                 clock-frequency = <6596040>;
 535                                 hactive = <320>;
 536                                 vactive = <240>;
 537                                 hback-porch = <38>;
 538                                 hsync-len = <30>;
 539                                 hfront-porch = <30>;
 540                                 vback-porch = <16>;
 541                                 vsync-len = <3>;
 542                                 vfront-porch = <4>;
 543                                 hsync-active = <0>;
 544                                 vsync-active = <0>;
 545                                 de-active = <1>;
 546                                 pixelclk-active = <1>;
 547                         };
 548                 };
 549         };
 550 };
 551
 552 &pwm5 {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pinctrl_pwm5>;
 555         #pwm-cells = <3>;
 556         status = "okay";
 557 };
 558
 559 &sai2 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&pinctrl_sai2>;
 562         status = "okay";
 563 };
 564
 565 &uart1 {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 568         uart-has-rtscts;
 569         status = "okay";
 570 };
 571
 572 &uart2 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 575         uart-has-rtscts;
 576         status = "okay";
 577 };
 578
 579 &uart5 {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 582         uart-has-rtscts;
 583         status = "okay";
 584 };
 585
 586 &usbotg1 {
 587         vbus-supply = <&reg_usbotg_vbus>;
 588         dr_mode = "peripheral";
 589         disable-over-current;
 590         status = "okay";
 591 };
 592
 593 &usbotg2 {
 594         vbus-supply = <&reg_usbh1_vbus>;
 595         dr_mode = "host";
 596         disable-over-current;
 597         status = "okay";
 598 };
 599
 600 &usdhc1 {
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 603         bus-width = <4>;
 604         no-1-8-v;
 605         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 606         fsl,wp-controller;
 607         status = "okay";
 608 };
 609
 610 &iomuxc {
 611         pinctrl-names = "default";
 612         pinctrl-0 = <&pinctrl_hog>;
 613
 614         pinctrl_hog: hoggrp {
 615         };
 616
 617         pinctrl_led: ledgrp {
 618                 fsl,pins = <
 619                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 620                 >;
 621         };
 622
 623         pinctrl_disp0_1: disp0grp-1 {
 624                 fsl,pins = <
 625                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 626                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 627                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 628                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 629                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 630                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 631                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 632                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 633                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 634                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 635                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 636                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 637                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 638                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 639                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 640                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 641                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 642                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 643                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 644                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 645                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 646                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 647                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 648                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 649                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 650                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 651                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 652                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 653                 >;
 654         };
 655
 656         pinctrl_disp0_2: disp0grp-2 {
 657                 fsl,pins = <
 658                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 659                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 660                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 661                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 662                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 663                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 664                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 665                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 666                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 667                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 668                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 669                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 670                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 671                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 672                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 673                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 674                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 675                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 676                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 677                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 678                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 679                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 680                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 681                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 682                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 683                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 684                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 685                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 686                 >;
 687         };
 688
 689         pinctrl_ecspi2: ecspi2grp {
 690                 fsl,pins = <
 691                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 692                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 693                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 694                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 695                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 696                 >;
 697         };
 698
 699         pinctrl_edt_ft5x06: edt-ft5x06grp {
 700                 fsl,pins = <
 701                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 702                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 703                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 704                 >;
 705         };
 706
 707         pinctrl_enet1: enet1grp {
 708                 fsl,pins = <
 709                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 710                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 711                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 712                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 713                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 714                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 715                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 716                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x400000b1
 717                 >;
 718         };
 719
 720         pinctrl_enet2: enet2grp {
 721                 fsl,pins = <
 722                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 723                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 724                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 725                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 726                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 727                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 728                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 729                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x400000b1
 730                 >;
 731         };
 732
 733         pinctrl_enet1_mdio: enet1-mdiogrp {
 734                 fsl,pins = <
 735                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 736                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 737                 >;
 738         };
 739
 740         pinctrl_etnphy_power: etnphy-pwrgrp {
 741                 fsl,pins = <
 742                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 743                 >;
 744         };
 745
 746         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 747                 fsl,pins = <
 748                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 749                 >;
 750         };
 751
 752         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 753                 fsl,pins = <
 754                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 755                 >;
 756         };
 757
 758         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 759                 fsl,pins = <
 760                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 761                 >;
 762         };
 763
 764         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 765                 fsl,pins = <
 766                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 767                 >;
 768         };
 769
 770         pinctrl_flexcan1: flexcan1grp {
 771                 fsl,pins = <
 772                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 773                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 774                 >;
 775         };
 776
 777         pinctrl_flexcan2: flexcan2grp {
 778                 fsl,pins = <
 779                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 780                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 781                 >;
 782         };
 783
 784         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 785                 fsl,pins = <
 786                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 787                 >;
 788         };
 789
 790         pinctrl_gpmi_nand: gpminandgrp {
 791                 fsl,pins = <
 792                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 793                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 794                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 795                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 796                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 797                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 798                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 799                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 800                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 801                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 802                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 803                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 804                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 805                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 806                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 807                 >;
 808         };
 809
 810         pinctrl_i2c_gpio: i2c-gpiogrp {
 811                 fsl,pins = <
 812                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 813                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 814                 >;
 815         };
 816
 817         pinctrl_i2c2: i2c2grp {
 818                 fsl,pins = <
 819                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 820                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 821                 >;
 822         };
 823
 824         pinctrl_i2c2_gpio: i2c2-gpiogrp {
 825                 fsl,pins = <
 826                         MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0x4001b0b9
 827                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0x4001b0b9
 828                 >;
 829         };
 830
 831         pinctrl_kpp: kppgrp {
 832                 fsl,pins = <
 833                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 834                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 835                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 836                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 837                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 838                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 839                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 840                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 841                 >;
 842         };
 843
 844         pinctrl_lcd_pwr: lcd-pwrgrp {
 845                 fsl,pins = <
 846                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 847                 >;
 848         };
 849
 850         pinctrl_lcd_rst: lcd-rstgrp {
 851                 fsl,pins = <
 852                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 853                 >;
 854         };
 855
 856         pinctrl_pwm5: pwm5grp {
 857                 fsl,pins = <
 858                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 859                 >;
 860         };
 861
 862         pinctrl_sai2: sai2grp {
 863                 fsl,pins = <
 864                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 865                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 866                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 867                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 868                 >;
 869         };
 870
 871         pinctrl_spi_gpio: spi-gpiogrp {
 872                 fsl,pins = <
 873                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 874                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 875                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 876                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 877                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 878                 >;
 879         };
 880
 881         pinctrl_tsc2007: tsc2007grp {
 882                 fsl,pins = <
 883                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 884                 >;
 885         };
 886
 887         pinctrl_uart1: uart1grp {
 888                 fsl,pins = <
 889                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 890                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 891                 >;
 892         };
 893
 894         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 895                 fsl,pins = <
 896                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 897                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 898                 >;
 899         };
 900
 901         pinctrl_uart2: uart2grp {
 902                 fsl,pins = <
 903                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 904                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 905                 >;
 906         };
 907
 908         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 909                 fsl,pins = <
 910                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 911                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 912                 >;
 913         };
 914
 915         pinctrl_uart5: uart5grp {
 916                 fsl,pins = <
 917                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 918                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 919                 >;
 920         };
 921
 922         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 923                 fsl,pins = <
 924                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 925                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 926                 >;
 927         };
 928
 929         pinctrl_usbh1_oc: usbh1-ocgrp {
 930                 fsl,pins = <
 931                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 932                 >;
 933         };
 934
 935         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 936                 fsl,pins = <
 937                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 938                 >;
 939         };
 940
 941         pinctrl_usbotg_oc: usbotg-ocgrp {
 942                 fsl,pins = <
 943                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 944                 >;
 945         };
 946
 947         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 948                 fsl,pins = <
 949                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 950                 >;
 951         };
 952
 953         pinctrl_usdhc1: usdhc1grp {
 954                 fsl,pins = <
 955                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 956                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 957                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 958                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 959                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 960                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 961                 >;
 962         };
 963
 964         pinctrl_usdhc1_cd: usdhc1cdgrp {
 965                 fsl,pins = <
 966                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 967                 >;
 968         };
 969
 970         pinctrl_usdhc2: usdhc2grp {
 971                 fsl,pins = <
 972                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 973                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 974                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 975                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 976                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 977                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 978                         /* eMMC RESET */
 979                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 980                 >;
 981         };
 982 };