arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46
  47 / {
  48         aliases {
  49                 can0 = &can2;
  50                 can1 = &can1;
  51                 display = &display;
  52                 i2c0 = &i2c_gpio;
  53                 i2c1 = &i2c2;
  54                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  55                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  56                 pwm0 = &pwm5;
  57                 reg_can_xcvr = &reg_can_xcvr;
  58                 serial2 = &uart5;
  59 //              spi0 = &ecspi2;
  60                 spi0 = &spi_gpio;
  61                 stk5led = &user_led;
  62                 usbh1 = &usbotg2;
  63                 usbotg = &usbotg1;
  64         };
  65
  66         chosen {
  67                 stdout-path = &uart1;
  68         };
  69
  70         memory {
  71                 reg = <0 0>; /* will be filled by U-Boot */
  72         };
  73
  74         clocks {
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 mclk: clock@0 {
  78                         compatible = "fixed-clock";
  79                         reg = <0>;
  80                         #clock-cells = <0>;
  81                         clock-frequency = <27000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  88                 power-supply = <&reg_3v3>;
  89                 /*
  90                  * a poor man's way to create a 1:1 relationship between
  91                  * the PWM value and the actual duty cycle
  92                  */
  93                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  94                                      10 11 12 13 14 15 16 17 18 19
  95                                      20 21 22 23 24 25 26 27 28 29
  96                                      30 31 32 33 34 35 36 37 38 39
  97                                      40 41 42 43 44 45 46 47 48 49
  98                                      50 51 52 53 54 55 56 57 58 59
  99                                      60 61 62 63 64 65 66 67 68 69
 100                                      70 71 72 73 74 75 76 77 78 79
 101                                      80 81 82 83 84 85 86 87 88 89
 102                                      90 91 92 93 94 95 96 97 98 99
 103                                     100>;
 104                 default-brightness-level = <50>;
 105         };
 106
 107         gpio-keys {
 108                 compatible = "gpio-keys";
 109         };
 110
 111         i2c_gpio: i2c-gpio {
 112                 compatible = "i2c-gpio";
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 117                 gpios = <
 118                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 119                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 120                 >;
 121                 clock-frequency = <400000>;
 122                 status = "okay";
 123
 124                 ds1339: rtc@68 {
 125                         compatible = "dallas,ds1339";
 126                         reg = <0x68>;
 127                         status = "disabled";
 128                 };
 129         };
 130
 131         leds {
 132                 compatible = "gpio-leds";
 133
 134                 user_led: user {
 135                         label = "Heartbeat";
 136                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 137                         linux,default-trigger = "heartbeat";
 138                 };
 139         };
 140
 141         regulators {
 142                 compatible = "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145
 146                 reg_3v3_etn: regulator@0 {
 147                         compatible = "regulator-fixed";
 148                         reg = <0>;
 149                         regulator-name = "3V3_ETN";
 150                         regulator-min-microvolt = <3300000>;
 151                         regulator-max-microvolt = <3300000>;
 152                         pinctrl-names = "default";
 153                         pinctrl-0 = <&pinctrl_etnphy_power>;
 154                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 155                         enable-active-high;
 156                 };
 157
 158                 reg_2v5: regulator@1 {
 159                         compatible = "regulator-fixed";
 160                         reg = <1>;
 161                         regulator-name = "2V5";
 162                         regulator-min-microvolt = <2500000>;
 163                         regulator-max-microvolt = <2500000>;
 164                         regulator-always-on;
 165                 };
 166
 167                 reg_3v3: regulator@2 {
 168                         compatible = "regulator-fixed";
 169                         reg = <2>;
 170                         regulator-name = "3V3";
 171                         regulator-min-microvolt = <3300000>;
 172                         regulator-max-microvolt = <3300000>;
 173                         regulator-always-on;
 174                 };
 175
 176                 reg_can_xcvr: regulator@3 {
 177                         compatible = "regulator-fixed";
 178                         reg = <3>;
 179                         regulator-name = "CAN XCVR";
 180                         regulator-min-microvolt = <3300000>;
 181                         regulator-max-microvolt = <3300000>;
 182                         pinctrl-names = "default";
 183                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 184                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 185                         enable-active-low;
 186                 };
 187
 188                 reg_lcd_pwr: regulator@5 {
 189                         compatible = "regulator-fixed";
 190                         reg = <5>;
 191                         regulator-name = "LCD POWER";
 192                         regulator-min-microvolt = <3300000>;
 193                         regulator-max-microvolt = <3300000>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_lcd_pwr>;
 196                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 197                         enable-active-high;
 198                         regulator-boot-on;
 199                         regulator-always-on;
 200                 };
 201
 202                 reg_lcd_reset: regulator@6 {
 203                         compatible = "regulator-fixed";
 204                         reg = <6>;
 205                         regulator-name = "LCD RESET";
 206                         regulator-min-microvolt = <3300000>;
 207                         regulator-max-microvolt = <3300000>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&pinctrl_lcd_reset>;
 210                         gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 211                         enable-active-high;
 212                         regulator-boot-on;
 213                         regulator-always-on;
 214                 };
 215
 216                 reg_usbh1_vbus: regulator@7 {
 217                         compatible = "regulator-fixed";
 218                         reg = <7>;
 219                         regulator-name = "usbh1_vbus";
 220                         regulator-min-microvolt = <5000000>;
 221                         regulator-max-microvolt = <5000000>;
 222                         pinctrl-names = "default";
 223                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 224                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 225                         enable-active-high;
 226                 };
 227
 228                 reg_usbotg_vbus: regulator@8 {
 229                         compatible = "regulator-fixed";
 230                         reg = <8>;
 231                         regulator-name = "usbotg_vbus";
 232                         regulator-min-microvolt = <5000000>;
 233                         regulator-max-microvolt = <5000000>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 236                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 237                         enable-active-high;
 238                 };
 239         };
 240
 241         spi_gpio: spi-gpio {
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 compatible = "spi-gpio";
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&pinctrl_spi_gpio>;
 247                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 248                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 249                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 250                 num-chipselects = <2>;
 251                 cs-gpios = <
 252                         &gpio1 29 GPIO_ACTIVE_HIGH
 253                         &gpio1 10 GPIO_ACTIVE_HIGH
 254                 >;
 255                 status = "okay";
 256
 257                 spidev0: spi@0 {
 258                         compatible = "spidev";
 259                         reg = <0>;
 260                         spi-max-frequency = <54000000>;
 261                 };
 262
 263                 spidev1: spi@1 {
 264                         compatible = "spidev";
 265                         reg = <1>;
 266                         spi-max-frequency = <54000000>;
 267                 };
 268         };
 269
 270         sound {
 271                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 272                              "fsl,imx-audio-sgtl5000";
 273                 model = "imx6ul-tx6ul-sgtl5000-audio";
 274                 ssi-controller = <&sai2>;
 275                 audio-codec = <&sgtl5000>;
 276                 audio-routing =
 277                         "MIC_IN", "Mic Jack",
 278                         "Mic Jack", "Mic Bias",
 279                         "Headphone Jack", "HP_OUT";
 280                 fsl,no-audmux;
 281         };
 282 };
 283
 284 &can1 {
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_flexcan1>;
 287         xceiver-supply = <&reg_can_xcvr>;
 288         status = "okay";
 289 };
 290
 291 &can2 {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_flexcan2>;
 294         xceiver-supply = <&reg_can_xcvr>;
 295         status = "okay";
 296 };
 297
 298 #if 0
 299 &ecspi2 {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_ecspi2>;
 302         fsl,spi-num-chipselects = <2>;
 303         cs-gpios = <
 304                 &gpio1 29 GPIO_ACTIVE_HIGH
 305                 &gpio1 10 GPIO_ACTIVE_HIGH
 306         >;
 307         status = "okay";
 308
 309         spidev0: spi@0 {
 310                 compatible = "spidev";
 311                 reg = <0>;
 312                 spi-max-frequency = <54000000>;
 313         };
 314
 315         spidev1: spi@1 {
 316                 compatible = "spidev";
 317                 reg = <1>;
 318                 spi-max-frequency = <54000000>;
 319         };
 320 };
 321 #endif
 322
 323 &fec1 {
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
 326         phy-mode = "rmii";
 327         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
 328         phy-supply = <&reg_3v3_etn>;
 329         phy-handle = <&etnphy0>;
 330         status = "okay";
 331
 332         mdio {
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335
 336                 etnphy0: ethernet-phy@0 {
 337                         compatible = "ethernet-phy-ieee802.3-c22";
 338                         reg = <0>;
 339                         interrupt-parent = <&gpio5>;
 340                         interrupts = <5>;
 341                         status = "okay";
 342                 };
 343
 344                 etnphy1: ethernet-phy@1 {
 345                         compatible = "ethernet-phy-ieee802.3-c22";
 346                         reg = <1>;
 347                         status = "okay";
 348                 };
 349         };
 350 };
 351
 352 &fec2 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_enet2>;
 355         phy-mode = "rmii";
 356         phy-supply = <&reg_3v3_etn>;
 357         phy-handle = <&etnphy1>;
 358         status = "disabled";
 359 };
 360
 361 &gpmi {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_gpmi_nand>;
 364         nand-on-flash-bbt;
 365         fsl,no-blockmark-swap;
 366         status = "okay";
 367 };
 368
 369 &i2c2 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_i2c2>;
 372         clock-frequency = <400000>;
 373         status = "okay";
 374
 375         sgtl5000: sgtl5000@0a {
 376                 compatible = "fsl,sgtl5000";
 377                 reg = <0x0a>;
 378                 VDDA-supply = <&reg_2v5>;
 379                 VDDIO-supply = <&reg_3v3>;
 380                 clocks = <&mclk>;
 381         };
 382
 383         polytouch: edt-ft5x06@38 {
 384                 compatible = "edt,edt-ft5x06";
 385                 reg = <0x38>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 388                 interrupt-parent = <&gpio5>;
 389                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 390                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 391                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 392                 linux,wakeup;
 393         };
 394
 395         touchscreen: tsc2007@48 {
 396                 compatible = "ti,tsc2007";
 397                 reg = <0x48>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pinctrl_tsc2007>;
 400                 interrupt-parent = <&gpio3>;
 401                 interrupts = <26 0>;
 402                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 403                 ti,x-plate-ohms = <660>;
 404                 linux,wakeup;
 405         };
 406 };
 407
 408 &iomuxc {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_hog>;
 411
 412         imx6qdl-tx6 {
 413                 pinctrl_hog: hoggrp {
 414                         fsl,pins = <
 415                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 416                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 417                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 418                         >;
 419                 };
 420
 421                 pinctrl_disp0_1: disp0grp-1 {
 422                         fsl,pins = <
 423                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 424                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 425                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
 426                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
 427                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 428                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 429                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 430                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 431                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 432                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 433                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 434                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 435                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 436                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 437                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 438                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 439                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 440                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 441                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 442                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 443                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 444                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 445                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 446                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 447                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 448                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 449                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 450                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 451                         >;
 452                 };
 453
 454                 pinctrl_disp0_2: disp0grp-2 {
 455                         fsl,pins = <
 456                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 457                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 458                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 459                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 460                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 461                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 462                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 463                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 464                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 465                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 466                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 467                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 468                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 469                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 470                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 471                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 472                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 473                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 474                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 475                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 476                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 477                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 478                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 479                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 480                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 481                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 482                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 483                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 484                         >;
 485                 };
 486
 487                 pinctrl_ecspi2: ecspi2grp {
 488                         fsl,pins = <
 489                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 490                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 491                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 492                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 493                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 494                         >;
 495                 };
 496
 497                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 498                         fsl,pins = <
 499                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 500                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 501                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 502                         >;
 503                 };
 504
 505                 pinctrl_enet1: enet1grp {
 506                         fsl,pins = <
 507                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
 508                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
 509                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
 510                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
 511                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
 512                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
 513                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
 514                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
 515                         >;
 516                 };
 517
 518                 pinctrl_enet2: enet2grp {
 519                         fsl,pins = <
 520                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
 521                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
 522                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
 523                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
 524                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
 525                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
 526                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
 527                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
 528                         >;
 529                 };
 530
 531                 pinctrl_enet_mdio: enet-mdiogrp {
 532                         fsl,pins = <
 533                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 534                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 535                         >;
 536                 };
 537
 538                 pinctrl_etnphy_power: etnphy-pwrgrp {
 539                         fsl,pins = <
 540                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 541                         >;
 542                 };
 543
 544                 pinctrl_flexcan1: flexcan1grp {
 545                         fsl,pins = <
 546                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
 547                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
 548                         >;
 549                 };
 550
 551                 pinctrl_flexcan2: flexcan2grp {
 552                         fsl,pins = <
 553                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
 554                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
 555                         >;
 556                 };
 557
 558                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 559                         fsl,pins = <
 560                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 561                         >;
 562                 };
 563
 564                 pinctrl_gpmi_nand: gpminandgrp {
 565                         fsl,pins = <
 566                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 567                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 568                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 569                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 570                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 571                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 572                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 573                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 574                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 575                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 576                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 577                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 578                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 579                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 580                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 581                         >;
 582                 };
 583
 584                 pinctrl_i2c_gpio: i2c-gpiogrp {
 585                         fsl,pins = <
 586                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 587                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 588                         >;
 589                 };
 590
 591                 pinctrl_i2c2: i2c2grp {
 592                         fsl,pins = <
 593                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 594                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 595                         >;
 596                 };
 597
 598                 pinctrl_kpp: kppgrp {
 599                         fsl,pins = <
 600                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 601                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 602                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 603                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 604                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 605                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 606                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 607                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 608                         >;
 609                 };
 610
 611                 pinctrl_lcd_pwr: lcd-pwrgrp {
 612                         fsl,pins = <
 613                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 614                         >;
 615                 };
 616
 617                 pinctrl_lcd_reset: lcd-resetgrp {
 618                         fsl,pins = <
 619                                 MX6UL_PAD_LCD_RESET__GPIO3_IO04         0x0b0b0 /* LCD RESET */
 620                         >;
 621                 };
 622
 623                 pinctrl_pwm5: pwm5grp {
 624                         fsl,pins = <
 625                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 626                         >;
 627                 };
 628
 629                 pinctrl_sai2: sai2grp {
 630                         fsl,pins = <
 631                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 632                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 633                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 634                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 635                         >;
 636                 };
 637
 638                 pinctrl_spi_gpio: spi-gpiogrp {
 639                         fsl,pins = <
 640                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 641                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 642                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 643                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 644                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 645                         >;
 646                 };
 647
 648                 pinctrl_tsc2007: tsc2007grp {
 649                         fsl,pins = <
 650                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 651                         >;
 652                 };
 653
 654                 pinctrl_uart1: uart1grp {
 655                         fsl,pins = <
 656                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 657                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 658                         >;
 659                 };
 660
 661                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 662                         fsl,pins = <
 663                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 664                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 665                         >;
 666                 };
 667
 668                 pinctrl_uart2: uart2grp {
 669                         fsl,pins = <
 670                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 671                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 672                         >;
 673                 };
 674
 675                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 676                         fsl,pins = <
 677                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 678                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 679                         >;
 680                 };
 681
 682                 pinctrl_uart5: uart5grp {
 683                         fsl,pins = <
 684                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 685                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 686                         >;
 687                 };
 688
 689                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
 690                         fsl,pins = <
 691                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 692                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 693                         >;
 694                 };
 695
 696                 pinctrl_usbh1_oc: usbh1-ocgrp {
 697                         fsl,pins = <
 698                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 699                         >;
 700                 };
 701
 702                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 703                         fsl,pins = <
 704                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 705                         >;
 706                 };
 707
 708                 pinctrl_usbotg_oc: usbotg-ocgrp {
 709                         fsl,pins = <
 710                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 711                         >;
 712                 };
 713
 714                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 715                         fsl,pins = <
 716                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 717                         >;
 718                 };
 719
 720                 pinctrl_usdhc1: usdhc1grp {
 721                         fsl,pins = <
 722                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 723                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 724                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 725                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 726                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 727                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 728                                 /* SD1 CD */
 729                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 730                         >;
 731                 };
 732                 pinctrl_usdhc2: usdhc2grp {
 733                         fsl,pins = <
 734                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 735                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 736                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 737                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 738                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 739                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 740                                 /* eMMC RESET */
 741                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 742                         >;
 743                 };
 744         };
 745 };
 746
 747 &kpp {
 748         pinctrl-names = "default";
 749         pinctrl-0 = <&pinctrl_kpp>;
 750         /* sample keymap */
 751         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 752         linux,keymap = <
 753                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 754                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 755                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 756                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 757                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 758                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 759                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 760                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 761                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 762                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 763                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 764         >;
 765         status = "okay";
 766 };
 767
 768 &lcdif {
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&pinctrl_disp0_1>;
 771         lcd-supply = <&reg_lcd_pwr>;
 772         display = <&display>;
 773         status = "okay";
 774
 775         display: display@di0 {
 776                 bits-per-pixel = <32>;
 777                 bus-width = <24>;
 778                 status = "okay";
 779
 780                 display-timings {
 781                         VGA {
 782                                 clock-frequency = <25200000>;
 783                                 hactive = <640>;
 784                                 vactive = <480>;
 785                                 hback-porch = <48>;
 786                                 hsync-len = <96>;
 787                                 hfront-porch = <16>;
 788                                 vback-porch = <31>;
 789                                 vsync-len = <2>;
 790                                 vfront-porch = <12>;
 791                                 hsync-active = <0>;
 792                                 vsync-active = <0>;
 793                                 de-active = <1>;
 794                                 pixelclk-active = <1>;
 795                         };
 796
 797                         ETV570 {
 798                                 clock-frequency = <25200000>;
 799                                 hactive = <640>;
 800                                 vactive = <480>;
 801                                 hback-porch = <114>;
 802                                 hsync-len = <30>;
 803                                 hfront-porch = <16>;
 804                                 vback-porch = <32>;
 805                                 vsync-len = <3>;
 806                                 vfront-porch = <10>;
 807                                 hsync-active = <0>;
 808                                 vsync-active = <0>;
 809                                 de-active = <1>;
 810                                 pixelclk-active = <1>;
 811                         };
 812
 813                         ET0350 {
 814                                 clock-frequency = <6413760>;
 815                                 hactive = <320>;
 816                                 vactive = <240>;
 817                                 hback-porch = <34>;
 818                                 hsync-len = <34>;
 819                                 hfront-porch = <20>;
 820                                 vback-porch = <15>;
 821                                 vsync-len = <3>;
 822                                 vfront-porch = <4>;
 823                                 hsync-active = <0>;
 824                                 vsync-active = <0>;
 825                                 de-active = <1>;
 826                                 pixelclk-active = <1>;
 827                         };
 828
 829                         ET0430 {
 830                                 clock-frequency = <9009000>;
 831                                 hactive = <480>;
 832                                 vactive = <272>;
 833                                 hback-porch = <2>;
 834                                 hsync-len = <41>;
 835                                 hfront-porch = <2>;
 836                                 vback-porch = <2>;
 837                                 vsync-len = <10>;
 838                                 vfront-porch = <2>;
 839                                 hsync-active = <0>;
 840                                 vsync-active = <0>;
 841                                 de-active = <1>;
 842                                 pixelclk-active = <0>;
 843                         };
 844
 845                         ET0500 {
 846                                 clock-frequency = <33264000>;
 847                                 hactive = <800>;
 848                                 vactive = <480>;
 849                                 hback-porch = <88>;
 850                                 hsync-len = <128>;
 851                                 hfront-porch = <40>;
 852                                 vback-porch = <33>;
 853                                 vsync-len = <2>;
 854                                 vfront-porch = <10>;
 855                                 hsync-active = <0>;
 856                                 vsync-active = <0>;
 857                                 de-active = <1>;
 858                                 pixelclk-active = <1>;
 859                         };
 860
 861                         ET0700 { /* same as ET0500 */
 862                                 clock-frequency = <33264000>;
 863                                 hactive = <800>;
 864                                 vactive = <480>;
 865                                 hback-porch = <88>;
 866                                 hsync-len = <128>;
 867                                 hfront-porch = <40>;
 868                                 vback-porch = <33>;
 869                                 vsync-len = <2>;
 870                                 vfront-porch = <10>;
 871                                 hsync-active = <0>;
 872                                 vsync-active = <0>;
 873                                 de-active = <1>;
 874                                 pixelclk-active = <1>;
 875                         };
 876
 877                         ETQ570 {
 878                                 clock-frequency = <6596040>;
 879                                 hactive = <320>;
 880                                 vactive = <240>;
 881                                 hback-porch = <38>;
 882                                 hsync-len = <30>;
 883                                 hfront-porch = <30>;
 884                                 vback-porch = <16>;
 885                                 vsync-len = <3>;
 886                                 vfront-porch = <4>;
 887                                 hsync-active = <0>;
 888                                 vsync-active = <0>;
 889                                 de-active = <1>;
 890                                 pixelclk-active = <1>;
 891                         };
 892                 };
 893         };
 894 };
 895
 896 &pwm5 {
 897         pinctrl-names = "default";
 898         pinctrl-0 = <&pinctrl_pwm5>;
 899         #pwm-cells = <3>;
 900         status = "okay";
 901 };
 902
 903 &sai2 {
 904         pinctrl-names = "default";
 905         pinctrl-0 = <&pinctrl_sai2>;
 906         status = "okay";
 907 };
 908
 909 &uart1 {
 910         pinctrl-names = "default";
 911         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 912         status = "okay";
 913 };
 914
 915 &uart2 {
 916         pinctrl-names = "default";
 917         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 918         status = "okay";
 919 };
 920
 921 &uart5 {
 922         pinctrl-names = "default";
 923         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 924         status = "okay";
 925 };
 926
 927 &usbotg2 {
 928         vbus-supply = <&reg_usbh1_vbus>;
 929         dr_mode = "host";
 930         disable-over-current;
 931         status = "okay";
 932 };
 933
 934 &usbotg1 {
 935         vbus-supply = <&reg_usbotg_vbus>;
 936         dr_mode = "peripheral";
 937         disable-over-current;
 938         status = "okay";
 939 };
 940
 941 &usdhc1 {
 942         pinctrl-names = "default";
 943         pinctrl-0 = <&pinctrl_usdhc1>;
 944         bus-width = <4>;
 945         no-1-8-v;
 946         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 947         fsl,wp-controller;
 948         status = "okay";
 949 };