arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46
  47 / {
  48         aliases {
  49                 can0 = &can2;
  50                 can1 = &can1;
  51                 display = &display;
  52                 i2c0 = &i2c_gpio;
  53                 i2c1 = &i2c2;
  54                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  55                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  56                 pwm0 = &pwm5;
  57                 reg_can_xcvr = &reg_can_xcvr;
  58                 serial2 = &uart5;
  59                 serial4 = &uart3;
  60                 spi0 = &ecspi2;
  61                 spi1 = &spi_gpio;
  62                 stk5led = &user_led;
  63                 usbh1 = &usbotg2;
  64                 usbotg = &usbotg1;
  65         };
  66
  67         chosen {
  68                 stdout-path = &uart1;
  69         };
  70
  71         memory {
  72                 reg = <0 0>; /* will be filled by U-Boot */
  73         };
  74
  75         clocks {
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78                 mclk: clock@0 {
  79                         compatible = "fixed-clock";
  80                         reg = <0>;
  81                         #clock-cells = <0>;
  82                         clock-frequency = <27000000>;
  83                 };
  84         };
  85
  86         backlight: backlight {
  87                 compatible = "pwm-backlight";
  88                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  89                 power-supply = <&reg_3v3>;
  90                 /*
  91                  * a poor man's way to create a 1:1 relationship between
  92                  * the PWM value and the actual duty cycle
  93                  */
  94                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  95                                      10 11 12 13 14 15 16 17 18 19
  96                                      20 21 22 23 24 25 26 27 28 29
  97                                      30 31 32 33 34 35 36 37 38 39
  98                                      40 41 42 43 44 45 46 47 48 49
  99                                      50 51 52 53 54 55 56 57 58 59
 100                                      60 61 62 63 64 65 66 67 68 69
 101                                      70 71 72 73 74 75 76 77 78 79
 102                                      80 81 82 83 84 85 86 87 88 89
 103                                      90 91 92 93 94 95 96 97 98 99
 104                                     100>;
 105                 default-brightness-level = <50>;
 106         };
 107
 108         gpio-keys {
 109                 compatible = "gpio-keys";
 110         };
 111
 112         i2c_gpio: i2c-gpio {
 113                 compatible = "i2c-gpio";
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116                 pinctrl-names = "default";
 117                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 118                 gpios = <
 119                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 120                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 121                 >;
 122                 clock-frequency = <400000>;
 123                 status = "okay";
 124
 125                 ds1339: rtc@68 {
 126                         compatible = "dallas,ds1339";
 127                         reg = <0x68>;
 128                         status = "disabled";
 129                 };
 130         };
 131
 132         leds {
 133                 compatible = "gpio-leds";
 134
 135                 user_led: user {
 136                         label = "Heartbeat";
 137                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 138                         linux,default-trigger = "heartbeat";
 139                 };
 140         };
 141
 142         regulators {
 143                 compatible = "simple-bus";
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146
 147                 reg_3v3_etn: regulator@0 {
 148                         compatible = "regulator-fixed";
 149                         reg = <0>;
 150                         regulator-name = "3V3_ETN";
 151                         regulator-min-microvolt = <3300000>;
 152                         regulator-max-microvolt = <3300000>;
 153                         pinctrl-names = "default";
 154                         pinctrl-0 = <&pinctrl_etnphy_power>;
 155                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 156                         enable-active-high;
 157                 };
 158
 159                 reg_2v5: regulator@1 {
 160                         compatible = "regulator-fixed";
 161                         reg = <1>;
 162                         regulator-name = "2V5";
 163                         regulator-min-microvolt = <2500000>;
 164                         regulator-max-microvolt = <2500000>;
 165                         regulator-always-on;
 166                 };
 167
 168                 reg_3v3: regulator@2 {
 169                         compatible = "regulator-fixed";
 170                         reg = <2>;
 171                         regulator-name = "3V3";
 172                         regulator-min-microvolt = <3300000>;
 173                         regulator-max-microvolt = <3300000>;
 174                         regulator-always-on;
 175                 };
 176
 177                 reg_can_xcvr: regulator@3 {
 178                         compatible = "regulator-fixed";
 179                         reg = <3>;
 180                         regulator-name = "CAN XCVR";
 181                         regulator-min-microvolt = <3300000>;
 182                         regulator-max-microvolt = <3300000>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 185                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 186                         enable-active-low;
 187                 };
 188
 189                 reg_lcd_pwr: regulator@5 {
 190                         compatible = "regulator-fixed";
 191                         reg = <5>;
 192                         regulator-name = "LCD POWER";
 193                         regulator-min-microvolt = <3300000>;
 194                         regulator-max-microvolt = <3300000>;
 195                         pinctrl-names = "default";
 196                         pinctrl-0 = <&pinctrl_lcd_pwr>;
 197                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 198                         enable-active-high;
 199                         regulator-boot-on;
 200                         regulator-always-on;
 201                 };
 202
 203                 reg_lcd_reset: regulator@6 {
 204                         compatible = "regulator-fixed";
 205                         reg = <6>;
 206                         regulator-name = "LCD RESET";
 207                         regulator-min-microvolt = <3300000>;
 208                         regulator-max-microvolt = <3300000>;
 209                         pinctrl-names = "default";
 210                         pinctrl-0 = <&pinctrl_lcd_reset>;
 211                         gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
 212                         enable-active-high;
 213                         regulator-boot-on;
 214                         regulator-always-on;
 215                 };
 216
 217                 reg_usbh1_vbus: regulator@7 {
 218                         compatible = "regulator-fixed";
 219                         reg = <7>;
 220                         regulator-name = "usbh1_vbus";
 221                         regulator-min-microvolt = <5000000>;
 222                         regulator-max-microvolt = <5000000>;
 223                         pinctrl-names = "default";
 224                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 225                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 226                         enable-active-high;
 227                 };
 228
 229                 reg_usbotg_vbus: regulator@8 {
 230                         compatible = "regulator-fixed";
 231                         reg = <8>;
 232                         regulator-name = "usbotg_vbus";
 233                         regulator-min-microvolt = <5000000>;
 234                         regulator-max-microvolt = <5000000>;
 235                         pinctrl-names = "default";
 236                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 237                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 238                         enable-active-high;
 239                 };
 240         };
 241
 242         spi_gpio: spi-gpio {
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 compatible = "spi-gpio";
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&pinctrl_spi_gpio>;
 248                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 249                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 250                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 251                 num-chipselects = <2>;
 252                 cs-gpios = <
 253                         &gpio1 29 GPIO_ACTIVE_HIGH
 254                         &gpio1 10 GPIO_ACTIVE_HIGH
 255                 >;
 256                 status = "disabled";
 257
 258                 spi@0 {
 259                         compatible = "spidev";
 260                         reg = <0>;
 261                         spi-max-frequency = <54000000>;
 262                 };
 263
 264                 spi@1 {
 265                         compatible = "spidev";
 266                         reg = <1>;
 267                         spi-max-frequency = <54000000>;
 268                 };
 269         };
 270
 271         sound {
 272                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 273                              "fsl,imx-audio-sgtl5000";
 274                 model = "imx6ul-tx6ul-sgtl5000-audio";
 275                 ssi-controller = <&sai2>;
 276                 audio-codec = <&sgtl5000>;
 277                 audio-routing =
 278                         "MIC_IN", "Mic Jack",
 279                         "Mic Jack", "Mic Bias",
 280                         "Headphone Jack", "HP_OUT";
 281                 fsl,no-audmux;
 282         };
 283 };
 284
 285 &can1 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_flexcan1>;
 288         xceiver-supply = <&reg_can_xcvr>;
 289         status = "okay";
 290 };
 291
 292 &can2 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_flexcan2>;
 295         xceiver-supply = <&reg_can_xcvr>;
 296         status = "okay";
 297 };
 298
 299 &ecspi2 {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_ecspi2>;
 302         fsl,spi-num-chipselects = <2>;
 303         cs-gpios = <
 304                 &gpio1 29 GPIO_ACTIVE_HIGH
 305                 &gpio1 10 GPIO_ACTIVE_HIGH
 306         >;
 307         status = "okay";
 308
 309         spi@0 {
 310                 compatible = "spidev";
 311                 reg = <0>;
 312                 spi-max-frequency = <54000000>;
 313         };
 314
 315         spi@1 {
 316                 compatible = "spidev";
 317                 reg = <1>;
 318                 spi-max-frequency = <54000000>;
 319         };
 320 };
 321
 322 &fec1 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
 325         phy-mode = "rmii";
 326         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
 327         phy-supply = <&reg_3v3_etn>;
 328         phy-handle = <&etnphy0>;
 329         status = "okay";
 330
 331         mdio {
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334
 335                 etnphy0: ethernet-phy@0 {
 336                         compatible = "ethernet-phy-ieee802.3-c22";
 337                         reg = <0>;
 338                         interrupt-parent = <&gpio5>;
 339                         interrupts = <5>;
 340                         status = "okay";
 341                 };
 342
 343                 etnphy1: ethernet-phy@1 {
 344                         compatible = "ethernet-phy-ieee802.3-c22";
 345                         reg = <1>;
 346                         status = "okay";
 347                 };
 348         };
 349 };
 350
 351 &fec2 {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_enet2>;
 354         phy-mode = "rmii";
 355         phy-supply = <&reg_3v3_etn>;
 356         phy-handle = <&etnphy1>;
 357         status = "disabled";
 358 };
 359
 360 &gpmi {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_gpmi_nand>;
 363         nand-on-flash-bbt;
 364         fsl,no-blockmark-swap;
 365         status = "okay";
 366 };
 367
 368 &i2c2 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_i2c2>;
 371         clock-frequency = <400000>;
 372         status = "okay";
 373
 374         sgtl5000: sgtl5000@0a {
 375                 compatible = "fsl,sgtl5000";
 376                 reg = <0x0a>;
 377                 VDDA-supply = <&reg_2v5>;
 378                 VDDIO-supply = <&reg_3v3>;
 379                 clocks = <&mclk>;
 380         };
 381
 382         polytouch: edt-ft5x06@38 {
 383                 compatible = "edt,edt-ft5x06";
 384                 reg = <0x38>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 387                 interrupt-parent = <&gpio5>;
 388                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 389                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 390                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 391                 linux,wakeup;
 392         };
 393
 394         touchscreen: tsc2007@48 {
 395                 compatible = "ti,tsc2007";
 396                 reg = <0x48>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&pinctrl_tsc2007>;
 399                 interrupt-parent = <&gpio3>;
 400                 interrupts = <26 0>;
 401                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 402                 ti,x-plate-ohms = <660>;
 403                 linux,wakeup;
 404         };
 405 };
 406
 407 &iomuxc {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_hog>;
 410
 411         imx6qdl-tx6 {
 412                 pinctrl_hog: hoggrp {
 413                         fsl,pins = <
 414                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 415                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 416                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 417                         >;
 418                 };
 419
 420                 pinctrl_disp0_1: disp0grp-1 {
 421                         fsl,pins = <
 422                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 423                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 424                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
 425                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
 426                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 427                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 428                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 429                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 430                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 431                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 432                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 433                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 434                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 435                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 436                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 437                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 438                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 439                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 440                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 441                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 442                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 443                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 444                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 445                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 446                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 447                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 448                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 449                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 450                         >;
 451                 };
 452
 453                 pinctrl_disp0_2: disp0grp-2 {
 454                         fsl,pins = <
 455                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 456                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 457                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 458                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 459                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 460                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 461                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 462                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 463                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 464                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 465                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 466                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 467                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 468                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 469                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 470                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 471                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 472                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 473                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 474                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 475                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 476                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 477                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 478                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 479                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 480                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 481                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 482                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 483                         >;
 484                 };
 485
 486                 pinctrl_ecspi2: ecspi2grp {
 487                         fsl,pins = <
 488                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 489                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 490                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 491                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 492                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 493                         >;
 494                 };
 495
 496                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 497                         fsl,pins = <
 498                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 499                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 500                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 501                         >;
 502                 };
 503
 504                 pinctrl_enet1: enet1grp {
 505                         fsl,pins = <
 506                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
 507                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
 508                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
 509                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
 510                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
 511                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
 512                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
 513                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
 514                         >;
 515                 };
 516
 517                 pinctrl_enet2: enet2grp {
 518                         fsl,pins = <
 519                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
 520                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
 521                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
 522                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
 523                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
 524                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
 525                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
 526                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
 527                         >;
 528                 };
 529
 530                 pinctrl_enet_mdio: enet-mdiogrp {
 531                         fsl,pins = <
 532                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 533                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 534                         >;
 535                 };
 536
 537                 pinctrl_etnphy_power: etnphy-pwrgrp {
 538                         fsl,pins = <
 539                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 540                         >;
 541                 };
 542
 543                 pinctrl_flexcan1: flexcan1grp {
 544                         fsl,pins = <
 545                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
 546                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
 547                         >;
 548                 };
 549
 550                 pinctrl_flexcan2: flexcan2grp {
 551                         fsl,pins = <
 552                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
 553                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
 554                         >;
 555                 };
 556
 557                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 558                         fsl,pins = <
 559                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 560                         >;
 561                 };
 562
 563                 pinctrl_gpmi_nand: gpminandgrp {
 564                         fsl,pins = <
 565                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 566                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 567                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 568                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 569                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 570                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 571                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 572                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 573                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 574                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 575                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 576                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 577                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 578                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 579                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 580                         >;
 581                 };
 582
 583                 pinctrl_i2c_gpio: i2c-gpiogrp {
 584                         fsl,pins = <
 585                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 586                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 587                         >;
 588                 };
 589
 590                 pinctrl_i2c2: i2c2grp {
 591                         fsl,pins = <
 592                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 593                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 594                         >;
 595                 };
 596
 597                 pinctrl_kpp: kppgrp {
 598                         fsl,pins = <
 599                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 600                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 601                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 602                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 603                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 604                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 605                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 606                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 607                         >;
 608                 };
 609
 610                 pinctrl_lcd_pwr: lcd-pwrgrp {
 611                         fsl,pins = <
 612                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 613                         >;
 614                 };
 615
 616                 pinctrl_lcd_reset: lcd-resetgrp {
 617                         fsl,pins = <
 618                                 MX6UL_PAD_LCD_RESET__GPIO3_IO04         0x0b0b0 /* LCD RESET */
 619                         >;
 620                 };
 621
 622                 pinctrl_pwm5: pwm5grp {
 623                         fsl,pins = <
 624                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 625                         >;
 626                 };
 627
 628                 pinctrl_sai2: sai2grp {
 629                         fsl,pins = <
 630                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 631                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 632                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 633                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 634                         >;
 635                 };
 636
 637                 pinctrl_spi_gpio: spi-gpiogrp {
 638                         fsl,pins = <
 639                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 640                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 641                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 642                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 643                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 644                         >;
 645                 };
 646
 647                 pinctrl_tsc2007: tsc2007grp {
 648                         fsl,pins = <
 649                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 650                         >;
 651                 };
 652
 653                 pinctrl_uart1: uart1grp {
 654                         fsl,pins = <
 655                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 656                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 657                         >;
 658                 };
 659
 660                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 661                         fsl,pins = <
 662                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 663                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 664                         >;
 665                 };
 666
 667                 pinctrl_uart2: uart2grp {
 668                         fsl,pins = <
 669                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 670                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 671                         >;
 672                 };
 673
 674                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 675                         fsl,pins = <
 676                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 677                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 678                         >;
 679                 };
 680
 681                 pinctrl_uart5: uart5grp {
 682                         fsl,pins = <
 683                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 684                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 685                         >;
 686                 };
 687
 688                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
 689                         fsl,pins = <
 690                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 691                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 692                         >;
 693                 };
 694
 695                 pinctrl_usbh1_oc: usbh1-ocgrp {
 696                         fsl,pins = <
 697                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 698                         >;
 699                 };
 700
 701                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 702                         fsl,pins = <
 703                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 704                         >;
 705                 };
 706
 707                 pinctrl_usbotg_oc: usbotg-ocgrp {
 708                         fsl,pins = <
 709                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 710                         >;
 711                 };
 712
 713                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 714                         fsl,pins = <
 715                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 716                         >;
 717                 };
 718
 719                 pinctrl_usdhc1: usdhc1grp {
 720                         fsl,pins = <
 721                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 722                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 723                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 724                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 725                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 726                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 727                                 /* SD1 CD */
 728                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 729                         >;
 730                 };
 731                 pinctrl_usdhc2: usdhc2grp {
 732                         fsl,pins = <
 733                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 734                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 735                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 736                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 737                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 738                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 739                                 /* eMMC RESET */
 740                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 741                         >;
 742                 };
 743         };
 744 };
 745
 746 &kpp {
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&pinctrl_kpp>;
 749         /* sample keymap */
 750         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 751         linux,keymap = <
 752                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 753                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 754                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 755                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 756                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 757                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 758                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 759                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 760                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 761                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 762                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 763         >;
 764         status = "okay";
 765 };
 766
 767 &lcdif {
 768         pinctrl-names = "default";
 769         pinctrl-0 = <&pinctrl_disp0_1>;
 770         lcd-supply = <&reg_lcd_pwr>;
 771         display = <&display>;
 772         status = "okay";
 773
 774         display: display@di0 {
 775                 bits-per-pixel = <32>;
 776                 bus-width = <24>;
 777                 status = "okay";
 778
 779                 display-timings {
 780                         VGA {
 781                                 clock-frequency = <25200000>;
 782                                 hactive = <640>;
 783                                 vactive = <480>;
 784                                 hback-porch = <48>;
 785                                 hsync-len = <96>;
 786                                 hfront-porch = <16>;
 787                                 vback-porch = <31>;
 788                                 vsync-len = <2>;
 789                                 vfront-porch = <12>;
 790                                 hsync-active = <0>;
 791                                 vsync-active = <0>;
 792                                 de-active = <1>;
 793                                 pixelclk-active = <1>;
 794                         };
 795
 796                         ETV570 {
 797                                 clock-frequency = <25200000>;
 798                                 hactive = <640>;
 799                                 vactive = <480>;
 800                                 hback-porch = <114>;
 801                                 hsync-len = <30>;
 802                                 hfront-porch = <16>;
 803                                 vback-porch = <32>;
 804                                 vsync-len = <3>;
 805                                 vfront-porch = <10>;
 806                                 hsync-active = <0>;
 807                                 vsync-active = <0>;
 808                                 de-active = <1>;
 809                                 pixelclk-active = <1>;
 810                         };
 811
 812                         ET0350 {
 813                                 clock-frequency = <6413760>;
 814                                 hactive = <320>;
 815                                 vactive = <240>;
 816                                 hback-porch = <34>;
 817                                 hsync-len = <34>;
 818                                 hfront-porch = <20>;
 819                                 vback-porch = <15>;
 820                                 vsync-len = <3>;
 821                                 vfront-porch = <4>;
 822                                 hsync-active = <0>;
 823                                 vsync-active = <0>;
 824                                 de-active = <1>;
 825                                 pixelclk-active = <1>;
 826                         };
 827
 828                         ET0430 {
 829                                 clock-frequency = <9009000>;
 830                                 hactive = <480>;
 831                                 vactive = <272>;
 832                                 hback-porch = <2>;
 833                                 hsync-len = <41>;
 834                                 hfront-porch = <2>;
 835                                 vback-porch = <2>;
 836                                 vsync-len = <10>;
 837                                 vfront-porch = <2>;
 838                                 hsync-active = <0>;
 839                                 vsync-active = <0>;
 840                                 de-active = <1>;
 841                                 pixelclk-active = <0>;
 842                         };
 843
 844                         ET0500 {
 845                                 clock-frequency = <33264000>;
 846                                 hactive = <800>;
 847                                 vactive = <480>;
 848                                 hback-porch = <88>;
 849                                 hsync-len = <128>;
 850                                 hfront-porch = <40>;
 851                                 vback-porch = <33>;
 852                                 vsync-len = <2>;
 853                                 vfront-porch = <10>;
 854                                 hsync-active = <0>;
 855                                 vsync-active = <0>;
 856                                 de-active = <1>;
 857                                 pixelclk-active = <1>;
 858                         };
 859
 860                         ET0700 { /* same as ET0500 */
 861                                 clock-frequency = <33264000>;
 862                                 hactive = <800>;
 863                                 vactive = <480>;
 864                                 hback-porch = <88>;
 865                                 hsync-len = <128>;
 866                                 hfront-porch = <40>;
 867                                 vback-porch = <33>;
 868                                 vsync-len = <2>;
 869                                 vfront-porch = <10>;
 870                                 hsync-active = <0>;
 871                                 vsync-active = <0>;
 872                                 de-active = <1>;
 873                                 pixelclk-active = <1>;
 874                         };
 875
 876                         ETQ570 {
 877                                 clock-frequency = <6596040>;
 878                                 hactive = <320>;
 879                                 vactive = <240>;
 880                                 hback-porch = <38>;
 881                                 hsync-len = <30>;
 882                                 hfront-porch = <30>;
 883                                 vback-porch = <16>;
 884                                 vsync-len = <3>;
 885                                 vfront-porch = <4>;
 886                                 hsync-active = <0>;
 887                                 vsync-active = <0>;
 888                                 de-active = <1>;
 889                                 pixelclk-active = <1>;
 890                         };
 891                 };
 892         };
 893 };
 894
 895 &pwm5 {
 896         pinctrl-names = "default";
 897         pinctrl-0 = <&pinctrl_pwm5>;
 898         #pwm-cells = <3>;
 899         status = "okay";
 900 };
 901
 902 &sai2 {
 903         pinctrl-names = "default";
 904         pinctrl-0 = <&pinctrl_sai2>;
 905         status = "okay";
 906 };
 907
 908 &uart1 {
 909         pinctrl-names = "default";
 910         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 911         status = "okay";
 912 };
 913
 914 &uart2 {
 915         pinctrl-names = "default";
 916         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 917         status = "okay";
 918 };
 919
 920 &uart5 {
 921         pinctrl-names = "default";
 922         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 923         status = "okay";
 924 };
 925
 926 &usbotg2 {
 927         vbus-supply = <&reg_usbh1_vbus>;
 928         dr_mode = "host";
 929         disable-over-current;
 930         status = "okay";
 931 };
 932
 933 &usbotg1 {
 934         vbus-supply = <&reg_usbotg_vbus>;
 935         dr_mode = "peripheral";
 936         disable-over-current;
 937         status = "okay";
 938 };
 939
 940 &usdhc1 {
 941         pinctrl-names = "default";
 942         pinctrl-0 = <&pinctrl_usdhc1>;
 943         bus-width = <4>;
 944         no-1-8-v;
 945         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 946         fsl,wp-controller;
 947         status = "okay";
 948 };