f2050d8cf8e81804a699728f8a8057a2986eaf2f
[karo-tx-linux.git] / arch / arm / boot / dts / imx6ul-tx6ul.dtsi
1 /*
2  * Copyright 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10
11 / {
12         aliases {
13                 can0 = &can2;
14                 can1 = &can1;
15                 display = &display;
16                 i2c0 = &i2c_gpio;
17                 i2c1 = &i2c2;
18                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
19                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
20                 pwm0 = &pwm5;
21                 reg_can_xcvr = &reg_can_xcvr;
22                 serial2 = &uart5;
23 //              spi0 = &ecspi2;
24                 spi0 = &spi_gpio;
25                 stk5led = &user_led;
26                 usbh1 = &usbotg2;
27                 usbotg = &usbotg1;
28         };
29
30         chosen {
31                 stdout-path = &uart1;
32         };
33
34         memory {
35                 reg = <0 0>; /* will be filled by U-Boot */
36         };
37
38         clocks {
39                 #address-cells = <1>;
40                 #size-cells = <0>;
41                 mclk: clock@0 {
42                         compatible = "fixed-clock";
43                         reg = <0>;
44                         #clock-cells = <0>;
45                         clock-frequency = <27000000>;
46                 };
47         };
48
49         backlight: backlight {
50                 compatible = "pwm-backlight";
51                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
52                 power-supply = <&reg_3v3>;
53                 /*
54                  * a poor man's way to create a 1:1 relationship between
55                  * the PWM value and the actual duty cycle
56                  */
57                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
58                                      10 11 12 13 14 15 16 17 18 19
59                                      20 21 22 23 24 25 26 27 28 29
60                                      30 31 32 33 34 35 36 37 38 39
61                                      40 41 42 43 44 45 46 47 48 49
62                                      50 51 52 53 54 55 56 57 58 59
63                                      60 61 62 63 64 65 66 67 68 69
64                                      70 71 72 73 74 75 76 77 78 79
65                                      80 81 82 83 84 85 86 87 88 89
66                                      90 91 92 93 94 95 96 97 98 99
67                                     100>;
68                 default-brightness-level = <50>;
69         };
70
71         gpio-keys {
72                 compatible = "gpio-keys";
73         };
74
75         i2c_gpio: i2c-gpio {
76                 compatible = "i2c-gpio";
77                 #address-cells = <1>;
78                 #size-cells = <0>;
79                 pinctrl-names = "default";
80                 pinctrl-0 = <&pinctrl_i2c_gpio>;
81                 gpios = <
82                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
83                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
84                 >;
85                 clock-frequency = <400000>;
86                 status = "okay";
87
88                 ds1339: rtc@68 {
89                         compatible = "dallas,ds1339";
90                         reg = <0x68>;
91                 };
92         };
93
94         leds {
95                 compatible = "gpio-leds";
96
97                 user_led: user {
98                         label = "Heartbeat";
99                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
100                         linux,default-trigger = "heartbeat";
101                 };
102         };
103
104         regulators {
105                 compatible = "simple-bus";
106                 #address-cells = <1>;
107                 #size-cells = <0>;
108
109                 reg_3v3_etn: regulator@0 {
110                         compatible = "regulator-fixed";
111                         reg = <0>;
112                         regulator-name = "3V3_ETN";
113                         regulator-min-microvolt = <3300000>;
114                         regulator-max-microvolt = <3300000>;
115                         pinctrl-names = "default";
116                         pinctrl-0 = <&pinctrl_etnphy_power>;
117                         gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
118                         enable-active-high;
119                 };
120
121                 reg_2v5: regulator@1 {
122                         compatible = "regulator-fixed";
123                         reg = <1>;
124                         regulator-name = "2V5";
125                         regulator-min-microvolt = <2500000>;
126                         regulator-max-microvolt = <2500000>;
127                         regulator-always-on;
128                 };
129
130                 reg_3v3: regulator@2 {
131                         compatible = "regulator-fixed";
132                         reg = <2>;
133                         regulator-name = "3V3";
134                         regulator-min-microvolt = <3300000>;
135                         regulator-max-microvolt = <3300000>;
136                         regulator-always-on;
137                 };
138
139                 reg_can_xcvr: regulator@3 {
140                         compatible = "regulator-fixed";
141                         reg = <3>;
142                         regulator-name = "CAN XCVR";
143                         regulator-min-microvolt = <3300000>;
144                         regulator-max-microvolt = <3300000>;
145                         pinctrl-names = "default";
146                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
147                         gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
148                         enable-active-low;
149                 };
150
151                 reg_lcd_pwr: regulator@5 {
152                         compatible = "regulator-fixed";
153                         reg = <5>;
154                         regulator-name = "LCD POWER";
155                         regulator-min-microvolt = <3300000>;
156                         regulator-max-microvolt = <3300000>;
157                         pinctrl-names = "default";
158                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
159                         gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
160                         enable-active-high;
161                         regulator-boot-on;
162                         regulator-always-on;
163                 };
164
165                 reg_usbh1_vbus: regulator@6 {
166                         compatible = "regulator-fixed";
167                         reg = <6>;
168                         regulator-name = "usbh1_vbus";
169                         regulator-min-microvolt = <5000000>;
170                         regulator-max-microvolt = <5000000>;
171                         pinctrl-names = "default";
172                         pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
173                         gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
174                         enable-active-high;
175                 };
176
177                 reg_usbotg_vbus: regulator@7 {
178                         compatible = "regulator-fixed";
179                         reg = <7>;
180                         regulator-name = "usbotg_vbus";
181                         regulator-min-microvolt = <5000000>;
182                         regulator-max-microvolt = <5000000>;
183                         pinctrl-names = "default";
184                         pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
185                         gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
186                         enable-active-high;
187                 };
188         };
189
190         spi_gpio: spi-gpio {
191                 #address-cells = <1>;
192                 #size-cells = <0>;
193                 compatible = "spi-gpio";
194                 pinctrl-names = "default";
195                 pinctrl-0 = <&pinctrl_spi_gpio>;
196                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
197                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
198                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
199                 num-chipselects = <2>;
200                 cs-gpios = <
201                         &gpio1 29 GPIO_ACTIVE_HIGH
202                         &gpio1 10 GPIO_ACTIVE_HIGH
203                 >;
204                 status = "okay";
205
206                 spidev0: spi@0 {
207                         compatible = "spidev";
208                         reg = <0>;
209                         spi-max-frequency = <54000000>;
210                 };
211
212                 spidev1: spi@1 {
213                         compatible = "spidev";
214                         reg = <1>;
215                         spi-max-frequency = <54000000>;
216                 };
217         };
218 };
219
220 &can1 {
221         pinctrl-names = "default";
222         pinctrl-0 = <&pinctrl_flexcan1>;
223         xceiver-supply = <&reg_can_xcvr>;
224         status = "okay";
225 };
226
227 &can2 {
228         pinctrl-names = "default";
229         pinctrl-0 = <&pinctrl_flexcan2>;
230         xceiver-supply = <&reg_can_xcvr>;
231         status = "okay";
232 };
233
234 #if 0
235 &ecspi2 {
236         pinctrl-names = "default";
237         pinctrl-0 = <&pinctrl_ecspi2>;
238         fsl,spi-num-chipselects = <2>;
239         cs-gpios = <
240                 &gpio1 29 GPIO_ACTIVE_HIGH
241                 &gpio1 10 GPIO_ACTIVE_HIGH
242         >;
243         status = "okay";
244
245         spidev0: spi@0 {
246                 compatible = "spidev";
247                 reg = <0>;
248                 spi-max-frequency = <54000000>;
249         };
250
251         spidev1: spi@1 {
252                 compatible = "spidev";
253                 reg = <1>;
254                 spi-max-frequency = <54000000>;
255         };
256 };
257 #endif
258
259 &fec1 {
260         pinctrl-names = "default";
261         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
262         phy-mode = "rmii";
263         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
264         phy-supply = <&reg_3v3_etn>;
265         phy-handle = <&etnphy0>;
266         status = "okay";
267
268         mdio {
269                 #address-cells = <1>;
270                 #size-cells = <0>;
271
272                 etnphy0: ethernet-phy@0 {
273                         compatible = "ethernet-phy-ieee802.3-c22";
274                         reg = <0>;
275                         interrupt-parent = <&gpio5>;
276                         interrupts = <5>;
277                         status = "okay";
278                 };
279
280                 etnphy1: ethernet-phy@1 {
281                         compatible = "ethernet-phy-ieee802.3-c22";
282                         reg = <1>;
283                         status = "okay";
284                 };
285         };
286 };
287
288 &fec2 {
289         pinctrl-names = "default";
290         pinctrl-0 = <&pinctrl_enet2>;
291         phy-mode = "rmii";
292         phy-supply = <&reg_3v3_etn>;
293         phy-handle = <&etnphy1>;
294         status = "okay";
295 };
296
297 &gpmi {
298         pinctrl-names = "default";
299         pinctrl-0 = <&pinctrl_gpmi_nand>;
300         nand-on-flash-bbt;
301         fsl,no-blockmark-swap;
302         status = "okay";
303 };
304
305 &i2c2 {
306         pinctrl-names = "default";
307         pinctrl-0 = <&pinctrl_i2c2>;
308         clock-frequency = <400000>;
309         status = "okay";
310
311         sgtl5000: sgtl5000@0a {
312                 compatible = "fsl,sgtl5000";
313                 reg = <0x0a>;
314                 VDDA-supply = <&reg_2v5>;
315                 VDDIO-supply = <&reg_3v3>;
316                 clocks = <&mclk>;
317         };
318
319         polytouch: edt-ft5x06@38 {
320                 compatible = "edt,edt-ft5x06";
321                 reg = <0x38>;
322                 pinctrl-names = "default";
323                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
324                 interrupt-parent = <&gpio5>;
325                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
326                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
327                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
328                 linux,wakeup;
329         };
330
331         touchscreen: tsc2007@48 {
332                 compatible = "ti,tsc2007";
333                 reg = <0x48>;
334                 pinctrl-names = "default";
335                 pinctrl-0 = <&pinctrl_tsc2007>;
336                 interrupt-parent = <&gpio3>;
337                 interrupts = <26 0>;
338                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
339                 ti,x-plate-ohms = <660>;
340                 linux,wakeup;
341         };
342 };
343
344 &iomuxc {
345         pinctrl-names = "default";
346         pinctrl-0 = <&pinctrl_hog>;
347
348         imx6qdl-tx6 {
349                 pinctrl_hog: hoggrp {
350                         fsl,pins = <
351                                 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
352                                 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
353                                 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
354                         >;
355                 };
356
357                 pinctrl_disp0_1: disp0grp-1 {
358                         fsl,pins = <
359                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
360                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
361                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
362                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
363                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
364                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
365                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
366                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
367                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
368                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
369                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
370                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
371                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
372                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
373                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
374                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
375                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
376                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
377                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
378                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
379                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
380                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
381                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
382                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
383                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
384                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
385                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
386                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
387                         >;
388                 };
389
390                 pinctrl_disp0_2: disp0grp-2 {
391                         fsl,pins = <
392                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
393                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
394                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
395                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
396                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
397                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
398                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
399                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
400                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
401                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
402                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
403                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
404                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
405                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
406                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
407                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
408                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
409                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
410                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
411                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
412                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
413                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
414                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
415                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
416                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
417                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
418                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
419                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
420                         >;
421                 };
422
423                 pinctrl_ecspi2: ecspi2grp {
424                         fsl,pins = <
425                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
426                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
427                                 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
428                                 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
429                                 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
430                         >;
431                 };
432
433                 pinctrl_edt_ft5x06: edt-ft5x06grp {
434                         fsl,pins = <
435                                 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
436                                 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
437                                 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
438                         >;
439                 };
440
441                 pinctrl_enet1: enet1grp {
442                         fsl,pins = <
443                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
444                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
445                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
446                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
447                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
448                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
449                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
450                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
451                         >;
452                 };
453
454                 pinctrl_enet2: enet2grp {
455                         fsl,pins = <
456                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
457                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
458                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
459                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
460                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
461                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
462                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
463                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
464                         >;
465                 };
466
467                 pinctrl_enet_mdio: enet-mdiogrp {
468                         fsl,pins = <
469                                 MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
470                                 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
471                         >;
472                 };
473
474                 pinctrl_etnphy_power: etnphy-pwrgrp {
475                         fsl,pins = <
476                                 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
477                         >;
478                 };
479
480                 pinctrl_flexcan1: flexcan1grp {
481                         fsl,pins = <
482                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
483                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
484                         >;
485                 };
486
487                 pinctrl_flexcan2: flexcan2grp {
488                         fsl,pins = <
489                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
490                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
491                         >;
492                 };
493
494                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
495                         fsl,pins = <
496                                 MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
497                         >;
498                 };
499
500                 pinctrl_gpmi_nand: gpminandgrp {
501                         fsl,pins = <
502                                 MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
503                                 MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
504                                 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
505                                 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
506                                 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
507                                 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
508                                 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
509                                 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
510                                 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
511                                 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
512                                 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
513                                 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
514                                 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
515                                 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
516                                 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
517                         >;
518                 };
519
520                 pinctrl_i2c_gpio: i2c-gpiogrp {
521                         fsl,pins = <
522                                 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
523                                 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
524                         >;
525                 };
526
527                 pinctrl_i2c2: i2c2grp {
528                         fsl,pins = <
529                                 MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
530                                 MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
531                         >;
532                 };
533
534                 pinctrl_kpp: kppgrp {
535                         fsl,pins = <
536                                 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
537                                 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
538                                 MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
539                                 MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
540                                 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
541                                 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
542                                 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
543                                 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
544                         >;
545                 };
546
547                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
548                         fsl,pins = <
549                                 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
550                         >;
551                 };
552
553                 pinctrl_pwm5: pwm5grp {
554                         fsl,pins = <
555                                 MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
556                         >;
557                 };
558
559                 pinctrl_sai2: sai2grp {
560                         fsl,pins = <
561                                 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
562                                 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
563                                 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
564                                 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
565                         >;
566                 };
567
568                 pinctrl_spi_gpio: spi-gpiogrp {
569                         fsl,pins = <
570                                 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
571                                 MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
572                                 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
573                                 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
574                                 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
575                         >;
576                 };
577
578                 pinctrl_tsc2007: tsc2007grp {
579                         fsl,pins = <
580                                 MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
581                         >;
582                 };
583
584                 pinctrl_uart1: uart1grp {
585                         fsl,pins = <
586                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
587                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
588                         >;
589                 };
590
591                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
592                         fsl,pins = <
593                                 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
594                                 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
595                         >;
596                 };
597
598                 pinctrl_uart2: uart2grp {
599                         fsl,pins = <
600                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
601                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
602                         >;
603                 };
604
605                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
606                         fsl,pins = <
607                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
608                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
609                         >;
610                 };
611
612                 pinctrl_uart5: uart5grp {
613                         fsl,pins = <
614                                 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
615                                 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
616                         >;
617                 };
618
619                 pinctrl_uart5_rtscts: uart5_rtsctsgrp {
620                         fsl,pins = <
621                                 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
622                                 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
623                         >;
624                 };
625
626                 pinctrl_usbh1_oc: usbh1-ocgrp {
627                         fsl,pins = <
628                                 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
629                         >;
630                 };
631
632                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
633                         fsl,pins = <
634                                 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
635                         >;
636                 };
637
638                 pinctrl_usbotg_oc: usbotg-ocgrp {
639                         fsl,pins = <
640                                 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
641                         >;
642                 };
643
644                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
645                         fsl,pins = <
646                                 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
647                         >;
648                 };
649
650                 pinctrl_usdhc1: usdhc1grp {
651                         fsl,pins = <
652                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
653                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
654                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
655                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
656                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
657                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
658                                 /* SD1 CD */
659                                 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
660                         >;
661                 };
662                 pinctrl_usdhc2: usdhc2grp {
663                         fsl,pins = <
664                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
665                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
666                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
667                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
668                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
669                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
670                                 /* eMMC RESET */
671                                 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
672                         >;
673                 };
674         };
675 };
676
677 &kpp {
678         pinctrl-names = "default";
679         pinctrl-0 = <&pinctrl_kpp>;
680         /* sample keymap */
681         /* row/col 0,1 are mapped to KPP row/col 6,7 */
682         linux,keymap = <
683                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
684                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
685                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
686                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
687                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
688                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
689                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
690                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
691                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
692                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
693                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
694         >;
695         status = "okay";
696 };
697
698 &lcdif {
699         pinctrl-names = "default";
700         pinctrl-0 = <&pinctrl_disp0_1>;
701         lcd-supply = <&reg_lcd_pwr>;
702         display = <&display>;
703         status = "okay";
704
705         display: display@di0 {
706                 bits-per-pixel = <32>;
707                 bus-width = <24>;
708                 status = "okay";
709
710                 display-timings {
711                         VGA {
712                                 clock-frequency = <25200000>;
713                                 hactive = <640>;
714                                 vactive = <480>;
715                                 hback-porch = <48>;
716                                 hsync-len = <96>;
717                                 hfront-porch = <16>;
718                                 vback-porch = <31>;
719                                 vsync-len = <2>;
720                                 vfront-porch = <12>;
721                                 hsync-active = <0>;
722                                 vsync-active = <0>;
723                                 de-active = <1>;
724                                 pixelclk-active = <0>;
725                         };
726
727                         ETV570 {
728                                 clock-frequency = <25200000>;
729                                 hactive = <640>;
730                                 vactive = <480>;
731                                 hback-porch = <114>;
732                                 hsync-len = <30>;
733                                 hfront-porch = <16>;
734                                 vback-porch = <32>;
735                                 vsync-len = <3>;
736                                 vfront-porch = <10>;
737                                 hsync-active = <0>;
738                                 vsync-active = <0>;
739                                 de-active = <1>;
740                                 pixelclk-active = <0>;
741                         };
742
743                         ET0350 {
744                                 clock-frequency = <6413760>;
745                                 hactive = <320>;
746                                 vactive = <240>;
747                                 hback-porch = <34>;
748                                 hsync-len = <34>;
749                                 hfront-porch = <20>;
750                                 vback-porch = <15>;
751                                 vsync-len = <3>;
752                                 vfront-porch = <4>;
753                                 hsync-active = <0>;
754                                 vsync-active = <0>;
755                                 de-active = <1>;
756                                 pixelclk-active = <0>;
757                         };
758
759                         ET0430 {
760                                 clock-frequency = <9009000>;
761                                 hactive = <480>;
762                                 vactive = <272>;
763                                 hback-porch = <2>;
764                                 hsync-len = <41>;
765                                 hfront-porch = <2>;
766                                 vback-porch = <2>;
767                                 vsync-len = <10>;
768                                 vfront-porch = <2>;
769                                 hsync-active = <0>;
770                                 vsync-active = <0>;
771                                 de-active = <1>;
772                                 pixelclk-active = <1>;
773                         };
774
775                         ET0500 {
776                                 clock-frequency = <33264000>;
777                                 hactive = <800>;
778                                 vactive = <480>;
779                                 hback-porch = <88>;
780                                 hsync-len = <128>;
781                                 hfront-porch = <40>;
782                                 vback-porch = <33>;
783                                 vsync-len = <2>;
784                                 vfront-porch = <10>;
785                                 hsync-active = <0>;
786                                 vsync-active = <0>;
787                                 de-active = <1>;
788                                 pixelclk-active = <0>;
789                         };
790
791                         ET0700 { /* same as ET0500 */
792                                 clock-frequency = <33264000>;
793                                 hactive = <800>;
794                                 vactive = <480>;
795                                 hback-porch = <88>;
796                                 hsync-len = <128>;
797                                 hfront-porch = <40>;
798                                 vback-porch = <33>;
799                                 vsync-len = <2>;
800                                 vfront-porch = <10>;
801                                 hsync-active = <0>;
802                                 vsync-active = <0>;
803                                 de-active = <1>;
804                                 pixelclk-active = <0>;
805                         };
806
807                         ETQ570 {
808                                 clock-frequency = <6596040>;
809                                 hactive = <320>;
810                                 vactive = <240>;
811                                 hback-porch = <38>;
812                                 hsync-len = <30>;
813                                 hfront-porch = <30>;
814                                 vback-porch = <16>;
815                                 vsync-len = <3>;
816                                 vfront-porch = <4>;
817                                 hsync-active = <0>;
818                                 vsync-active = <0>;
819                                 de-active = <1>;
820                                 pixelclk-active = <0>;
821                         };
822                 };
823         };
824 };
825
826 &pwm5 {
827         pinctrl-names = "default";
828         pinctrl-0 = <&pinctrl_pwm5>;
829         #pwm-cells = <3>;
830         status = "okay";
831 };
832
833 &sai2 {
834         pinctrl-names = "default";
835         pinctrl-0 = <&pinctrl_sai2>;
836         status = "okay";
837 };
838
839 &uart1 {
840         pinctrl-names = "default";
841         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
842         status = "okay";
843 };
844
845 &uart2 {
846         pinctrl-names = "default";
847         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
848         status = "okay";
849 };
850
851 &uart5 {
852         pinctrl-names = "default";
853         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
854         status = "okay";
855 };
856
857 &usbotg2 {
858         vbus-supply = <&reg_usbh1_vbus>;
859         dr_mode = "host";
860         disable-over-current;
861         status = "okay";
862 };
863
864 &usbotg1 {
865         vbus-supply = <&reg_usbotg_vbus>;
866         dr_mode = "peripheral";
867         disable-over-current;
868         status = "okay";
869 };
870
871 &usdhc1 {
872         pinctrl-names = "default";
873         pinctrl-0 = <&pinctrl_usdhc1>;
874         bus-width = <4>;
875         no-1-8-v;
876         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
877         fsl,wp-controller;
878         status = "okay";
879 };